1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/usb/pd.h>
7#include "imx8mn.dtsi"
8
9/ {
10	chosen {
11		stdout-path = &uart2;
12	};
13
14	gpio-leds {
15		compatible = "gpio-leds";
16		pinctrl-names = "default";
17		pinctrl-0 = <&pinctrl_gpio_led>;
18
19		status {
20			label = "yellow:status";
21			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22			default-state = "on";
23		};
24	};
25
26	memory@40000000 {
27		device_type = "memory";
28		reg = <0x0 0x40000000 0 0x80000000>;
29	};
30
31	reg_usdhc2_vmmc: regulator-usdhc2 {
32		compatible = "regulator-fixed";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35		regulator-name = "VSD_3V3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39		enable-active-high;
40	};
41
42	ir-receiver {
43		compatible = "gpio-ir-receiver";
44		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_ir>;
47		linux,autosuspend-period = <125>;
48	};
49
50	wm8524: audio-codec {
51		#sound-dai-cells = <0>;
52		compatible = "wlf,wm8524";
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_gpio_wlf>;
55		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
56		clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
57		clock-names = "mclk";
58	};
59
60	sound-wm8524 {
61		compatible = "fsl,imx-audio-wm8524";
62		model = "wm8524-audio";
63		audio-cpu = <&sai3>;
64		audio-codec = <&wm8524>;
65		audio-asrc = <&easrc>;
66		audio-routing =
67			"Line Out Jack", "LINEVOUTL",
68			"Line Out Jack", "LINEVOUTR";
69	};
70
71	sound-spdif {
72		compatible = "fsl,imx-audio-spdif";
73		model = "imx-spdif";
74		spdif-controller = <&spdif1>;
75		spdif-out;
76		spdif-in;
77	};
78};
79
80&easrc {
81	fsl,asrc-rate  = <48000>;
82	status = "okay";
83};
84
85&fec1 {
86	pinctrl-names = "default";
87	pinctrl-0 = <&pinctrl_fec1>;
88	phy-mode = "rgmii-id";
89	phy-handle = <&ethphy0>;
90	fsl,magic-packet;
91	status = "okay";
92
93	mdio {
94		#address-cells = <1>;
95		#size-cells = <0>;
96
97		ethphy0: ethernet-phy@0 {
98			compatible = "ethernet-phy-ieee802.3-c22";
99			reg = <0>;
100		};
101	};
102};
103
104&i2c1 {
105	clock-frequency = <400000>;
106	pinctrl-names = "default";
107	pinctrl-0 = <&pinctrl_i2c1>;
108	status = "okay";
109};
110
111&i2c2 {
112	clock-frequency = <400000>;
113	pinctrl-names = "default";
114	pinctrl-0 = <&pinctrl_i2c2>;
115	status = "okay";
116
117	ptn5110: tcpc@50 {
118		compatible = "nxp,ptn5110";
119		pinctrl-names = "default";
120		pinctrl-0 = <&pinctrl_typec1>;
121		reg = <0x50>;
122		interrupt-parent = <&gpio2>;
123		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
124		status = "okay";
125
126		port {
127			typec1_dr_sw: endpoint {
128				remote-endpoint = <&usb1_drd_sw>;
129			};
130		};
131
132		typec1_con: connector {
133			compatible = "usb-c-connector";
134			label = "USB-C";
135			power-role = "dual";
136			data-role = "dual";
137			try-power-role = "sink";
138			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
139			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
140				     PDO_VAR(5000, 20000, 3000)>;
141			op-sink-microwatt = <15000000>;
142			self-powered;
143		};
144	};
145};
146
147&i2c3 {
148	clock-frequency = <400000>;
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_i2c3>;
151	status = "okay";
152
153	pca6416: gpio@20 {
154		compatible = "ti,tca6416";
155		reg = <0x20>;
156		gpio-controller;
157		#gpio-cells = <2>;
158	};
159};
160
161&sai3 {
162	pinctrl-names = "default";
163	pinctrl-0 = <&pinctrl_sai3>;
164	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
165	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
166	assigned-clock-rates = <24576000>;
167	fsl,sai-mclk-direction-output;
168	status = "okay";
169};
170
171&snvs_pwrkey {
172	status = "okay";
173};
174
175&spdif1 {
176	pinctrl-names = "default";
177	pinctrl-0 = <&pinctrl_spdif1>;
178	assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
179	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
180	assigned-clock-rates = <24576000>;
181	status = "okay";
182};
183
184&uart2 { /* console */
185	pinctrl-names = "default";
186	pinctrl-0 = <&pinctrl_uart2>;
187	status = "okay";
188};
189
190&usbotg1 {
191	dr_mode = "otg";
192	hnp-disable;
193	srp-disable;
194	adp-disable;
195	usb-role-switch;
196	samsung,picophy-pre-emp-curr-control = <3>;
197	samsung,picophy-dc-vol-level-adjust = <7>;
198	status = "okay";
199
200	port {
201		usb1_drd_sw: endpoint {
202			remote-endpoint = <&typec1_dr_sw>;
203		};
204	};
205};
206
207&usdhc2 {
208	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
209	assigned-clock-rates = <200000000>;
210	pinctrl-names = "default", "state_100mhz", "state_200mhz";
211	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
212	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
213	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
214	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
215	bus-width = <4>;
216	vmmc-supply = <&reg_usdhc2_vmmc>;
217	status = "okay";
218};
219
220&usdhc3 {
221	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
222	assigned-clock-rates = <400000000>;
223	pinctrl-names = "default", "state_100mhz", "state_200mhz";
224	pinctrl-0 = <&pinctrl_usdhc3>;
225	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
226	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
227	bus-width = <8>;
228	non-removable;
229	status = "okay";
230};
231
232&wdog1 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_wdog>;
235	fsl,ext-reset-output;
236	status = "okay";
237};
238
239&iomuxc {
240	pinctrl_fec1: fec1grp {
241		fsl,pins = <
242			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
243			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
244			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
245			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
246			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
247			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
248			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
249			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
250			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
251			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
252			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
253			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
254			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
255			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
256			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
257		>;
258	};
259
260	pinctrl_gpio_led: gpioledgrp {
261		fsl,pins = <
262			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
263		>;
264	};
265
266	pinctrl_gpio_wlf: gpiowlfgrp {
267		fsl,pins = <
268			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
269		>;
270	};
271
272	pinctrl_ir: irgrp {
273		fsl,pins = <
274			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
275		>;
276	};
277
278	pinctrl_i2c1: i2c1grp {
279		fsl,pins = <
280			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
281			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
282		>;
283	};
284
285	pinctrl_i2c2: i2c2grp {
286		fsl,pins = <
287			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
288			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
289		>;
290	};
291
292	pinctrl_i2c3: i2c3grp {
293		fsl,pins = <
294			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
295			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
296		>;
297	};
298
299	pinctrl_pmic: pmicirqgrp {
300		fsl,pins = <
301			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
302		>;
303	};
304
305	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
306		fsl,pins = <
307			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
308		>;
309	};
310
311	pinctrl_sai3: sai3grp {
312		fsl,pins = <
313			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
314			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
315			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
316			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
317		>;
318	};
319
320	pinctrl_spdif1: spdif1grp {
321		fsl,pins = <
322			MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
323			MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
324		>;
325	};
326
327	pinctrl_typec1: typec1grp {
328		fsl,pins = <
329			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
330		>;
331	};
332
333	pinctrl_uart2: uart2grp {
334		fsl,pins = <
335			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
336			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
337		>;
338	};
339
340	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
341		fsl,pins = <
342			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
343		>;
344	};
345
346	pinctrl_usdhc2: usdhc2grp {
347		fsl,pins = <
348			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
349			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
350			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
351			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
352			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
353			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
354			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
355		>;
356	};
357
358	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
359		fsl,pins = <
360			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
361			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
362			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
363			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
364			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
365			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
366			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
367		>;
368	};
369
370	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
371		fsl,pins = <
372			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
373			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
374			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
375			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
376			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
377			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
378			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
379		>;
380	};
381
382	pinctrl_usdhc3: usdhc3grp {
383		fsl,pins = <
384			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
385			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
386			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
387			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
388			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
389			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
390			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
391			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
392			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
393			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
394			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
395		>;
396	};
397
398	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
399		fsl,pins = <
400			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
401			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
402			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
403			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
404			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
405			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
406			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
407			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
408			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
409			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
410			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
411		>;
412	};
413
414	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
415		fsl,pins = <
416			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
417			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
418			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
419			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
420			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
421			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
422			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
423			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
424			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
425			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
426			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
427		>;
428	};
429
430	pinctrl_wdog: wdoggrp {
431		fsl,pins = <
432			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
433		>;
434	};
435};
436