1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/clock/imx8-lpcg.h>
8#include <dt-bindings/firmware/imx/rsrc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/pads-imx8qm.h>
12
13/ {
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		mmc0 = &usdhc1;
20		mmc1 = &usdhc2;
21		mmc2 = &usdhc3;
22		serial0 = &lpuart0;
23		serial1 = &lpuart1;
24		serial2 = &lpuart2;
25		serial3 = &lpuart3;
26		vpu_core0 = &vpu_core0;
27		vpu_core1 = &vpu_core1;
28		vpu_core2 = &vpu_core2;
29	};
30
31	cpus {
32		#address-cells = <2>;
33		#size-cells = <0>;
34
35		cpu-map {
36			cluster0 {
37				core0 {
38					cpu = <&A53_0>;
39				};
40				core1 {
41					cpu = <&A53_1>;
42				};
43				core2 {
44					cpu = <&A53_2>;
45				};
46				core3 {
47					cpu = <&A53_3>;
48				};
49			};
50
51			cluster1 {
52				core0 {
53					cpu = <&A72_0>;
54				};
55				core1 {
56					cpu = <&A72_1>;
57				};
58			};
59		};
60
61		A53_0: cpu@0 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a53";
64			reg = <0x0 0x0>;
65			enable-method = "psci";
66			i-cache-size = <0x8000>;
67			i-cache-line-size = <64>;
68			i-cache-sets = <256>;
69			d-cache-size = <0x8000>;
70			d-cache-line-size = <64>;
71			d-cache-sets = <128>;
72			next-level-cache = <&A53_L2>;
73		};
74
75		A53_1: cpu@1 {
76			device_type = "cpu";
77			compatible = "arm,cortex-a53";
78			reg = <0x0 0x1>;
79			enable-method = "psci";
80			i-cache-size = <0x8000>;
81			i-cache-line-size = <64>;
82			i-cache-sets = <256>;
83			d-cache-size = <0x8000>;
84			d-cache-line-size = <64>;
85			d-cache-sets = <128>;
86			next-level-cache = <&A53_L2>;
87		};
88
89		A53_2: cpu@2 {
90			device_type = "cpu";
91			compatible = "arm,cortex-a53";
92			reg = <0x0 0x2>;
93			enable-method = "psci";
94			i-cache-size = <0x8000>;
95			i-cache-line-size = <64>;
96			i-cache-sets = <256>;
97			d-cache-size = <0x8000>;
98			d-cache-line-size = <64>;
99			d-cache-sets = <128>;
100			next-level-cache = <&A53_L2>;
101		};
102
103		A53_3: cpu@3 {
104			device_type = "cpu";
105			compatible = "arm,cortex-a53";
106			reg = <0x0 0x3>;
107			enable-method = "psci";
108			i-cache-size = <0x8000>;
109			i-cache-line-size = <64>;
110			i-cache-sets = <256>;
111			d-cache-size = <0x8000>;
112			d-cache-line-size = <64>;
113			d-cache-sets = <128>;
114			next-level-cache = <&A53_L2>;
115		};
116
117		A72_0: cpu@100 {
118			device_type = "cpu";
119			compatible = "arm,cortex-a72";
120			reg = <0x0 0x100>;
121			enable-method = "psci";
122			i-cache-size = <0xC000>;
123			i-cache-line-size = <64>;
124			i-cache-sets = <256>;
125			d-cache-size = <0x8000>;
126			d-cache-line-size = <64>;
127			d-cache-sets = <256>;
128			next-level-cache = <&A72_L2>;
129		};
130
131		A72_1: cpu@101 {
132			device_type = "cpu";
133			compatible = "arm,cortex-a72";
134			reg = <0x0 0x101>;
135			enable-method = "psci";
136			next-level-cache = <&A72_L2>;
137		};
138
139		A53_L2: l2-cache0 {
140			compatible = "cache";
141			cache-level = <2>;
142			cache-unified;
143			cache-size = <0x100000>;
144			cache-line-size = <64>;
145			cache-sets = <1024>;
146		};
147
148		A72_L2: l2-cache1 {
149			compatible = "cache";
150			cache-level = <2>;
151			cache-unified;
152			cache-size = <0x100000>;
153			cache-line-size = <64>;
154			cache-sets = <1024>;
155		};
156	};
157
158	gic: interrupt-controller@51a00000 {
159		compatible = "arm,gic-v3";
160		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
161		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
162		      <0x0 0x52000000 0 0x2000>,  /* GICC */
163		      <0x0 0x52010000 0 0x1000>,  /* GICH */
164		      <0x0 0x52020000 0 0x20000>; /* GICV */
165		#interrupt-cells = <3>;
166		interrupt-controller;
167		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
168		interrupt-parent = <&gic>;
169	};
170
171	pmu {
172		compatible = "arm,armv8-pmuv3";
173		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
174	};
175
176	psci {
177		compatible = "arm,psci-1.0";
178		method = "smc";
179	};
180
181	timer {
182		compatible = "arm,armv8-timer";
183		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
184			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
185			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
186			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
187	};
188
189	system-controller {
190		compatible = "fsl,imx-scu";
191		mbox-names = "tx0",
192			     "rx0",
193			     "gip3";
194		mboxes = <&lsio_mu1 0 0
195			  &lsio_mu1 1 0
196			  &lsio_mu1 3 3>;
197
198		pd: power-controller {
199			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
200			#power-domain-cells = <1>;
201		};
202
203		clk: clock-controller {
204			compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
205			#clock-cells = <2>;
206		};
207
208		iomuxc: pinctrl {
209			compatible = "fsl,imx8qm-iomuxc";
210		};
211
212		rtc: rtc {
213			compatible = "fsl,imx8qxp-sc-rtc";
214		};
215	};
216
217	/* sorted in register address */
218	#include "imx8-ss-vpu.dtsi"
219	#include "imx8-ss-img.dtsi"
220	#include "imx8-ss-dma.dtsi"
221	#include "imx8-ss-conn.dtsi"
222	#include "imx8-ss-lsio.dtsi"
223};
224
225#include "imx8qm-ss-img.dtsi"
226#include "imx8qm-ss-dma.dtsi"
227#include "imx8qm-ss-conn.dtsi"
228#include "imx8qm-ss-lsio.dtsi"
229