1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8ulp.dtsi"
9
10/ {
11	model = "NXP i.MX8ULP EVK";
12	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
13
14	chosen {
15		stdout-path = &lpuart5;
16	};
17
18	memory@80000000 {
19		device_type = "memory";
20		reg = <0x0 0x80000000 0 0x80000000>;
21	};
22};
23
24&lpuart5 {
25	/* console */
26	pinctrl-names = "default", "sleep";
27	pinctrl-0 = <&pinctrl_lpuart5>;
28	pinctrl-1 = <&pinctrl_lpuart5>;
29	status = "okay";
30};
31
32&usdhc0 {
33	pinctrl-names = "default", "sleep";
34	pinctrl-0 = <&pinctrl_usdhc0>;
35	pinctrl-1 = <&pinctrl_usdhc0>;
36	non-removable;
37	bus-width = <8>;
38	status = "okay";
39};
40
41&iomuxc1 {
42	pinctrl_lpuart5: lpuart5grp {
43		fsl,pins = <
44			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
45			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
46		>;
47	};
48
49	pinctrl_usdhc0: usdhc0grp {
50		fsl,pins = <
51			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
52			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
53			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
54			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
55			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
56			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
57			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
58			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
59			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
60			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
61			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
62		>;
63	};
64};
65