1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6#include <dt-bindings/clock/imx8ulp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/imx8ulp-power.h> 10 11#include "imx8ulp-pinfunc.h" 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 gpio0 = &gpiod; 20 gpio1 = &gpioe; 21 gpio2 = &gpiof; 22 mmc0 = &usdhc0; 23 mmc1 = &usdhc1; 24 mmc2 = &usdhc2; 25 serial0 = &lpuart4; 26 serial1 = &lpuart5; 27 serial2 = &lpuart6; 28 serial3 = &lpuart7; 29 }; 30 31 cpus { 32 #address-cells = <2>; 33 #size-cells = <0>; 34 35 A35_0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a35"; 38 reg = <0x0 0x0>; 39 enable-method = "psci"; 40 next-level-cache = <&A35_L2>; 41 }; 42 43 A35_1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 next-level-cache = <&A35_L2>; 49 }; 50 51 A35_L2: l2-cache0 { 52 compatible = "cache"; 53 }; 54 }; 55 56 gic: interrupt-controller@2d400000 { 57 compatible = "arm,gic-v3"; 58 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ 59 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 60 #interrupt-cells = <3>; 61 interrupt-controller; 62 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0"; 67 method = "smc"; 68 }; 69 70 timer { 71 compatible = "arm,armv8-timer"; 72 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 73 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 74 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 75 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 76 }; 77 78 frosc: clock-frosc { 79 compatible = "fixed-clock"; 80 clock-frequency = <192000000>; 81 clock-output-names = "frosc"; 82 #clock-cells = <0>; 83 }; 84 85 lposc: clock-lposc { 86 compatible = "fixed-clock"; 87 clock-frequency = <1000000>; 88 clock-output-names = "lposc"; 89 #clock-cells = <0>; 90 }; 91 92 rosc: clock-rosc { 93 compatible = "fixed-clock"; 94 clock-frequency = <32768>; 95 clock-output-names = "rosc"; 96 #clock-cells = <0>; 97 }; 98 99 sosc: clock-sosc { 100 compatible = "fixed-clock"; 101 clock-frequency = <24000000>; 102 clock-output-names = "sosc"; 103 #clock-cells = <0>; 104 }; 105 106 sram@2201f000 { 107 compatible = "mmio-sram"; 108 reg = <0x0 0x2201f000 0x0 0x1000>; 109 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges = <0 0x0 0x2201f000 0x1000>; 113 114 scmi_buf: scmi-buf@0 { 115 compatible = "arm,scmi-shmem"; 116 reg = <0x0 0x400>; 117 }; 118 }; 119 120 firmware { 121 scmi { 122 compatible = "arm,scmi-smc"; 123 arm,smc-id = <0xc20000fe>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 shmem = <&scmi_buf>; 127 128 scmi_devpd: protocol@11 { 129 reg = <0x11>; 130 #power-domain-cells = <1>; 131 }; 132 133 scmi_sensor: protocol@15 { 134 reg = <0x15>; 135 #thermal-sensor-cells = <1>; 136 }; 137 }; 138 }; 139 140 soc: soc@0 { 141 compatible = "simple-bus"; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges = <0x0 0x0 0x0 0x40000000>; 145 146 per_bridge3: bus@29000000 { 147 compatible = "simple-bus"; 148 reg = <0x29000000 0x800000>; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges; 152 153 wdog3: watchdog@292a0000 { 154 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; 155 reg = <0x292a0000 0x10000>; 156 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 158 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 159 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; 160 timeout-sec = <40>; 161 }; 162 163 cgc1: clock-controller@292c0000 { 164 compatible = "fsl,imx8ulp-cgc1"; 165 reg = <0x292c0000 0x10000>; 166 clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; 167 clock-names = "rosc", "sosc", "frosc", "lposc"; 168 #clock-cells = <1>; 169 }; 170 171 pcc3: clock-controller@292d0000 { 172 compatible = "fsl,imx8ulp-pcc3"; 173 reg = <0x292d0000 0x10000>; 174 #clock-cells = <1>; 175 #reset-cells = <1>; 176 }; 177 178 tpm5: tpm@29340000 { 179 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; 180 reg = <0x29340000 0x1000>; 181 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&pcc3 IMX8ULP_CLK_TPM5>, 183 <&pcc3 IMX8ULP_CLK_TPM5>; 184 clock-names = "ipg", "per"; 185 status = "disabled"; 186 }; 187 188 lpi2c4: i2c@29370000 { 189 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 190 reg = <0x29370000 0x10000>; 191 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, 193 <&pcc3 IMX8ULP_CLK_LPI2C4>; 194 clock-names = "per", "ipg"; 195 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; 196 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 197 assigned-clock-rates = <48000000>; 198 status = "disabled"; 199 }; 200 201 lpi2c5: i2c@29380000 { 202 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 203 reg = <0x29380000 0x10000>; 204 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, 206 <&pcc3 IMX8ULP_CLK_LPI2C5>; 207 clock-names = "per", "ipg"; 208 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; 209 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 210 assigned-clock-rates = <48000000>; 211 status = "disabled"; 212 }; 213 214 lpuart4: serial@29390000 { 215 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 216 reg = <0x29390000 0x1000>; 217 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; 219 clock-names = "ipg"; 220 status = "disabled"; 221 }; 222 223 lpuart5: serial@293a0000 { 224 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 225 reg = <0x293a0000 0x1000>; 226 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; 228 clock-names = "ipg"; 229 status = "disabled"; 230 }; 231 232 lpspi4: spi@293b0000 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 236 reg = <0x293b0000 0x10000>; 237 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, 239 <&pcc3 IMX8ULP_CLK_LPSPI4>; 240 clock-names = "per", "ipg"; 241 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; 242 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 243 assigned-clock-rates = <16000000>; 244 status = "disabled"; 245 }; 246 247 lpspi5: spi@293c0000 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 251 reg = <0x293c0000 0x10000>; 252 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, 254 <&pcc3 IMX8ULP_CLK_LPSPI5>; 255 clock-names = "per", "ipg"; 256 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; 257 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 258 assigned-clock-rates = <16000000>; 259 status = "disabled"; 260 }; 261 }; 262 263 per_bridge4: bus@29800000 { 264 compatible = "simple-bus"; 265 reg = <0x29800000 0x800000>; 266 #address-cells = <1>; 267 #size-cells = <1>; 268 ranges; 269 270 pcc4: clock-controller@29800000 { 271 compatible = "fsl,imx8ulp-pcc4"; 272 reg = <0x29800000 0x10000>; 273 #clock-cells = <1>; 274 #reset-cells = <1>; 275 }; 276 277 lpi2c6: i2c@29840000 { 278 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 279 reg = <0x29840000 0x10000>; 280 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, 282 <&pcc4 IMX8ULP_CLK_LPI2C6>; 283 clock-names = "per", "ipg"; 284 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; 285 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 286 assigned-clock-rates = <48000000>; 287 status = "disabled"; 288 }; 289 290 lpi2c7: i2c@29850000 { 291 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 292 reg = <0x29850000 0x10000>; 293 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, 295 <&pcc4 IMX8ULP_CLK_LPI2C7>; 296 clock-names = "per", "ipg"; 297 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; 298 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 299 assigned-clock-rates = <48000000>; 300 status = "disabled"; 301 }; 302 303 lpuart6: serial@29860000 { 304 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 305 reg = <0x29860000 0x1000>; 306 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; 308 clock-names = "ipg"; 309 status = "disabled"; 310 }; 311 312 lpuart7: serial@29870000 { 313 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 314 reg = <0x29870000 0x1000>; 315 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; 317 clock-names = "ipg"; 318 status = "disabled"; 319 }; 320 321 iomuxc1: pinctrl@298c0000 { 322 compatible = "fsl,imx8ulp-iomuxc1"; 323 reg = <0x298c0000 0x10000>; 324 }; 325 326 usdhc0: mmc@298d0000 { 327 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 328 reg = <0x298d0000 0x10000>; 329 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 331 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, 332 <&pcc4 IMX8ULP_CLK_USDHC0>; 333 clock-names = "ipg", "ahb", "per"; 334 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; 335 fsl,tuning-start-tap = <20>; 336 fsl,tuning-step = <2>; 337 bus-width = <4>; 338 status = "disabled"; 339 }; 340 341 usdhc1: mmc@298e0000 { 342 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 343 reg = <0x298e0000 0x10000>; 344 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 346 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 347 <&pcc4 IMX8ULP_CLK_USDHC1>; 348 clock-names = "ipg", "ahb", "per"; 349 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; 350 fsl,tuning-start-tap = <20>; 351 fsl,tuning-step = <2>; 352 bus-width = <4>; 353 status = "disabled"; 354 }; 355 356 usdhc2: mmc@298f0000 { 357 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 358 reg = <0x298f0000 0x10000>; 359 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 361 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 362 <&pcc4 IMX8ULP_CLK_USDHC2>; 363 clock-names = "ipg", "ahb", "per"; 364 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 365 fsl,tuning-start-tap = <20>; 366 fsl,tuning-step = <2>; 367 bus-width = <4>; 368 status = "disabled"; 369 }; 370 }; 371 372 gpioe: gpio@2d000080 { 373 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 374 reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; 375 gpio-controller; 376 #gpio-cells = <2>; 377 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, 381 <&pcc4 IMX8ULP_CLK_PCTLE>; 382 clock-names = "gpio", "port"; 383 gpio-ranges = <&iomuxc1 0 32 24>; 384 }; 385 386 gpiof: gpio@2d010080 { 387 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 388 reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; 389 gpio-controller; 390 #gpio-cells = <2>; 391 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, 395 <&pcc4 IMX8ULP_CLK_PCTLF>; 396 clock-names = "gpio", "port"; 397 gpio-ranges = <&iomuxc1 0 64 32>; 398 }; 399 400 per_bridge5: bus@2d800000 { 401 compatible = "simple-bus"; 402 reg = <0x2d800000 0x800000>; 403 #address-cells = <1>; 404 #size-cells = <1>; 405 ranges; 406 407 cgc2: clock-controller@2da60000 { 408 compatible = "fsl,imx8ulp-cgc2"; 409 reg = <0x2da60000 0x10000>; 410 clocks = <&sosc>, <&frosc>; 411 clock-names = "sosc", "frosc"; 412 #clock-cells = <1>; 413 }; 414 415 pcc5: clock-controller@2da70000 { 416 compatible = "fsl,imx8ulp-pcc5"; 417 reg = <0x2da70000 0x10000>; 418 #clock-cells = <1>; 419 #reset-cells = <1>; 420 }; 421 }; 422 423 gpiod: gpio@2e200080 { 424 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 425 reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; 426 gpio-controller; 427 #gpio-cells = <2>; 428 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, 432 <&pcc5 IMX8ULP_CLK_RGPIOD>; 433 clock-names = "gpio", "port"; 434 gpio-ranges = <&iomuxc1 0 0 24>; 435 }; 436 }; 437}; 438