1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi6220 SoC
4 *
5 * Copyright (C) 2015, HiSilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/reset/hisi,hi6220-resets.h>
10#include <dt-bindings/clock/hi6220-clock.h>
11#include <dt-bindings/pinctrl/hisi.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15	compatible = "hisilicon,hi6220";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	psci {
21		compatible = "arm,psci-0.2";
22		method = "smc";
23	};
24
25	cpus {
26		#address-cells = <2>;
27		#size-cells = <0>;
28
29		cpu-map {
30			cluster0 {
31				core0 {
32					cpu = <&cpu0>;
33				};
34				core1 {
35					cpu = <&cpu1>;
36				};
37				core2 {
38					cpu = <&cpu2>;
39				};
40				core3 {
41					cpu = <&cpu3>;
42				};
43			};
44			cluster1 {
45				core0 {
46					cpu = <&cpu4>;
47				};
48				core1 {
49					cpu = <&cpu5>;
50				};
51				core2 {
52					cpu = <&cpu6>;
53				};
54				core3 {
55					cpu = <&cpu7>;
56				};
57			};
58		};
59
60		idle-states {
61			entry-method = "psci";
62
63			CPU_SLEEP: cpu-sleep {
64				compatible = "arm,idle-state";
65				local-timer-stop;
66				arm,psci-suspend-param = <0x0010000>;
67				entry-latency-us = <700>;
68				exit-latency-us = <250>;
69				min-residency-us = <1000>;
70			};
71
72			CLUSTER_SLEEP: cluster-sleep {
73				compatible = "arm,idle-state";
74				local-timer-stop;
75				arm,psci-suspend-param = <0x1010000>;
76				entry-latency-us = <1000>;
77				exit-latency-us = <700>;
78				min-residency-us = <2700>;
79				wakeup-latency-us = <1500>;
80			};
81		};
82
83		cpu0: cpu@0 {
84			compatible = "arm,cortex-a53";
85			device_type = "cpu";
86			reg = <0x0 0x0>;
87			enable-method = "psci";
88			next-level-cache = <&CLUSTER0_L2>;
89			clocks = <&stub_clock 0>;
90			operating-points-v2 = <&cpu_opp_table>;
91			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92			#cooling-cells = <2>; /* min followed by max */
93			dynamic-power-coefficient = <311>;
94		};
95
96		cpu1: cpu@1 {
97			compatible = "arm,cortex-a53";
98			device_type = "cpu";
99			reg = <0x0 0x1>;
100			enable-method = "psci";
101			next-level-cache = <&CLUSTER0_L2>;
102			clocks = <&stub_clock 0>;
103			operating-points-v2 = <&cpu_opp_table>;
104			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105			#cooling-cells = <2>; /* min followed by max */
106			dynamic-power-coefficient = <311>;
107		};
108
109		cpu2: cpu@2 {
110			compatible = "arm,cortex-a53";
111			device_type = "cpu";
112			reg = <0x0 0x2>;
113			enable-method = "psci";
114			next-level-cache = <&CLUSTER0_L2>;
115			clocks = <&stub_clock 0>;
116			operating-points-v2 = <&cpu_opp_table>;
117			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118			#cooling-cells = <2>; /* min followed by max */
119			dynamic-power-coefficient = <311>;
120		};
121
122		cpu3: cpu@3 {
123			compatible = "arm,cortex-a53";
124			device_type = "cpu";
125			reg = <0x0 0x3>;
126			enable-method = "psci";
127			next-level-cache = <&CLUSTER0_L2>;
128			clocks = <&stub_clock 0>;
129			operating-points-v2 = <&cpu_opp_table>;
130			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131			#cooling-cells = <2>; /* min followed by max */
132			dynamic-power-coefficient = <311>;
133		};
134
135		cpu4: cpu@100 {
136			compatible = "arm,cortex-a53";
137			device_type = "cpu";
138			reg = <0x0 0x100>;
139			enable-method = "psci";
140			next-level-cache = <&CLUSTER1_L2>;
141			clocks = <&stub_clock 0>;
142			operating-points-v2 = <&cpu_opp_table>;
143			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144			#cooling-cells = <2>; /* min followed by max */
145			dynamic-power-coefficient = <311>;
146		};
147
148		cpu5: cpu@101 {
149			compatible = "arm,cortex-a53";
150			device_type = "cpu";
151			reg = <0x0 0x101>;
152			enable-method = "psci";
153			next-level-cache = <&CLUSTER1_L2>;
154			clocks = <&stub_clock 0>;
155			operating-points-v2 = <&cpu_opp_table>;
156			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157			#cooling-cells = <2>; /* min followed by max */
158			dynamic-power-coefficient = <311>;
159		};
160
161		cpu6: cpu@102 {
162			compatible = "arm,cortex-a53";
163			device_type = "cpu";
164			reg = <0x0 0x102>;
165			enable-method = "psci";
166			next-level-cache = <&CLUSTER1_L2>;
167			clocks = <&stub_clock 0>;
168			operating-points-v2 = <&cpu_opp_table>;
169			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170			#cooling-cells = <2>; /* min followed by max */
171			dynamic-power-coefficient = <311>;
172		};
173
174		cpu7: cpu@103 {
175			compatible = "arm,cortex-a53";
176			device_type = "cpu";
177			reg = <0x0 0x103>;
178			enable-method = "psci";
179			next-level-cache = <&CLUSTER1_L2>;
180			clocks = <&stub_clock 0>;
181			operating-points-v2 = <&cpu_opp_table>;
182			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183			#cooling-cells = <2>; /* min followed by max */
184			dynamic-power-coefficient = <311>;
185		};
186
187		CLUSTER0_L2: l2-cache0 {
188			compatible = "cache";
189		};
190
191		CLUSTER1_L2: l2-cache1 {
192			compatible = "cache";
193		};
194	};
195
196	cpu_opp_table: opp-table-0 {
197		compatible = "operating-points-v2";
198		opp-shared;
199
200		opp00 {
201			opp-hz = /bits/ 64 <208000000>;
202			opp-microvolt = <1040000>;
203			clock-latency-ns = <500000>;
204		};
205		opp01 {
206			opp-hz = /bits/ 64 <432000000>;
207			opp-microvolt = <1040000>;
208			clock-latency-ns = <500000>;
209		};
210		opp02 {
211			opp-hz = /bits/ 64 <729000000>;
212			opp-microvolt = <1090000>;
213			clock-latency-ns = <500000>;
214		};
215		opp03 {
216			opp-hz = /bits/ 64 <960000000>;
217			opp-microvolt = <1180000>;
218			clock-latency-ns = <500000>;
219		};
220		opp04 {
221			opp-hz = /bits/ 64 <1200000000>;
222			opp-microvolt = <1330000>;
223			clock-latency-ns = <500000>;
224		};
225	};
226
227	gic: interrupt-controller@f6801000 {
228		compatible = "arm,gic-400";
229		reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
230		      <0x0 0xf6802000 0 0x2000>, /* GICC */
231		      <0x0 0xf6804000 0 0x2000>, /* GICH */
232		      <0x0 0xf6806000 0 0x2000>; /* GICV */
233		#address-cells = <0>;
234		#interrupt-cells = <3>;
235		interrupt-controller;
236		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
237	};
238
239	timer {
240		compatible = "arm,armv8-timer";
241		interrupt-parent = <&gic>;
242		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
243			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
244			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
245			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
246	};
247
248	soc {
249		compatible = "simple-bus";
250		#address-cells = <2>;
251		#size-cells = <2>;
252		ranges;
253
254		sram: sram@fff80000 {
255			compatible = "hisilicon,hi6220-sramctrl", "syscon";
256			reg = <0x0 0xfff80000 0x0 0x12000>;
257		};
258
259		ao_ctrl: ao_ctrl@f7800000 {
260			compatible = "hisilicon,hi6220-aoctrl", "syscon";
261			reg = <0x0 0xf7800000 0x0 0x2000>;
262			#clock-cells = <1>;
263			#reset-cells = <1>;
264		};
265
266		sys_ctrl: sys_ctrl@f7030000 {
267			compatible = "hisilicon,hi6220-sysctrl", "syscon";
268			reg = <0x0 0xf7030000 0x0 0x2000>;
269			#clock-cells = <1>;
270			#reset-cells = <1>;
271		};
272
273		media_ctrl: media_ctrl@f4410000 {
274			compatible = "hisilicon,hi6220-mediactrl", "syscon";
275			reg = <0x0 0xf4410000 0x0 0x1000>;
276			#clock-cells = <1>;
277			#reset-cells = <1>;
278		};
279
280		pm_ctrl: pm_ctrl@f7032000 {
281			compatible = "hisilicon,hi6220-pmctrl", "syscon";
282			reg = <0x0 0xf7032000 0x0 0x1000>;
283			#clock-cells = <1>;
284		};
285
286		acpu_sctrl: acpu_sctrl@f6504000 {
287			compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
288			reg = <0x0 0xf6504000 0x0 0x1000>;
289			#clock-cells = <1>;
290		};
291
292		medianoc_ade: medianoc_ade@f4520000 {
293			compatible = "syscon";
294			reg = <0x0 0xf4520000 0x0 0x4000>;
295		};
296
297		stub_clock: stub_clock {
298			compatible = "hisilicon,hi6220-stub-clk";
299			hisilicon,hi6220-clk-sram = <&sram>;
300			#clock-cells = <1>;
301			mbox-names = "mbox-tx";
302			mboxes = <&mailbox 1 0 11>;
303		};
304
305		uart0: serial@f8015000 {	/* console */
306			compatible = "arm,pl011", "arm,primecell";
307			reg = <0x0 0xf8015000 0x0 0x1000>;
308			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
309			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
310				 <&ao_ctrl HI6220_UART0_PCLK>;
311			clock-names = "uartclk", "apb_pclk";
312		};
313
314		uart1: serial@f7111000 {
315			compatible = "arm,pl011", "arm,primecell";
316			reg = <0x0 0xf7111000 0x0 0x1000>;
317			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
318			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
319				 <&sys_ctrl HI6220_UART1_PCLK>;
320			clock-names = "uartclk", "apb_pclk";
321			pinctrl-names = "default";
322			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
323			dmas = <&dma0 8 &dma0 9>;
324			dma-names = "rx", "tx";
325			status = "disabled";
326		};
327
328		uart2: serial@f7112000 {
329			compatible = "arm,pl011", "arm,primecell";
330			reg = <0x0 0xf7112000 0x0 0x1000>;
331			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
332			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
333				 <&sys_ctrl HI6220_UART2_PCLK>;
334			clock-names = "uartclk", "apb_pclk";
335			pinctrl-names = "default";
336			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
337			status = "disabled";
338		};
339
340		uart3: serial@f7113000 {
341			compatible = "arm,pl011", "arm,primecell";
342			reg = <0x0 0xf7113000 0x0 0x1000>;
343			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
344			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
345				 <&sys_ctrl HI6220_UART3_PCLK>;
346			clock-names = "uartclk", "apb_pclk";
347			pinctrl-names = "default";
348			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
349			status = "disabled";
350		};
351
352		uart4: serial@f7114000 {
353			compatible = "arm,pl011", "arm,primecell";
354			reg = <0x0 0xf7114000 0x0 0x1000>;
355			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
356			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
357				 <&sys_ctrl HI6220_UART4_PCLK>;
358			clock-names = "uartclk", "apb_pclk";
359			pinctrl-names = "default";
360			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
361			status = "disabled";
362		};
363
364		dma0: dma@f7370000 {
365			compatible = "hisilicon,k3-dma-1.0";
366			reg = <0x0 0xf7370000 0x0 0x1000>;
367			#dma-cells = <1>;
368			dma-channels = <15>;
369			dma-requests = <32>;
370			interrupts = <0 84 4>;
371			clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
372			dma-no-cci;
373			dma-type = "hi6220_dma";
374			status = "okay";
375		};
376
377		dual_timer0: timer@f8008000 {
378			compatible = "arm,sp804", "arm,primecell";
379			reg = <0x0 0xf8008000 0x0 0x1000>;
380			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
381				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
382			clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
383				 <&ao_ctrl HI6220_TIMER0_PCLK>,
384				 <&ao_ctrl HI6220_TIMER0_PCLK>;
385			clock-names = "timer1", "timer2", "apb_pclk";
386		};
387
388		rtc0: rtc@f8003000 {
389			compatible = "arm,pl031", "arm,primecell";
390			reg = <0x0 0xf8003000 0x0 0x1000>;
391			interrupts = <0 12 4>;
392			clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
393			clock-names = "apb_pclk";
394		};
395
396		rtc1: rtc@f8004000 {
397			compatible = "arm,pl031", "arm,primecell";
398			reg = <0x0 0xf8004000 0x0 0x1000>;
399			interrupts = <0 8 4>;
400			clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
401			clock-names = "apb_pclk";
402		};
403
404		pmx0: pinmux@f7010000 {
405			compatible = "pinctrl-single";
406			reg = <0x0 0xf7010000  0x0 0x27c>;
407			#address-cells = <1>;
408			#size-cells = <1>;
409			#pinctrl-cells = <1>;
410			#gpio-range-cells = <3>;
411			pinctrl-single,register-width = <32>;
412			pinctrl-single,function-mask = <7>;
413			pinctrl-single,gpio-range = <
414				&range  80  8 MUX_M0 /* gpio  3: [0..7] */
415				&range  88  8 MUX_M0 /* gpio  4: [0..7] */
416				&range  96  8 MUX_M0 /* gpio  5: [0..7] */
417				&range 104  8 MUX_M0 /* gpio  6: [0..7] */
418				&range 112  8 MUX_M0 /* gpio  7: [0..7] */
419				&range 120  2 MUX_M0 /* gpio  8: [0..1] */
420				&range   2  6 MUX_M1 /* gpio  8: [2..7] */
421				&range   8  8 MUX_M1 /* gpio  9: [0..7] */
422				&range   0  1 MUX_M1 /* gpio 10: [0]    */
423				&range  16  7 MUX_M1 /* gpio 10: [1..7] */
424				&range  23  3 MUX_M1 /* gpio 11: [0..2] */
425				&range  28  5 MUX_M1 /* gpio 11: [3..7] */
426				&range  33  3 MUX_M1 /* gpio 12: [0..2] */
427				&range  43  5 MUX_M1 /* gpio 12: [3..7] */
428				&range  48  8 MUX_M1 /* gpio 13: [0..7] */
429				&range  56  8 MUX_M1 /* gpio 14: [0..7] */
430				&range  74  6 MUX_M1 /* gpio 15: [0..5] */
431				&range 122  1 MUX_M1 /* gpio 15: [6]    */
432				&range 126  1 MUX_M1 /* gpio 15: [7]    */
433				&range 127  8 MUX_M1 /* gpio 16: [0..7] */
434				&range 135  8 MUX_M1 /* gpio 17: [0..7] */
435				&range 143  8 MUX_M1 /* gpio 18: [0..7] */
436				&range 151  8 MUX_M1 /* gpio 19: [0..7] */
437			>;
438			range: gpio-range {
439				#pinctrl-single,gpio-range-cells = <3>;
440			};
441		};
442
443		pmx1: pinmux@f7010800 {
444			compatible = "pinconf-single";
445			reg = <0x0 0xf7010800 0x0 0x28c>;
446			#address-cells = <1>;
447			#size-cells = <1>;
448			#pinctrl-cells = <1>;
449			pinctrl-single,register-width = <32>;
450		};
451
452		pmx2: pinmux@f8001800 {
453			compatible = "pinconf-single";
454			reg = <0x0 0xf8001800 0x0 0x78>;
455			#address-cells = <1>;
456			#size-cells = <1>;
457			#pinctrl-cells = <1>;
458			pinctrl-single,register-width = <32>;
459		};
460
461		gpio0: gpio@f8011000 {
462			compatible = "arm,pl061", "arm,primecell";
463			reg = <0x0 0xf8011000 0x0 0x1000>;
464			interrupts = <0 52 0x4>;
465			gpio-controller;
466			#gpio-cells = <2>;
467			interrupt-controller;
468			#interrupt-cells = <2>;
469			clocks = <&ao_ctrl 2>;
470			clock-names = "apb_pclk";
471		};
472
473		gpio1: gpio@f8012000 {
474			compatible = "arm,pl061", "arm,primecell";
475			reg = <0x0 0xf8012000 0x0 0x1000>;
476			interrupts = <0 53 0x4>;
477			gpio-controller;
478			#gpio-cells = <2>;
479			interrupt-controller;
480			#interrupt-cells = <2>;
481			clocks = <&ao_ctrl 2>;
482			clock-names = "apb_pclk";
483		};
484
485		gpio2: gpio@f8013000 {
486			compatible = "arm,pl061", "arm,primecell";
487			reg = <0x0 0xf8013000 0x0 0x1000>;
488			interrupts = <0 54 0x4>;
489			gpio-controller;
490			#gpio-cells = <2>;
491			interrupt-controller;
492			#interrupt-cells = <2>;
493			clocks = <&ao_ctrl 2>;
494			clock-names = "apb_pclk";
495		};
496
497		gpio3: gpio@f8014000 {
498			compatible = "arm,pl061", "arm,primecell";
499			reg = <0x0 0xf8014000 0x0 0x1000>;
500			interrupts = <0 55 0x4>;
501			gpio-controller;
502			#gpio-cells = <2>;
503			gpio-ranges = <&pmx0 0 80 8>;
504			interrupt-controller;
505			#interrupt-cells = <2>;
506			clocks = <&ao_ctrl 2>;
507			clock-names = "apb_pclk";
508		};
509
510		gpio4: gpio@f7020000 {
511			compatible = "arm,pl061", "arm,primecell";
512			reg = <0x0 0xf7020000 0x0 0x1000>;
513			interrupts = <0 56 0x4>;
514			gpio-controller;
515			#gpio-cells = <2>;
516			gpio-ranges = <&pmx0 0 88 8>;
517			interrupt-controller;
518			#interrupt-cells = <2>;
519			clocks = <&ao_ctrl 2>;
520			clock-names = "apb_pclk";
521		};
522
523		gpio5: gpio@f7021000 {
524			compatible = "arm,pl061", "arm,primecell";
525			reg = <0x0 0xf7021000 0x0 0x1000>;
526			interrupts = <0 57 0x4>;
527			gpio-controller;
528			#gpio-cells = <2>;
529			gpio-ranges = <&pmx0 0 96 8>;
530			interrupt-controller;
531			#interrupt-cells = <2>;
532			clocks = <&ao_ctrl 2>;
533			clock-names = "apb_pclk";
534		};
535
536		gpio6: gpio@f7022000 {
537			compatible = "arm,pl061", "arm,primecell";
538			reg = <0x0 0xf7022000 0x0 0x1000>;
539			interrupts = <0 58 0x4>;
540			gpio-controller;
541			#gpio-cells = <2>;
542			gpio-ranges = <&pmx0 0 104 8>;
543			interrupt-controller;
544			#interrupt-cells = <2>;
545			clocks = <&ao_ctrl 2>;
546			clock-names = "apb_pclk";
547		};
548
549		gpio7: gpio@f7023000 {
550			compatible = "arm,pl061", "arm,primecell";
551			reg = <0x0 0xf7023000 0x0 0x1000>;
552			interrupts = <0 59 0x4>;
553			gpio-controller;
554			#gpio-cells = <2>;
555			gpio-ranges = <&pmx0 0 112 8>;
556			interrupt-controller;
557			#interrupt-cells = <2>;
558			clocks = <&ao_ctrl 2>;
559			clock-names = "apb_pclk";
560		};
561
562		gpio8: gpio@f7024000 {
563			compatible = "arm,pl061", "arm,primecell";
564			reg = <0x0 0xf7024000 0x0 0x1000>;
565			interrupts = <0 60 0x4>;
566			gpio-controller;
567			#gpio-cells = <2>;
568			gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
569			interrupt-controller;
570			#interrupt-cells = <2>;
571			clocks = <&ao_ctrl 2>;
572			clock-names = "apb_pclk";
573		};
574
575		gpio9: gpio@f7025000 {
576			compatible = "arm,pl061", "arm,primecell";
577			reg = <0x0 0xf7025000 0x0 0x1000>;
578			interrupts = <0 61 0x4>;
579			gpio-controller;
580			#gpio-cells = <2>;
581			gpio-ranges = <&pmx0 0 8 8>;
582			interrupt-controller;
583			#interrupt-cells = <2>;
584			clocks = <&ao_ctrl 2>;
585			clock-names = "apb_pclk";
586		};
587
588		gpio10: gpio@f7026000 {
589			compatible = "arm,pl061", "arm,primecell";
590			reg = <0x0 0xf7026000 0x0 0x1000>;
591			interrupts = <0 62 0x4>;
592			gpio-controller;
593			#gpio-cells = <2>;
594			gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
595			interrupt-controller;
596			#interrupt-cells = <2>;
597			clocks = <&ao_ctrl 2>;
598			clock-names = "apb_pclk";
599		};
600
601		gpio11: gpio@f7027000 {
602			compatible = "arm,pl061", "arm,primecell";
603			reg = <0x0 0xf7027000 0x0 0x1000>;
604			interrupts = <0 63 0x4>;
605			gpio-controller;
606			#gpio-cells = <2>;
607			gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
608			interrupt-controller;
609			#interrupt-cells = <2>;
610			clocks = <&ao_ctrl 2>;
611			clock-names = "apb_pclk";
612		};
613
614		gpio12: gpio@f7028000 {
615			compatible = "arm,pl061", "arm,primecell";
616			reg = <0x0 0xf7028000 0x0 0x1000>;
617			interrupts = <0 64 0x4>;
618			gpio-controller;
619			#gpio-cells = <2>;
620			gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
621			interrupt-controller;
622			#interrupt-cells = <2>;
623			clocks = <&ao_ctrl 2>;
624			clock-names = "apb_pclk";
625		};
626
627		gpio13: gpio@f7029000 {
628			compatible = "arm,pl061", "arm,primecell";
629			reg = <0x0 0xf7029000 0x0 0x1000>;
630			interrupts = <0 65 0x4>;
631			gpio-controller;
632			#gpio-cells = <2>;
633			gpio-ranges = <&pmx0 0 48 8>;
634			interrupt-controller;
635			#interrupt-cells = <2>;
636			clocks = <&ao_ctrl 2>;
637			clock-names = "apb_pclk";
638		};
639
640		gpio14: gpio@f702a000 {
641			compatible = "arm,pl061", "arm,primecell";
642			reg = <0x0 0xf702a000 0x0 0x1000>;
643			interrupts = <0 66 0x4>;
644			gpio-controller;
645			#gpio-cells = <2>;
646			gpio-ranges = <&pmx0 0 56 8>;
647			interrupt-controller;
648			#interrupt-cells = <2>;
649			clocks = <&ao_ctrl 2>;
650			clock-names = "apb_pclk";
651		};
652
653		gpio15: gpio@f702b000 {
654			compatible = "arm,pl061", "arm,primecell";
655			reg = <0x0 0xf702b000 0x0 0x1000>;
656			interrupts = <0 67 0x4>;
657			gpio-controller;
658			#gpio-cells = <2>;
659			gpio-ranges = <
660				&pmx0 0 74 6
661				&pmx0 6 122 1
662				&pmx0 7 126 1
663			>;
664			interrupt-controller;
665			#interrupt-cells = <2>;
666			clocks = <&ao_ctrl 2>;
667			clock-names = "apb_pclk";
668		};
669
670		gpio16: gpio@f702c000 {
671			compatible = "arm,pl061", "arm,primecell";
672			reg = <0x0 0xf702c000 0x0 0x1000>;
673			interrupts = <0 68 0x4>;
674			gpio-controller;
675			#gpio-cells = <2>;
676			gpio-ranges = <&pmx0 0 127 8>;
677			interrupt-controller;
678			#interrupt-cells = <2>;
679			clocks = <&ao_ctrl 2>;
680			clock-names = "apb_pclk";
681		};
682
683		gpio17: gpio@f702d000 {
684			compatible = "arm,pl061", "arm,primecell";
685			reg = <0x0 0xf702d000 0x0 0x1000>;
686			interrupts = <0 69 0x4>;
687			gpio-controller;
688			#gpio-cells = <2>;
689			gpio-ranges = <&pmx0 0 135 8>;
690			interrupt-controller;
691			#interrupt-cells = <2>;
692			clocks = <&ao_ctrl 2>;
693			clock-names = "apb_pclk";
694		};
695
696		gpio18: gpio@f702e000 {
697			compatible = "arm,pl061", "arm,primecell";
698			reg = <0x0 0xf702e000 0x0 0x1000>;
699			interrupts = <0 70 0x4>;
700			gpio-controller;
701			#gpio-cells = <2>;
702			gpio-ranges = <&pmx0 0 143 8>;
703			interrupt-controller;
704			#interrupt-cells = <2>;
705			clocks = <&ao_ctrl 2>;
706			clock-names = "apb_pclk";
707		};
708
709		gpio19: gpio@f702f000 {
710			compatible = "arm,pl061", "arm,primecell";
711			reg = <0x0 0xf702f000 0x0 0x1000>;
712			interrupts = <0 71 0x4>;
713			gpio-controller;
714			#gpio-cells = <2>;
715			gpio-ranges = <&pmx0 0 151 8>;
716			interrupt-controller;
717			#interrupt-cells = <2>;
718			clocks = <&ao_ctrl 2>;
719			clock-names = "apb_pclk";
720		};
721
722		spi0: spi@f7106000 {
723			compatible = "arm,pl022", "arm,primecell";
724			reg = <0x0 0xf7106000 0x0 0x1000>;
725			interrupts = <0 50 4>;
726			bus-id = <0>;
727			enable-dma = <0>;
728			clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
729			clock-names = "sspclk", "apb_pclk";
730			pinctrl-names = "default";
731			pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
732			num-cs = <1>;
733			cs-gpios = <&gpio6 2 0>;
734			status = "disabled";
735		};
736
737		i2c0: i2c@f7100000 {
738			compatible = "snps,designware-i2c";
739			reg = <0x0 0xf7100000 0x0 0x1000>;
740			interrupts = <0 44 4>;
741			clocks = <&sys_ctrl HI6220_I2C0_CLK>;
742			i2c-sda-hold-time-ns = <300>;
743			pinctrl-names = "default";
744			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
745			status = "disabled";
746		};
747
748		i2c1: i2c@f7101000 {
749			compatible = "snps,designware-i2c";
750			reg = <0x0 0xf7101000 0x0 0x1000>;
751			clocks = <&sys_ctrl HI6220_I2C1_CLK>;
752			interrupts = <0 45 4>;
753			i2c-sda-hold-time-ns = <300>;
754			pinctrl-names = "default";
755			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
756			status = "disabled";
757		};
758
759		i2c2: i2c@f7102000 {
760			compatible = "snps,designware-i2c";
761			reg = <0x0 0xf7102000 0x0 0x1000>;
762			clocks = <&sys_ctrl HI6220_I2C2_CLK>;
763			interrupts = <0 46 4>;
764			i2c-sda-hold-time-ns = <300>;
765			pinctrl-names = "default";
766			pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
767			status = "disabled";
768		};
769
770		usb_phy: usbphy {
771			compatible = "hisilicon,hi6220-usb-phy";
772			#phy-cells = <0>;
773			phy-supply = <&reg_5v_hub>;
774			hisilicon,peripheral-syscon = <&sys_ctrl>;
775		};
776
777		usb: usb@f72c0000 {
778			compatible = "hisilicon,hi6220-usb";
779			reg = <0x0 0xf72c0000 0x0 0x40000>;
780			phys = <&usb_phy>;
781			phy-names = "usb2-phy";
782			clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
783			clock-names = "otg";
784			dr_mode = "otg";
785			g-rx-fifo-size = <512>;
786			g-np-tx-fifo-size = <128>;
787			g-tx-fifo-size = <128 128 128 128 128 128 128 128
788					   16  16  16  16  16  16  16>;
789			interrupts = <0 77 0x4>;
790		};
791
792		mailbox: mailbox@f7510000 {
793			compatible = "hisilicon,hi6220-mbox";
794			reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
795			      <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
796			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
797			#mbox-cells = <3>;
798		};
799
800		dwmmc_0: dwmmc0@f723d000 {
801			compatible = "hisilicon,hi6220-dw-mshc";
802			reg = <0x0 0xf723d000 0x0 0x1000>;
803			interrupts = <0x0 0x48 0x4>;
804			clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
805			clock-names = "ciu", "biu";
806			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
807			reset-names = "reset";
808			pinctrl-names = "default";
809			pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
810				     &emmc_cfg_func &emmc_rst_cfg_func>;
811		};
812
813		dwmmc_1: dwmmc1@f723e000 {
814			compatible = "hisilicon,hi6220-dw-mshc";
815			hisilicon,peripheral-syscon = <&ao_ctrl>;
816			reg = <0x0 0xf723e000 0x0 0x1000>;
817			interrupts = <0x0 0x49 0x4>;
818			#address-cells = <0x1>;
819			#size-cells = <0x0>;
820			clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
821			clock-names = "ciu", "biu";
822			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
823			reset-names = "reset";
824			pinctrl-names = "default", "idle";
825			pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
826			pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
827		};
828
829		dwmmc_2: dwmmc2@f723f000 {
830			compatible = "hisilicon,hi6220-dw-mshc";
831			reg = <0x0 0xf723f000 0x0 0x1000>;
832			interrupts = <0x0 0x4a 0x4>;
833			clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
834			clock-names = "ciu", "biu";
835			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
836			reset-names = "reset";
837			pinctrl-names = "default", "idle";
838			pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
839			pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
840		};
841
842		watchdog0: watchdog@f8005000 {
843			compatible = "arm,sp805", "arm,primecell";
844			reg = <0x0 0xf8005000 0x0 0x1000>;
845			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
846			clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
847				 <&ao_ctrl HI6220_WDT0_PCLK>;
848			clock-names = "wdog_clk", "apb_pclk";
849		};
850
851		tsensor: tsensor@0,f7030700 {
852			compatible = "hisilicon,tsensor";
853			reg = <0x0 0xf7030700 0x0 0x1000>;
854			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
855			clocks = <&sys_ctrl 22>;
856			clock-names = "thermal_clk";
857			#thermal-sensor-cells = <1>;
858		};
859
860		i2s0: i2s@f7118000{
861			compatible = "hisilicon,hi6210-i2s";
862			reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
863			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
864			clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
865				 <&sys_ctrl HI6220_BBPPLL0_DIV>;
866			clock-names = "dacodec", "i2s-base";
867			dmas = <&dma0 15 &dma0 14>;
868			dma-names = "rx", "tx";
869			hisilicon,sysctrl-syscon = <&sys_ctrl>;
870			#sound-dai-cells = <1>;
871		};
872
873		thermal-zones {
874
875			cls0: cls0-thermal {
876				polling-delay = <1000>;
877				polling-delay-passive = <100>;
878				sustainable-power = <3326>;
879
880				/* sensor ID */
881				thermal-sensors = <&tsensor 2>;
882
883				trips {
884					threshold: trip-point0 {
885						temperature = <65000>;
886						hysteresis = <0>;
887						type = "passive";
888					};
889
890					target: trip-point1 {
891						temperature = <75000>;
892						hysteresis = <0>;
893						type = "passive";
894					};
895				};
896
897				cooling-maps {
898					map0 {
899						trip = <&target>;
900						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
901								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
902								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
903								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
904								 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
905								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
906								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
907								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
908					};
909				};
910			};
911		};
912
913		ade: ade@f4100000 {
914			compatible = "hisilicon,hi6220-ade";
915			reg = <0x0 0xf4100000 0x0 0x7800>;
916			reg-names = "ade_base";
917			hisilicon,noc-syscon = <&medianoc_ade>;
918			resets = <&media_ctrl MEDIA_ADE>;
919			interrupts = <0 115 4>; /* ldi interrupt */
920
921			clocks = <&media_ctrl HI6220_ADE_CORE>,
922				 <&media_ctrl HI6220_CODEC_JPEG>,
923				 <&media_ctrl HI6220_ADE_PIX_SRC>;
924			/*clock name*/
925			clock-names  = "clk_ade_core",
926				       "clk_codec_jpeg",
927				       "clk_ade_pix";
928
929			assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
930				<&media_ctrl HI6220_CODEC_JPEG>;
931			assigned-clock-rates = <360000000>, <288000000>;
932			dma-coherent;
933			status = "disabled";
934
935			port {
936				ade_out: endpoint {
937					remote-endpoint = <&dsi_in>;
938				};
939			};
940		};
941
942		dsi: dsi@f4107800 {
943			compatible = "hisilicon,hi6220-dsi";
944			reg = <0x0 0xf4107800 0x0 0x100>;
945			clocks = <&media_ctrl  HI6220_DSI_PCLK>;
946			clock-names = "pclk";
947			status = "disabled";
948
949			ports {
950				#address-cells = <1>;
951				#size-cells = <0>;
952
953				/* 0 for input port */
954				port@0 {
955					reg = <0>;
956					dsi_in: endpoint {
957						remote-endpoint = <&ade_out>;
958					};
959				};
960			};
961		};
962
963		debug@f6590000 {
964			compatible = "arm,coresight-cpu-debug","arm,primecell";
965			reg = <0 0xf6590000 0 0x1000>;
966			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
967			clock-names = "apb_pclk";
968			cpu = <&cpu0>;
969		};
970
971		debug@f6592000 {
972			compatible = "arm,coresight-cpu-debug","arm,primecell";
973			reg = <0 0xf6592000 0 0x1000>;
974			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
975			clock-names = "apb_pclk";
976			cpu = <&cpu1>;
977		};
978
979		debug@f6594000 {
980			compatible = "arm,coresight-cpu-debug","arm,primecell";
981			reg = <0 0xf6594000 0 0x1000>;
982			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
983			clock-names = "apb_pclk";
984			cpu = <&cpu2>;
985		};
986
987		debug@f6596000 {
988			compatible = "arm,coresight-cpu-debug","arm,primecell";
989			reg = <0 0xf6596000 0 0x1000>;
990			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
991			clock-names = "apb_pclk";
992			cpu = <&cpu3>;
993		};
994
995		debug@f65d0000 {
996			compatible = "arm,coresight-cpu-debug","arm,primecell";
997			reg = <0 0xf65d0000 0 0x1000>;
998			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
999			clock-names = "apb_pclk";
1000			cpu = <&cpu4>;
1001		};
1002
1003		debug@f65d2000 {
1004			compatible = "arm,coresight-cpu-debug","arm,primecell";
1005			reg = <0 0xf65d2000 0 0x1000>;
1006			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1007			clock-names = "apb_pclk";
1008			cpu = <&cpu5>;
1009		};
1010
1011		debug@f65d4000 {
1012			compatible = "arm,coresight-cpu-debug","arm,primecell";
1013			reg = <0 0xf65d4000 0 0x1000>;
1014			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1015			clock-names = "apb_pclk";
1016			cpu = <&cpu6>;
1017		};
1018
1019		debug@f65d6000 {
1020			compatible = "arm,coresight-cpu-debug","arm,primecell";
1021			reg = <0 0xf65d6000 0 0x1000>;
1022			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1023			clock-names = "apb_pclk";
1024			cpu = <&cpu7>;
1025		};
1026
1027		mali: gpu@f4080000 {
1028			compatible = "hisilicon,hi6220-mali", "arm,mali-450";
1029			reg = <0x0 0xf4080000 0x0 0x00040000>;
1030			interrupt-parent = <&gic>;
1031			interrupts =	<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1032					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1033					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1034					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1035					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1036					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1037					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1038					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1039					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1040					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1041					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
1042
1043			interrupt-names = "gp",
1044					  "gpmmu",
1045					  "pp",
1046					  "pp0",
1047					  "ppmmu0",
1048					  "pp1",
1049					  "ppmmu1",
1050					  "pp2",
1051					  "ppmmu2",
1052					  "pp3",
1053					  "ppmmu3";
1054			clocks = <&media_ctrl HI6220_G3D_CLK>,
1055				 <&media_ctrl HI6220_G3D_PCLK>;
1056			clock-names = "bus", "core";
1057			assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
1058					  <&media_ctrl HI6220_G3D_PCLK>;
1059			assigned-clock-rates = <500000000>, <144000000>;
1060			reset-names = "ao_g3d", "media_g3d";
1061			resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>;
1062		};
1063	};
1064};
1065
1066#include "hi6220-coresight.dtsi"
1067