1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Pinctrl dts file for HiSilicon HiKey970 development board
4 */
5
6#include <dt-bindings/pinctrl/hisi.h>
7
8/ {
9	soc {
10		range: gpio-range {
11			#pinctrl-single,gpio-range-cells = <3>;
12		};
13
14		pmx0: pinmux@e896c000 {
15			compatible = "pinctrl-single";
16			reg = <0x0 0xe896c000 0x0 0x72c>;
17			#pinctrl-cells = <1>;
18			#gpio-range-cells = <0x3>;
19			pinctrl-single,register-width = <0x20>;
20			pinctrl-single,function-mask = <0x7>;
21			/* pin base, nr pins & gpio function */
22			pinctrl-single,gpio-range = <&range 0 82 0>;
23
24			uart0_pmx_func: uart0_pmx_func {
25				pinctrl-single,pins = <
26					0x054 MUX_M2 /* UART0_RXD */
27					0x058 MUX_M2 /* UART0_TXD */
28				>;
29			};
30
31			uart2_pmx_func: uart2_pmx_func {
32				pinctrl-single,pins = <
33					0x700 MUX_M2 /* UART2_CTS_N */
34					0x704 MUX_M2 /* UART2_RTS_N */
35					0x708 MUX_M2 /* UART2_RXD */
36					0x70c MUX_M2 /* UART2_TXD */
37				>;
38			};
39
40			uart3_pmx_func: uart3_pmx_func {
41				pinctrl-single,pins = <
42					0x064 MUX_M1 /* UART3_CTS_N */
43					0x068 MUX_M1 /* UART3_RTS_N */
44					0x06c MUX_M1 /* UART3_RXD */
45					0x070 MUX_M1 /* UART3_TXD */
46				>;
47			};
48
49			uart4_pmx_func: uart4_pmx_func {
50				pinctrl-single,pins = <
51					0x074 MUX_M1 /* UART4_CTS_N */
52					0x078 MUX_M1 /* UART4_RTS_N */
53					0x07c MUX_M1 /* UART4_RXD */
54					0x080 MUX_M1 /* UART4_TXD */
55				>;
56			};
57
58			uart6_pmx_func: uart6_pmx_func {
59				pinctrl-single,pins = <
60					0x05c MUX_M1 /* UART6_RXD */
61					0x060 MUX_M1 /* UART6_TXD */
62				>;
63			};
64
65			i2c3_pmx_func: i2c3_pmx_func {
66				pinctrl-single,pins = <
67					0x010 MUX_M1 /* I2C3_SCL */
68					0x014 MUX_M1 /* I2C3_SDA */
69				>;
70			};
71
72			i2c4_pmx_func: i2c4_pmx_func {
73				pinctrl-single,pins = <
74					0x03c MUX_M1 /* I2C4_SCL */
75					0x040 MUX_M1 /* I2C4_SDA */
76				>;
77			};
78
79			cam0_rst_pmx_func: cam0_rst_pmx_func {
80				pinctrl-single,pins = <
81					0x714 MUX_M0 /* CAM0_RST */
82				>;
83			};
84
85			cam1_rst_pmx_func: cam1_rst_pmx_func {
86				pinctrl-single,pins = <
87					0x048 MUX_M0 /* CAM1_RST */
88				>;
89			};
90
91			cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func {
92				pinctrl-single,pins = <
93					0x098 MUX_M0 /* CAM0_PWD_N */
94				>;
95			};
96
97			cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func {
98				pinctrl-single,pins = <
99					0x044 MUX_M0 /* CAM1_PWD_N */
100				>;
101			};
102
103			isp0_pmx_func: isp0_pmx_func {
104				pinctrl-single,pins = <
105					0x018 MUX_M1 /* ISP_CLK0 */
106					0x024 MUX_M1 /* ISP_SCL0 */
107					0x028 MUX_M1 /* ISP_SDA0 */
108				>;
109			};
110
111			isp1_pmx_func: isp1_pmx_func {
112				pinctrl-single,pins = <
113					0x01c MUX_M1 /* ISP_CLK1 */
114					0x02c MUX_M1 /* ISP_SCL1 */
115					0x030 MUX_M1 /* ISP_SDA1 */
116				>;
117			};
118		};
119
120		pmx1: pinmux@fff11000 {
121			compatible = "pinctrl-single";
122			reg = <0x0 0xfff11000 0x0 0x73c>;
123			#gpio-range-cells = <0x3>;
124			#pinctrl-cells = <1>;
125			pinctrl-single,register-width = <0x20>;
126			pinctrl-single,function-mask = <0x7>;
127			/* pin base, nr pins & gpio function */
128			pinctrl-single,gpio-range = <&range 0 46 0>;
129
130			pwr_key_pmx_func: pwr_key_pmx_func {
131				pinctrl-single,pins = <
132					0x064 MUX_M0 /* GPIO_203 */
133				>;
134			};
135
136			pd_pmx_func: pd_pmx_func{
137				pinctrl-single,pins = <
138					0x080 MUX_M0 /* GPIO_221 */
139				>;
140			};
141
142			i2s2_pmx_func: i2s2_pmx_func {
143			    pinctrl-single,pins = <
144					0x050 MUX_M1 /* I2S2_DI */
145					0x054 MUX_M1 /* I2S2_DO */
146					0x058 MUX_M1 /* I2S2_XCLK */
147					0x05c MUX_M1 /* I2S2_XFS */
148			    >;
149			};
150
151			spi0_pmx_func: spi0_pmx_func {
152				pinctrl-single,pins = <
153					0x094 MUX_M1 /* SPI0_CLK */
154					0x098 MUX_M1 /* SPI0_DI */
155					0x09c MUX_M1 /* SPI0_DO */
156					0x0a0 MUX_M1 /* SPI0_CS0_N */
157				>;
158			};
159
160			spi2_pmx_func: spi2_pmx_func {
161				pinctrl-single,pins = <
162					0x710 MUX_M1 /* SPI2_CLK */
163					0x714 MUX_M1 /* SPI2_DI */
164					0x718 MUX_M1 /* SPI2_DO */
165					0x71c MUX_M1 /* SPI2_CS0_N */
166				>;
167			};
168
169			spi3_pmx_func: spi3_pmx_func {
170				pinctrl-single,pins = <
171					0x72c MUX_M1 /* SPI3_CLK */
172					0x730 MUX_M1 /* SPI3_DI */
173					0x734 MUX_M1 /* SPI3_DO */
174					0x738 MUX_M1 /* SPI3_CS0_N */
175				>;
176			};
177
178			i2c0_pmx_func: i2c0_pmx_func {
179				pinctrl-single,pins = <
180					0x020 MUX_M1 /* I2C0_SCL */
181					0x024 MUX_M1 /* I2C0_SDA */
182				>;
183			};
184
185			i2c1_pmx_func: i2c1_pmx_func {
186				pinctrl-single,pins = <
187					0x028 MUX_M1 /* I2C1_SCL */
188					0x02c MUX_M1 /* I2C1_SDA */
189				>;
190			};
191			i2c2_pmx_func: i2c2_pmx_func {
192				pinctrl-single,pins = <
193					0x030 MUX_M1 /* I2C2_SCL */
194					0x034 MUX_M1 /* I2C2_SDA */
195				>;
196			};
197
198			pcie_clkreq_pmx_func: pcie_clkreq_pmx_func {
199				pinctrl-single,pins = <
200					0x084 MUX_M1 /* PCIE0_CLKREQ_N */
201				>;
202			};
203
204			gpio185_pmx_func: gpio185_pmx_func {
205				pinctrl-single,pins = <0x01C    0x1>;
206			};
207
208			gpio185_pmx_idle: gpio185_pmx_idle {
209				pinctrl-single,pins = <0x01C    0x0>;
210			};
211		};
212
213		pmx2: pinmux@e896c800 {
214			compatible = "pinconf-single";
215			reg = <0x0 0xe896c800 0x0 0x72c>;
216			#pinctrl-cells = <1>;
217			pinctrl-single,register-width = <0x20>;
218
219			uart0_cfg_func: uart0_cfg_func {
220				pinctrl-single,pins = <
221					0x058 0x0 /* UART0_RXD */
222					0x05c 0x0 /* UART0_TXD */
223				>;
224				pinctrl-single,bias-pulldown = <
225					PULL_DIS
226					PULL_DOWN
227					PULL_DIS
228					PULL_DOWN
229				>;
230				pinctrl-single,bias-pullup = <
231					PULL_DIS
232					PULL_UP
233					PULL_DIS
234					PULL_UP
235				>;
236				pinctrl-single,drive-strength = <
237					DRIVE7_04MA DRIVE6_MASK
238				>;
239			};
240
241			uart2_cfg_func: uart2_cfg_func {
242				pinctrl-single,pins = <
243					0x700 0x0 /* UART2_CTS_N */
244					0x704 0x0 /* UART2_RTS_N */
245					0x708 0x0 /* UART2_RXD */
246					0x70c 0x0 /* UART2_TXD */
247				>;
248				pinctrl-single,bias-pulldown = <
249					PULL_DIS
250					PULL_DOWN
251					PULL_DIS
252					PULL_DOWN
253				>;
254				pinctrl-single,bias-pullup = <
255					PULL_DIS
256					PULL_UP
257					PULL_DIS
258					PULL_UP
259				>;
260				pinctrl-single,drive-strength = <
261					DRIVE7_04MA DRIVE6_MASK
262				>;
263			};
264
265			uart3_cfg_func: uart3_cfg_func {
266				pinctrl-single,pins = <
267					0x068 0x0 /* UART3_CTS_N */
268					0x06c 0x0 /* UART3_RTS_N */
269					0x070 0x0 /* UART3_RXD */
270					0x074 0x0 /* UART3_TXD */
271				>;
272				pinctrl-single,bias-pulldown = <
273					PULL_DIS
274					PULL_DOWN
275					PULL_DIS
276					PULL_DOWN
277				>;
278				pinctrl-single,bias-pullup = <
279					PULL_DIS
280					PULL_UP
281					PULL_DIS
282					PULL_UP
283				>;
284				pinctrl-single,drive-strength = <
285					DRIVE7_04MA DRIVE6_MASK
286				>;
287			};
288
289			uart4_cfg_func: uart4_cfg_func {
290				pinctrl-single,pins = <
291					0x078 0x0 /* UART4_CTS_N */
292					0x07c 0x0 /* UART4_RTS_N */
293					0x080 0x0 /* UART4_RXD */
294					0x084 0x0 /* UART4_TXD */
295				>;
296				pinctrl-single,bias-pulldown = <
297					PULL_DIS
298					PULL_DOWN
299					PULL_DIS
300					PULL_DOWN
301				>;
302				pinctrl-single,bias-pullup = <
303					PULL_DIS
304					PULL_UP
305					PULL_DIS
306					PULL_UP
307				>;
308				pinctrl-single,drive-strength = <
309					DRIVE7_04MA DRIVE6_MASK
310				>;
311			};
312
313			uart6_cfg_func: uart6_cfg_func {
314				pinctrl-single,pins = <
315					0x060 0x0 /* UART6_RXD */
316					0x064 0x0 /* UART6_TXD */
317				>;
318				pinctrl-single,bias-pulldown = <
319					PULL_DIS
320					PULL_DOWN
321					PULL_DIS
322					PULL_DOWN
323				>;
324				pinctrl-single,bias-pullup = <
325					PULL_DIS
326					PULL_UP
327					PULL_DIS
328					PULL_UP
329				>;
330				pinctrl-single,drive-strength = <
331					DRIVE7_02MA DRIVE6_MASK
332				>;
333			};
334
335			i2c3_cfg_func: i2c3_cfg_func {
336				pinctrl-single,pins = <
337					0x014 0x0 /* I2C3_SCL */
338					0x018 0x0 /* I2C3_SDA */
339				>;
340				pinctrl-single,bias-pulldown = <
341					PULL_DIS
342					PULL_DOWN
343					PULL_DIS
344					PULL_DOWN
345				>;
346				pinctrl-single,bias-pullup = <
347					PULL_DIS
348					PULL_UP
349					PULL_DIS
350					PULL_UP
351				>;
352				pinctrl-single,drive-strength = <
353					DRIVE7_04MA DRIVE6_MASK
354				>;
355			};
356
357			i2c4_cfg_func: i2c4_cfg_func {
358				pinctrl-single,pins = <
359					0x040 0x0 /* I2C4_SCL */
360					0x044 0x0 /* I2C4_SDA */
361				>;
362				pinctrl-single,bias-pulldown = <
363					PULL_DIS
364					PULL_DOWN
365					PULL_DIS
366					PULL_DOWN
367				>;
368				pinctrl-single,bias-pullup = <
369					PULL_DIS
370					PULL_UP
371					PULL_DIS
372					PULL_UP
373				>;
374				pinctrl-single,drive-strength = <
375					DRIVE7_04MA DRIVE6_MASK
376				>;
377			};
378
379			cam0_rst_cfg_func: cam0_rst_cfg_func {
380				pinctrl-single,pins = <
381					0x714 0x0 /* CAM0_RST */
382				>;
383				pinctrl-single,bias-pulldown = <
384					PULL_DIS
385					PULL_DOWN
386					PULL_DIS
387					PULL_DOWN
388				>;
389				pinctrl-single,bias-pullup = <
390					PULL_DIS
391					PULL_UP
392					PULL_DIS
393					PULL_UP
394				>;
395				pinctrl-single,drive-strength = <
396					DRIVE7_04MA DRIVE6_MASK
397				>;
398			};
399
400			cam1_rst_cfg_func: cam1_rst_cfg_func {
401				pinctrl-single,pins = <
402					0x04C 0x0 /* CAM1_RST */
403				>;
404				pinctrl-single,bias-pulldown = <
405					PULL_DIS
406					PULL_DOWN
407					PULL_DIS
408					PULL_DOWN
409				>;
410				pinctrl-single,bias-pullup = <
411					PULL_DIS
412					PULL_UP
413					PULL_DIS
414					PULL_UP
415				>;
416				pinctrl-single,drive-strength = <
417					DRIVE7_04MA DRIVE6_MASK
418				>;
419			};
420
421			cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func {
422				pinctrl-single,pins = <
423					0x09C 0x0 /* CAM0_PWD_N */
424				>;
425				pinctrl-single,bias-pulldown = <
426					PULL_DIS
427					PULL_DOWN
428					PULL_DIS
429					PULL_DOWN
430				>;
431				pinctrl-single,bias-pullup = <
432					PULL_DIS
433					PULL_UP
434					PULL_DIS
435					PULL_UP
436				>;
437				pinctrl-single,drive-strength = <
438					DRIVE7_04MA DRIVE6_MASK
439				>;
440			};
441
442			cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func {
443				pinctrl-single,pins = <
444					0x048 0x0 /* CAM1_PWD_N */
445				>;
446				pinctrl-single,bias-pulldown = <
447					PULL_DIS
448					PULL_DOWN
449					PULL_DIS
450					PULL_DOWN
451				>;
452				pinctrl-single,bias-pullup = <
453					PULL_DIS
454					PULL_UP
455					PULL_DIS
456					PULL_UP
457				>;
458				pinctrl-single,drive-strength = <
459					DRIVE7_04MA DRIVE6_MASK
460				>;
461			};
462
463			isp0_cfg_func: isp0_cfg_func {
464				pinctrl-single,pins = <
465					0x01C 0x0 /* ISP_CLK0 */
466					0x028 0x0 /* ISP_SCL0 */
467					0x02C 0x0 /* ISP_SDA0 */
468				>;
469				pinctrl-single,bias-pulldown = <
470					PULL_DIS
471					PULL_DOWN
472					PULL_DIS
473					PULL_DOWN
474				>;
475				pinctrl-single,bias-pullup = <
476					PULL_DIS
477					PULL_UP
478					PULL_DIS
479					PULL_UP
480				>;
481				pinctrl-single,drive-strength = <
482					DRIVE7_04MA DRIVE6_MASK
483				>;
484			};
485
486			isp1_cfg_func: isp1_cfg_func {
487				pinctrl-single,pins = <
488					0x020 0x0 /* ISP_CLK1 */
489					0x030 0x0 /* ISP_SCL1 */
490					0x034 0x0 /* ISP_SDA1 */
491				>;
492				pinctrl-single,bias-pulldown = <
493					PULL_DIS
494					PULL_DOWN
495					PULL_DIS
496					PULL_DOWN
497				>;
498				pinctrl-single,bias-pullup = <
499					PULL_DIS
500					PULL_UP
501					PULL_DIS
502					PULL_UP
503				>;
504				pinctrl-single,drive-strength = <
505					DRIVE7_04MA DRIVE6_MASK
506				>;
507			};
508		};
509
510		pmx5: pinmux@fc182000 {
511			compatible = "pinctrl-single";
512			reg = <0x0 0xfc182000 0x0 0x028>;
513			#gpio-range-cells = <3>;
514			#pinctrl-cells = <1>;
515			pinctrl-single,register-width = <0x20>;
516			pinctrl-single,function-mask = <0x7>;
517			/* pin base, nr pins & gpio function */
518			pinctrl-single,gpio-range = <&range 0 10 0>;
519
520			sdio_pmx_func: sdio_pmx_func {
521				pinctrl-single,pins = <
522					0x000 MUX_M1 /* SDIO_CLK */
523					0x004 MUX_M1 /* SDIO_CMD */
524					0x008 MUX_M1 /* SDIO_DATA0 */
525					0x00c MUX_M1 /* SDIO_DATA1 */
526					0x010 MUX_M1 /* SDIO_DATA2 */
527					0x014 MUX_M1 /* SDIO_DATA3 */
528				>;
529			};
530		};
531
532		pmx6: pinmux@fc182800 {
533			compatible = "pinconf-single";
534			reg = <0x0 0xfc182800 0x0 0x028>;
535			#pinctrl-cells = <1>;
536			pinctrl-single,register-width = <0x20>;
537
538			sdio_clk_cfg_func: sdio_clk_cfg_func {
539				pinctrl-single,pins = <
540					0x000 0x0 /* SDIO_CLK */
541				>;
542				pinctrl-single,bias-pulldown = <
543					PULL_DIS
544					PULL_DOWN
545					PULL_DIS
546					PULL_DOWN
547				>;
548				pinctrl-single,bias-pullup = <
549					PULL_DIS
550					PULL_UP
551					PULL_DIS
552					PULL_UP
553				>;
554				pinctrl-single,drive-strength = <
555					DRIVE6_32MA DRIVE6_MASK
556				>;
557			};
558
559			sdio_cfg_func: sdio_cfg_func {
560				pinctrl-single,pins = <
561					0x004 0x0 /* SDIO_CMD */
562					0x008 0x0 /* SDIO_DATA0 */
563					0x00c 0x0 /* SDIO_DATA1 */
564					0x010 0x0 /* SDIO_DATA2 */
565					0x014 0x0 /* SDIO_DATA3 */
566				>;
567				pinctrl-single,bias-pulldown = <
568					PULL_DIS
569					PULL_DOWN
570					PULL_DIS
571					PULL_DOWN
572				>;
573				pinctrl-single,bias-pullup = <
574					PULL_UP
575					PULL_UP
576					PULL_DIS
577					PULL_UP
578				>;
579				pinctrl-single,drive-strength = <
580					DRIVE6_19MA DRIVE6_MASK
581				>;
582			};
583		};
584
585		pmx7: pinmux@ff37e000 {
586			compatible = "pinctrl-single";
587			reg = <0x0 0xff37e000 0x0 0x030>;
588			#gpio-range-cells = <3>;
589			#pinctrl-cells = <1>;
590			pinctrl-single,register-width = <0x20>;
591			pinctrl-single,function-mask = <7>;
592			/* pin base, nr pins & gpio function */
593			pinctrl-single,gpio-range = <&range 0 12 0>;
594
595			sd_pmx_func: sd_pmx_func {
596				pinctrl-single,pins = <
597					0x000 MUX_M1 /* SD_CLK */
598					0x004 MUX_M1 /* SD_CMD */
599					0x008 MUX_M1 /* SD_DATA0 */
600					0x00c MUX_M1 /* SD_DATA1 */
601					0x010 MUX_M1 /* SD_DATA2 */
602					0x014 MUX_M1 /* SD_DATA3 */
603				>;
604			};
605		};
606
607		pmx8: pinmux@ff37e800 {
608			compatible = "pinconf-single";
609			reg = <0x0 0xff37e800 0x0 0x030>;
610			#pinctrl-cells = <1>;
611			pinctrl-single,register-width = <0x20>;
612
613			sd_clk_cfg_func: sd_clk_cfg_func {
614				pinctrl-single,pins = <
615					0x000 0x0 /* SD_CLK */
616				>;
617				pinctrl-single,bias-pulldown = <
618					PULL_DIS
619					PULL_DOWN
620					PULL_DIS
621					PULL_DOWN
622				>;
623				pinctrl-single,bias-pullup = <
624					PULL_DIS
625					PULL_UP
626					PULL_DIS
627					PULL_UP
628				>;
629				pinctrl-single,drive-strength = <
630					DRIVE6_32MA
631					DRIVE6_MASK
632				>;
633			};
634
635			sd_cfg_func: sd_cfg_func {
636				pinctrl-single,pins = <
637					0x004 0x0 /* SD_CMD */
638					0x008 0x0 /* SD_DATA0 */
639					0x00c 0x0 /* SD_DATA1 */
640					0x010 0x0 /* SD_DATA2 */
641					0x014 0x0 /* SD_DATA3 */
642				>;
643				pinctrl-single,bias-pulldown = <
644					PULL_DIS
645					PULL_DOWN
646					PULL_DIS
647					PULL_DOWN
648				>;
649				pinctrl-single,bias-pullup = <
650					PULL_UP
651					PULL_UP
652					PULL_DIS
653					PULL_UP
654				>;
655				pinctrl-single,drive-strength = <
656					DRIVE6_19MA
657					DRIVE6_MASK
658				>;
659			};
660		};
661
662		pmx16: pinmux@fff11800 {
663			compatible = "pinconf-single";
664			reg = <0x0 0xfff11800 0x0 0x73c>;
665			#pinctrl-cells = <1>;
666			pinctrl-single,register-width = <0x20>;
667
668			pwr_key_cfg_func: pwr_key_cfg_func {
669				pinctrl-single,pins = <
670					0x090 0x0 /* GPIO_203 */
671				>;
672				pinctrl-single,bias-pulldown = <
673					PULL_DIS
674					PULL_DOWN
675					PULL_DIS
676					PULL_DOWN
677				>;
678				pinctrl-single,bias-pullup = <
679					PULL_UP
680					PULL_UP
681					PULL_DIS
682					PULL_UP
683				>;
684				pinctrl-single,drive-strength = <
685					DRIVE7_02MA DRIVE6_MASK
686				>;
687			};
688
689			usb_cfg_func: usb_cfg_func {
690				pinctrl-single,pins = <
691					0x0AC 0x0 /* GPIO_221 */
692				>;
693				pinctrl-single,bias-pulldown  = <
694					PULL_DIS
695					PULL_DOWN
696					PULL_DIS
697					PULL_DOWN
698				>;
699				pinctrl-single,bias-pullup    = <
700					PULL_UP
701					PULL_UP
702					PULL_DIS
703					PULL_UP
704				>;
705				pinctrl-single,drive-strength = <
706					DRIVE7_02MA DRIVE6_MASK
707				>;
708			};
709
710			spi0_cfg_func: spi0_cfg_func {
711				pinctrl-single,pins = <
712					0x0c8 0x0 /* SPI0_DI */
713					0x0cc 0x0 /* SPI0_DO */
714					0x0d0 0x0 /* SPI0_CS0_N */
715				>;
716				pinctrl-single,bias-pulldown = <
717					PULL_DIS
718					PULL_DOWN
719					PULL_DIS
720					PULL_DOWN
721				>;
722				pinctrl-single,bias-pullup = <
723					PULL_DIS
724					PULL_UP
725					PULL_DIS
726					PULL_UP
727				>;
728				pinctrl-single,drive-strength = <
729					DRIVE7_06MA DRIVE6_MASK
730				>;
731			};
732
733			spi2_cfg_func: spi2_cfg_func {
734				pinctrl-single,pins = <
735					0x714 0x0 /* SPI2_DI */
736					0x718 0x0 /* SPI2_DO */
737					0x71c 0x0 /* SPI2_CS0_N */
738				>;
739				pinctrl-single,bias-pulldown = <
740					PULL_DIS
741					PULL_DOWN
742					PULL_DIS
743					PULL_DOWN
744				>;
745				pinctrl-single,bias-pullup = <
746					PULL_DIS
747					PULL_UP
748					PULL_DIS
749					PULL_UP
750				>;
751				pinctrl-single,drive-strength = <
752					DRIVE7_06MA DRIVE6_MASK
753				>;
754			};
755
756			spi3_cfg_func: spi3_cfg_func {
757				pinctrl-single,pins = <
758					0x730 0x0 /* SPI3_DI */
759					0x734 0x0 /* SPI3_DO */
760					0x738 0x0 /* SPI3_CS0_N */
761				>;
762				pinctrl-single,bias-pulldown = <
763					PULL_DIS
764					PULL_DOWN
765					PULL_DIS
766					PULL_DOWN
767				>;
768				pinctrl-single,bias-pullup = <
769					PULL_DIS
770					PULL_UP
771					PULL_DIS
772					PULL_UP
773				>;
774				pinctrl-single,drive-strength = <
775					DRIVE7_06MA DRIVE6_MASK
776				>;
777			};
778
779			spi0_clk_cfg_func: spi0_clk_cfg_func {
780				pinctrl-single,pins = <
781					0x0c4 0x0 /* SPI0_CLK */
782				>;
783				pinctrl-single,bias-pulldown = <
784					PULL_DIS
785					PULL_DOWN
786					PULL_DIS
787					PULL_DOWN
788				>;
789				pinctrl-single,bias-pullup = <
790					PULL_DIS
791					PULL_UP
792					PULL_DIS
793					PULL_UP
794				>;
795				pinctrl-single,drive-strength = <
796					DRIVE7_10MA DRIVE6_MASK
797				>;
798			};
799
800			spi2_clk_cfg_func: spi2_clk_cfg_func {
801				pinctrl-single,pins = <
802					0x710 0x0 /* SPI2_CLK */
803				>;
804				pinctrl-single,bias-pulldown = <
805					PULL_DIS
806					PULL_DOWN
807					PULL_DIS
808					PULL_DOWN
809				>;
810				pinctrl-single,bias-pullup = <
811					PULL_DIS
812					PULL_UP
813					PULL_DIS
814					PULL_UP
815				>;
816				pinctrl-single,drive-strength = <
817					DRIVE7_10MA DRIVE6_MASK
818				>;
819			};
820
821			spi3_clk_cfg_func: spi3_clk_cfg_func {
822				pinctrl-single,pins = <
823					0x72c 0x0 /* SPI3_CLK */
824				>;
825				pinctrl-single,bias-pulldown = <
826					PULL_DIS
827					PULL_DOWN
828					PULL_DIS
829					PULL_DOWN
830				>;
831				pinctrl-single,bias-pullup = <
832					PULL_DIS
833					PULL_UP
834					PULL_DIS
835					PULL_UP
836				>;
837				pinctrl-single,drive-strength = <
838					DRIVE7_10MA DRIVE6_MASK
839				>;
840			};
841
842			i2c0_cfg_func: i2c0_cfg_func {
843				pinctrl-single,pins = <
844					0x04c 0x0 /* I2C0_SCL */
845					0x050 0x0 /* I2C0_SDA */
846				>;
847				pinctrl-single,bias-pulldown = <
848					PULL_DIS
849					PULL_DOWN
850					PULL_DIS
851					PULL_DOWN
852				>;
853				pinctrl-single,bias-pullup = <
854					PULL_DIS
855					PULL_UP
856					PULL_DIS
857					PULL_UP
858				>;
859				pinctrl-single,drive-strength = <
860					DRIVE7_04MA DRIVE6_MASK
861				>;
862			};
863
864			i2c1_cfg_func: i2c1_cfg_func {
865				pinctrl-single,pins = <
866					0x054 0x0 /* I2C1_SCL */
867					0x058 0x0 /* I2C1_SDA */
868				>;
869				pinctrl-single,bias-pulldown = <
870					PULL_DIS
871					PULL_DOWN
872					PULL_DIS
873					PULL_DOWN
874				>;
875				pinctrl-single,bias-pullup = <
876					PULL_DIS
877					PULL_UP
878					PULL_DIS
879					PULL_UP
880				>;
881				pinctrl-single,drive-strength = <
882					DRIVE7_04MA DRIVE6_MASK
883				>;
884			};
885
886			i2c2_cfg_func: i2c2_cfg_func {
887				pinctrl-single,pins = <
888					0x05c 0x0 /* I2C2_SCL */
889					0x060 0x0 /* I2C2_SDA */
890				>;
891				pinctrl-single,bias-pulldown = <
892					PULL_DIS
893					PULL_DOWN
894					PULL_DIS
895					PULL_DOWN
896				>;
897				pinctrl-single,bias-pullup = <
898					PULL_DIS
899					PULL_UP
900					PULL_DIS
901					PULL_UP
902				>;
903				pinctrl-single,drive-strength = <
904					DRIVE7_04MA DRIVE6_MASK
905				>;
906			};
907
908			pcie_clkreq_cfg_func: pcie_clkreq_cfg_func {
909				pinctrl-single,pins = <
910					0x0b0 0x0
911				>;
912				pinctrl-single,bias-pulldown = <
913					PULL_DIS
914					PULL_DOWN
915					PULL_DIS
916					PULL_DOWN
917				>;
918				pinctrl-single,bias-pullup = <
919					PULL_DIS
920					PULL_UP
921					PULL_DIS
922					PULL_UP
923				>;
924				pinctrl-single,drive-strength = <
925					DRIVE7_06MA DRIVE6_MASK
926				>;
927			};
928			i2s2_cfg_func: i2s2_cfg_func {
929				pinctrl-single,pins = <
930					0x07c 0x0 /* I2S2_DI */
931					0x080 0x0 /* I2S2_DO */
932					0x084 0x0 /* I2S2_XCLK */
933					0x088 0x0 /* I2S2_XFS */
934				>;
935				pinctrl-single,bias-pulldown = <
936					PULL_DIS
937					PULL_DOWN
938					PULL_DIS
939					PULL_DOWN
940				>;
941				pinctrl-single,bias-pullup = <
942					PULL_UP
943					PULL_UP
944					PULL_DIS
945					PULL_UP
946				>;
947				pinctrl-single,drive-strength = <
948					DRIVE7_02MA DRIVE6_MASK
949				>;
950			};
951
952			gpio185_cfg_func: gpio185_cfg_func {
953				pinctrl-single,pins = <0x048  0>;
954				pinctrl-single,bias-pulldown = <0 2 0 2>;
955				pinctrl-single,bias-pullup = <0 1 0 1>;
956				pinctrl-single,drive-strength = <0x00 0x70>;
957				pinctrl-single,slew-rate = <0x0 0x80>;
958			};
959
960			gpio185_cfg_idle: gpio185_cfg_idle {
961				pinctrl-single,pins = <0x048  0>;
962				pinctrl-single,bias-pulldown = <2 2 0 2>;
963				pinctrl-single,bias-pullup = <0 1 0 1>;
964				pinctrl-single,drive-strength = <0x00 0x70>;
965				pinctrl-single,slew-rate = <0x0 0x80>;
966			};
967		};
968	};
969};
970