1// SPDX-License-Identifier: GPL-2.0-only
2/**
3 * dts file for Hisilicon D05 Development Board
4 *
5 * Copyright (C) 2016 HiSilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	compatible = "hisilicon,hip07-d05";
12	interrupt-parent = <&gic>;
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	psci {
17		compatible = "arm,psci-0.2";
18		method = "smc";
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu-map {
26			cluster0 {
27				core0 {
28					cpu = <&cpu0>;
29				};
30				core1 {
31					cpu = <&cpu1>;
32				};
33				core2 {
34					cpu = <&cpu2>;
35				};
36				core3 {
37					cpu = <&cpu3>;
38				};
39			};
40
41			cluster1 {
42				core0 {
43					cpu = <&cpu4>;
44				};
45				core1 {
46					cpu = <&cpu5>;
47				};
48				core2 {
49					cpu = <&cpu6>;
50				};
51				core3 {
52					cpu = <&cpu7>;
53				};
54			};
55
56			cluster2 {
57				core0 {
58					cpu = <&cpu8>;
59				};
60				core1 {
61					cpu = <&cpu9>;
62				};
63				core2 {
64					cpu = <&cpu10>;
65				};
66				core3 {
67					cpu = <&cpu11>;
68				};
69			};
70
71			cluster3 {
72				core0 {
73					cpu = <&cpu12>;
74				};
75				core1 {
76					cpu = <&cpu13>;
77				};
78				core2 {
79					cpu = <&cpu14>;
80				};
81				core3 {
82					cpu = <&cpu15>;
83				};
84			};
85
86			cluster4 {
87				core0 {
88					cpu = <&cpu16>;
89				};
90				core1 {
91					cpu = <&cpu17>;
92				};
93				core2 {
94					cpu = <&cpu18>;
95				};
96				core3 {
97					cpu = <&cpu19>;
98				};
99			};
100
101			cluster5 {
102				core0 {
103					cpu = <&cpu20>;
104				};
105				core1 {
106					cpu = <&cpu21>;
107				};
108				core2 {
109					cpu = <&cpu22>;
110				};
111				core3 {
112					cpu = <&cpu23>;
113				};
114			};
115
116			cluster6 {
117				core0 {
118					cpu = <&cpu24>;
119				};
120				core1 {
121					cpu = <&cpu25>;
122				};
123				core2 {
124					cpu = <&cpu26>;
125				};
126				core3 {
127					cpu = <&cpu27>;
128				};
129			};
130
131			cluster7 {
132				core0 {
133					cpu = <&cpu28>;
134				};
135				core1 {
136					cpu = <&cpu29>;
137				};
138				core2 {
139					cpu = <&cpu30>;
140				};
141				core3 {
142					cpu = <&cpu31>;
143				};
144			};
145
146			cluster8 {
147				core0 {
148					cpu = <&cpu32>;
149				};
150				core1 {
151					cpu = <&cpu33>;
152				};
153				core2 {
154					cpu = <&cpu34>;
155				};
156				core3 {
157					cpu = <&cpu35>;
158				};
159			};
160
161			cluster9 {
162				core0 {
163					cpu = <&cpu36>;
164				};
165				core1 {
166					cpu = <&cpu37>;
167				};
168				core2 {
169					cpu = <&cpu38>;
170				};
171				core3 {
172					cpu = <&cpu39>;
173				};
174			};
175
176			cluster10 {
177				core0 {
178					cpu = <&cpu40>;
179				};
180				core1 {
181					cpu = <&cpu41>;
182				};
183				core2 {
184					cpu = <&cpu42>;
185				};
186				core3 {
187					cpu = <&cpu43>;
188				};
189			};
190
191			cluster11 {
192				core0 {
193					cpu = <&cpu44>;
194				};
195				core1 {
196					cpu = <&cpu45>;
197				};
198				core2 {
199					cpu = <&cpu46>;
200				};
201				core3 {
202					cpu = <&cpu47>;
203				};
204			};
205
206			cluster12 {
207				core0 {
208					cpu = <&cpu48>;
209				};
210				core1 {
211					cpu = <&cpu49>;
212				};
213				core2 {
214					cpu = <&cpu50>;
215				};
216				core3 {
217					cpu = <&cpu51>;
218				};
219			};
220
221			cluster13 {
222				core0 {
223					cpu = <&cpu52>;
224				};
225				core1 {
226					cpu = <&cpu53>;
227				};
228				core2 {
229					cpu = <&cpu54>;
230				};
231				core3 {
232					cpu = <&cpu55>;
233				};
234			};
235
236			cluster14 {
237				core0 {
238					cpu = <&cpu56>;
239				};
240				core1 {
241					cpu = <&cpu57>;
242				};
243				core2 {
244					cpu = <&cpu58>;
245				};
246				core3 {
247					cpu = <&cpu59>;
248				};
249			};
250
251			cluster15 {
252				core0 {
253					cpu = <&cpu60>;
254				};
255				core1 {
256					cpu = <&cpu61>;
257				};
258				core2 {
259					cpu = <&cpu62>;
260				};
261				core3 {
262					cpu = <&cpu63>;
263				};
264			};
265		};
266
267		cpu0: cpu@10000 {
268			device_type = "cpu";
269			compatible = "arm,cortex-a72";
270			reg = <0x10000>;
271			enable-method = "psci";
272			next-level-cache = <&cluster0_l2>;
273			numa-node-id = <0>;
274		};
275
276		cpu1: cpu@10001 {
277			device_type = "cpu";
278			compatible = "arm,cortex-a72";
279			reg = <0x10001>;
280			enable-method = "psci";
281			next-level-cache = <&cluster0_l2>;
282			numa-node-id = <0>;
283		};
284
285		cpu2: cpu@10002 {
286			device_type = "cpu";
287			compatible = "arm,cortex-a72";
288			reg = <0x10002>;
289			enable-method = "psci";
290			next-level-cache = <&cluster0_l2>;
291			numa-node-id = <0>;
292		};
293
294		cpu3: cpu@10003 {
295			device_type = "cpu";
296			compatible = "arm,cortex-a72";
297			reg = <0x10003>;
298			enable-method = "psci";
299			next-level-cache = <&cluster0_l2>;
300			numa-node-id = <0>;
301		};
302
303		cpu4: cpu@10100 {
304			device_type = "cpu";
305			compatible = "arm,cortex-a72";
306			reg = <0x10100>;
307			enable-method = "psci";
308			next-level-cache = <&cluster1_l2>;
309			numa-node-id = <0>;
310		};
311
312		cpu5: cpu@10101 {
313			device_type = "cpu";
314			compatible = "arm,cortex-a72";
315			reg = <0x10101>;
316			enable-method = "psci";
317			next-level-cache = <&cluster1_l2>;
318			numa-node-id = <0>;
319		};
320
321		cpu6: cpu@10102 {
322			device_type = "cpu";
323			compatible = "arm,cortex-a72";
324			reg = <0x10102>;
325			enable-method = "psci";
326			next-level-cache = <&cluster1_l2>;
327			numa-node-id = <0>;
328		};
329
330		cpu7: cpu@10103 {
331			device_type = "cpu";
332			compatible = "arm,cortex-a72";
333			reg = <0x10103>;
334			enable-method = "psci";
335			next-level-cache = <&cluster1_l2>;
336			numa-node-id = <0>;
337		};
338
339		cpu8: cpu@10200 {
340			device_type = "cpu";
341			compatible = "arm,cortex-a72";
342			reg = <0x10200>;
343			enable-method = "psci";
344			next-level-cache = <&cluster2_l2>;
345			numa-node-id = <0>;
346		};
347
348		cpu9: cpu@10201 {
349			device_type = "cpu";
350			compatible = "arm,cortex-a72";
351			reg = <0x10201>;
352			enable-method = "psci";
353			next-level-cache = <&cluster2_l2>;
354			numa-node-id = <0>;
355		};
356
357		cpu10: cpu@10202 {
358			device_type = "cpu";
359			compatible = "arm,cortex-a72";
360			reg = <0x10202>;
361			enable-method = "psci";
362			next-level-cache = <&cluster2_l2>;
363			numa-node-id = <0>;
364		};
365
366		cpu11: cpu@10203 {
367			device_type = "cpu";
368			compatible = "arm,cortex-a72";
369			reg = <0x10203>;
370			enable-method = "psci";
371			next-level-cache = <&cluster2_l2>;
372			numa-node-id = <0>;
373		};
374
375		cpu12: cpu@10300 {
376			device_type = "cpu";
377			compatible = "arm,cortex-a72";
378			reg = <0x10300>;
379			enable-method = "psci";
380			next-level-cache = <&cluster3_l2>;
381			numa-node-id = <0>;
382		};
383
384		cpu13: cpu@10301 {
385			device_type = "cpu";
386			compatible = "arm,cortex-a72";
387			reg = <0x10301>;
388			enable-method = "psci";
389			next-level-cache = <&cluster3_l2>;
390			numa-node-id = <0>;
391		};
392
393		cpu14: cpu@10302 {
394			device_type = "cpu";
395			compatible = "arm,cortex-a72";
396			reg = <0x10302>;
397			enable-method = "psci";
398			next-level-cache = <&cluster3_l2>;
399			numa-node-id = <0>;
400		};
401
402		cpu15: cpu@10303 {
403			device_type = "cpu";
404			compatible = "arm,cortex-a72";
405			reg = <0x10303>;
406			enable-method = "psci";
407			next-level-cache = <&cluster3_l2>;
408			numa-node-id = <0>;
409		};
410
411		cpu16: cpu@30000 {
412			device_type = "cpu";
413			compatible = "arm,cortex-a72";
414			reg = <0x30000>;
415			enable-method = "psci";
416			next-level-cache = <&cluster4_l2>;
417			numa-node-id = <1>;
418		};
419
420		cpu17: cpu@30001 {
421			device_type = "cpu";
422			compatible = "arm,cortex-a72";
423			reg = <0x30001>;
424			enable-method = "psci";
425			next-level-cache = <&cluster4_l2>;
426			numa-node-id = <1>;
427		};
428
429		cpu18: cpu@30002 {
430			device_type = "cpu";
431			compatible = "arm,cortex-a72";
432			reg = <0x30002>;
433			enable-method = "psci";
434			next-level-cache = <&cluster4_l2>;
435			numa-node-id = <1>;
436		};
437
438		cpu19: cpu@30003 {
439			device_type = "cpu";
440			compatible = "arm,cortex-a72";
441			reg = <0x30003>;
442			enable-method = "psci";
443			next-level-cache = <&cluster4_l2>;
444			numa-node-id = <1>;
445		};
446
447		cpu20: cpu@30100 {
448			device_type = "cpu";
449			compatible = "arm,cortex-a72";
450			reg = <0x30100>;
451			enable-method = "psci";
452			next-level-cache = <&cluster5_l2>;
453			numa-node-id = <1>;
454		};
455
456		cpu21: cpu@30101 {
457			device_type = "cpu";
458			compatible = "arm,cortex-a72";
459			reg = <0x30101>;
460			enable-method = "psci";
461			next-level-cache = <&cluster5_l2>;
462			numa-node-id = <1>;
463		};
464
465		cpu22: cpu@30102 {
466			device_type = "cpu";
467			compatible = "arm,cortex-a72";
468			reg = <0x30102>;
469			enable-method = "psci";
470			next-level-cache = <&cluster5_l2>;
471			numa-node-id = <1>;
472		};
473
474		cpu23: cpu@30103 {
475			device_type = "cpu";
476			compatible = "arm,cortex-a72";
477			reg = <0x30103>;
478			enable-method = "psci";
479			next-level-cache = <&cluster5_l2>;
480			numa-node-id = <1>;
481		};
482
483		cpu24: cpu@30200 {
484			device_type = "cpu";
485			compatible = "arm,cortex-a72";
486			reg = <0x30200>;
487			enable-method = "psci";
488			next-level-cache = <&cluster6_l2>;
489			numa-node-id = <1>;
490		};
491
492		cpu25: cpu@30201 {
493			device_type = "cpu";
494			compatible = "arm,cortex-a72";
495			reg = <0x30201>;
496			enable-method = "psci";
497			next-level-cache = <&cluster6_l2>;
498			numa-node-id = <1>;
499		};
500
501		cpu26: cpu@30202 {
502			device_type = "cpu";
503			compatible = "arm,cortex-a72";
504			reg = <0x30202>;
505			enable-method = "psci";
506			next-level-cache = <&cluster6_l2>;
507			numa-node-id = <1>;
508		};
509
510		cpu27: cpu@30203 {
511			device_type = "cpu";
512			compatible = "arm,cortex-a72";
513			reg = <0x30203>;
514			enable-method = "psci";
515			next-level-cache = <&cluster6_l2>;
516			numa-node-id = <1>;
517		};
518
519		cpu28: cpu@30300 {
520			device_type = "cpu";
521			compatible = "arm,cortex-a72";
522			reg = <0x30300>;
523			enable-method = "psci";
524			next-level-cache = <&cluster7_l2>;
525			numa-node-id = <1>;
526		};
527
528		cpu29: cpu@30301 {
529			device_type = "cpu";
530			compatible = "arm,cortex-a72";
531			reg = <0x30301>;
532			enable-method = "psci";
533			next-level-cache = <&cluster7_l2>;
534			numa-node-id = <1>;
535		};
536
537		cpu30: cpu@30302 {
538			device_type = "cpu";
539			compatible = "arm,cortex-a72";
540			reg = <0x30302>;
541			enable-method = "psci";
542			next-level-cache = <&cluster7_l2>;
543			numa-node-id = <1>;
544		};
545
546		cpu31: cpu@30303 {
547			device_type = "cpu";
548			compatible = "arm,cortex-a72";
549			reg = <0x30303>;
550			enable-method = "psci";
551			next-level-cache = <&cluster7_l2>;
552			numa-node-id = <1>;
553		};
554
555		cpu32: cpu@50000 {
556			device_type = "cpu";
557			compatible = "arm,cortex-a72";
558			reg = <0x50000>;
559			enable-method = "psci";
560			next-level-cache = <&cluster8_l2>;
561			numa-node-id = <2>;
562		};
563
564		cpu33: cpu@50001 {
565			device_type = "cpu";
566			compatible = "arm,cortex-a72";
567			reg = <0x50001>;
568			enable-method = "psci";
569			next-level-cache = <&cluster8_l2>;
570			numa-node-id = <2>;
571		};
572
573		cpu34: cpu@50002 {
574			device_type = "cpu";
575			compatible = "arm,cortex-a72";
576			reg = <0x50002>;
577			enable-method = "psci";
578			next-level-cache = <&cluster8_l2>;
579			numa-node-id = <2>;
580		};
581
582		cpu35: cpu@50003 {
583			device_type = "cpu";
584			compatible = "arm,cortex-a72";
585			reg = <0x50003>;
586			enable-method = "psci";
587			next-level-cache = <&cluster8_l2>;
588			numa-node-id = <2>;
589		};
590
591		cpu36: cpu@50100 {
592			device_type = "cpu";
593			compatible = "arm,cortex-a72";
594			reg = <0x50100>;
595			enable-method = "psci";
596			next-level-cache = <&cluster9_l2>;
597			numa-node-id = <2>;
598		};
599
600		cpu37: cpu@50101 {
601			device_type = "cpu";
602			compatible = "arm,cortex-a72";
603			reg = <0x50101>;
604			enable-method = "psci";
605			next-level-cache = <&cluster9_l2>;
606			numa-node-id = <2>;
607		};
608
609		cpu38: cpu@50102 {
610			device_type = "cpu";
611			compatible = "arm,cortex-a72";
612			reg = <0x50102>;
613			enable-method = "psci";
614			next-level-cache = <&cluster9_l2>;
615			numa-node-id = <2>;
616		};
617
618		cpu39: cpu@50103 {
619			device_type = "cpu";
620			compatible = "arm,cortex-a72";
621			reg = <0x50103>;
622			enable-method = "psci";
623			next-level-cache = <&cluster9_l2>;
624			numa-node-id = <2>;
625		};
626
627		cpu40: cpu@50200 {
628			device_type = "cpu";
629			compatible = "arm,cortex-a72";
630			reg = <0x50200>;
631			enable-method = "psci";
632			next-level-cache = <&cluster10_l2>;
633			numa-node-id = <2>;
634		};
635
636		cpu41: cpu@50201 {
637			device_type = "cpu";
638			compatible = "arm,cortex-a72";
639			reg = <0x50201>;
640			enable-method = "psci";
641			next-level-cache = <&cluster10_l2>;
642			numa-node-id = <2>;
643		};
644
645		cpu42: cpu@50202 {
646			device_type = "cpu";
647			compatible = "arm,cortex-a72";
648			reg = <0x50202>;
649			enable-method = "psci";
650			next-level-cache = <&cluster10_l2>;
651			numa-node-id = <2>;
652		};
653
654		cpu43: cpu@50203 {
655			device_type = "cpu";
656			compatible = "arm,cortex-a72";
657			reg = <0x50203>;
658			enable-method = "psci";
659			next-level-cache = <&cluster10_l2>;
660			numa-node-id = <2>;
661		};
662
663		cpu44: cpu@50300 {
664			device_type = "cpu";
665			compatible = "arm,cortex-a72";
666			reg = <0x50300>;
667			enable-method = "psci";
668			next-level-cache = <&cluster11_l2>;
669			numa-node-id = <2>;
670		};
671
672		cpu45: cpu@50301 {
673			device_type = "cpu";
674			compatible = "arm,cortex-a72";
675			reg = <0x50301>;
676			enable-method = "psci";
677			next-level-cache = <&cluster11_l2>;
678			numa-node-id = <2>;
679		};
680
681		cpu46: cpu@50302 {
682			device_type = "cpu";
683			compatible = "arm,cortex-a72";
684			reg = <0x50302>;
685			enable-method = "psci";
686			next-level-cache = <&cluster11_l2>;
687			numa-node-id = <2>;
688		};
689
690		cpu47: cpu@50303 {
691			device_type = "cpu";
692			compatible = "arm,cortex-a72";
693			reg = <0x50303>;
694			enable-method = "psci";
695			next-level-cache = <&cluster11_l2>;
696			numa-node-id = <2>;
697		};
698
699		cpu48: cpu@70000 {
700			device_type = "cpu";
701			compatible = "arm,cortex-a72";
702			reg = <0x70000>;
703			enable-method = "psci";
704			next-level-cache = <&cluster12_l2>;
705			numa-node-id = <3>;
706		};
707
708		cpu49: cpu@70001 {
709			device_type = "cpu";
710			compatible = "arm,cortex-a72";
711			reg = <0x70001>;
712			enable-method = "psci";
713			next-level-cache = <&cluster12_l2>;
714			numa-node-id = <3>;
715		};
716
717		cpu50: cpu@70002 {
718			device_type = "cpu";
719			compatible = "arm,cortex-a72";
720			reg = <0x70002>;
721			enable-method = "psci";
722			next-level-cache = <&cluster12_l2>;
723			numa-node-id = <3>;
724		};
725
726		cpu51: cpu@70003 {
727			device_type = "cpu";
728			compatible = "arm,cortex-a72";
729			reg = <0x70003>;
730			enable-method = "psci";
731			next-level-cache = <&cluster12_l2>;
732			numa-node-id = <3>;
733		};
734
735		cpu52: cpu@70100 {
736			device_type = "cpu";
737			compatible = "arm,cortex-a72";
738			reg = <0x70100>;
739			enable-method = "psci";
740			next-level-cache = <&cluster13_l2>;
741			numa-node-id = <3>;
742		};
743
744		cpu53: cpu@70101 {
745			device_type = "cpu";
746			compatible = "arm,cortex-a72";
747			reg = <0x70101>;
748			enable-method = "psci";
749			next-level-cache = <&cluster13_l2>;
750			numa-node-id = <3>;
751		};
752
753		cpu54: cpu@70102 {
754			device_type = "cpu";
755			compatible = "arm,cortex-a72";
756			reg = <0x70102>;
757			enable-method = "psci";
758			next-level-cache = <&cluster13_l2>;
759			numa-node-id = <3>;
760		};
761
762		cpu55: cpu@70103 {
763			device_type = "cpu";
764			compatible = "arm,cortex-a72";
765			reg = <0x70103>;
766			enable-method = "psci";
767			next-level-cache = <&cluster13_l2>;
768			numa-node-id = <3>;
769		};
770
771		cpu56: cpu@70200 {
772			device_type = "cpu";
773			compatible = "arm,cortex-a72";
774			reg = <0x70200>;
775			enable-method = "psci";
776			next-level-cache = <&cluster14_l2>;
777			numa-node-id = <3>;
778		};
779
780		cpu57: cpu@70201 {
781			device_type = "cpu";
782			compatible = "arm,cortex-a72";
783			reg = <0x70201>;
784			enable-method = "psci";
785			next-level-cache = <&cluster14_l2>;
786			numa-node-id = <3>;
787		};
788
789		cpu58: cpu@70202 {
790			device_type = "cpu";
791			compatible = "arm,cortex-a72";
792			reg = <0x70202>;
793			enable-method = "psci";
794			next-level-cache = <&cluster14_l2>;
795			numa-node-id = <3>;
796		};
797
798		cpu59: cpu@70203 {
799			device_type = "cpu";
800			compatible = "arm,cortex-a72";
801			reg = <0x70203>;
802			enable-method = "psci";
803			next-level-cache = <&cluster14_l2>;
804			numa-node-id = <3>;
805		};
806
807		cpu60: cpu@70300 {
808			device_type = "cpu";
809			compatible = "arm,cortex-a72";
810			reg = <0x70300>;
811			enable-method = "psci";
812			next-level-cache = <&cluster15_l2>;
813			numa-node-id = <3>;
814		};
815
816		cpu61: cpu@70301 {
817			device_type = "cpu";
818			compatible = "arm,cortex-a72";
819			reg = <0x70301>;
820			enable-method = "psci";
821			next-level-cache = <&cluster15_l2>;
822			numa-node-id = <3>;
823		};
824
825		cpu62: cpu@70302 {
826			device_type = "cpu";
827			compatible = "arm,cortex-a72";
828			reg = <0x70302>;
829			enable-method = "psci";
830			next-level-cache = <&cluster15_l2>;
831			numa-node-id = <3>;
832		};
833
834		cpu63: cpu@70303 {
835			device_type = "cpu";
836			compatible = "arm,cortex-a72";
837			reg = <0x70303>;
838			enable-method = "psci";
839			next-level-cache = <&cluster15_l2>;
840			numa-node-id = <3>;
841		};
842
843		cluster0_l2: l2-cache0 {
844			compatible = "cache";
845		};
846
847		cluster1_l2: l2-cache1 {
848			compatible = "cache";
849		};
850
851		cluster2_l2: l2-cache2 {
852			compatible = "cache";
853		};
854
855		cluster3_l2: l2-cache3 {
856			compatible = "cache";
857		};
858
859		cluster4_l2: l2-cache4 {
860			compatible = "cache";
861		};
862
863		cluster5_l2: l2-cache5 {
864			compatible = "cache";
865		};
866
867		cluster6_l2: l2-cache6 {
868			compatible = "cache";
869		};
870
871		cluster7_l2: l2-cache7 {
872			compatible = "cache";
873		};
874
875		cluster8_l2: l2-cache8 {
876			compatible = "cache";
877		};
878
879		cluster9_l2: l2-cache9 {
880			compatible = "cache";
881		};
882
883		cluster10_l2: l2-cache10 {
884			compatible = "cache";
885		};
886
887		cluster11_l2: l2-cache11 {
888			compatible = "cache";
889		};
890
891		cluster12_l2: l2-cache12 {
892			compatible = "cache";
893		};
894
895		cluster13_l2: l2-cache13 {
896			compatible = "cache";
897		};
898
899		cluster14_l2: l2-cache14 {
900			compatible = "cache";
901		};
902
903		cluster15_l2: l2-cache15 {
904			compatible = "cache";
905		};
906	};
907
908	gic: interrupt-controller@4d000000 {
909		compatible = "arm,gic-v3";
910		#interrupt-cells = <3>;
911		#address-cells = <2>;
912		#size-cells = <2>;
913		ranges;
914		interrupt-controller;
915		#redistributor-regions = <4>;
916		redistributor-stride = <0x0 0x40000>;
917		reg = <0x0 0x4d000000 0x0 0x10000>,	/* GICD */
918		      <0x0 0x4d100000 0x0 0x400000>,	/* p0 GICR node 0 */
919		      <0x0 0x6d100000 0x0 0x400000>,	/* p0 GICR node 1 */
920		      <0x400 0x4d100000 0x0 0x400000>,	/* p1 GICR node 2 */
921		      <0x400 0x6d100000 0x0 0x400000>,	/* p1 GICR node 3 */
922		      <0x0 0xfe000000 0x0 0x10000>,	/* GICC */
923		      <0x0 0xfe010000 0x0 0x10000>,	/* GICH */
924		      <0x0 0xfe020000 0x0 0x10000>;	/* GICV */
925		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
926
927		p0_its_peri_a: msi-controller@4c000000 {
928			compatible = "arm,gic-v3-its";
929			msi-controller;
930			#msi-cells = <1>;
931			reg = <0x0 0x4c000000 0x0 0x40000>;
932		};
933
934		p0_its_peri_b: msi-controller@6c000000 {
935			compatible = "arm,gic-v3-its";
936			msi-controller;
937			#msi-cells = <1>;
938			reg = <0x0 0x6c000000 0x0 0x40000>;
939		};
940
941		p0_its_dsa_a: msi-controller@c6000000 {
942			compatible = "arm,gic-v3-its";
943			msi-controller;
944			#msi-cells = <1>;
945			reg = <0x0 0xc6000000 0x0 0x40000>;
946		};
947
948		p0_its_dsa_b: msi-controller@8c6000000 {
949			compatible = "arm,gic-v3-its";
950			msi-controller;
951			#msi-cells = <1>;
952			reg = <0x8 0xc6000000 0x0 0x40000>;
953		};
954
955		p1_its_peri_a: msi-controller@4004c000000 {
956			compatible = "arm,gic-v3-its";
957			msi-controller;
958			#msi-cells = <1>;
959			reg = <0x400 0x4c000000 0x0 0x40000>;
960		};
961
962		p1_its_peri_b: msi-controller@4006c000000 {
963			compatible = "arm,gic-v3-its";
964			msi-controller;
965			#msi-cells = <1>;
966			reg = <0x400 0x6c000000 0x0 0x40000>;
967		};
968
969		p1_its_dsa_a: msi-controller@400c6000000 {
970			compatible = "arm,gic-v3-its";
971			msi-controller;
972			#msi-cells = <1>;
973			reg = <0x400 0xc6000000 0x0 0x40000>;
974		};
975
976		p1_its_dsa_b: msi-controller@408c6000000 {
977			compatible = "arm,gic-v3-its";
978			msi-controller;
979			#msi-cells = <1>;
980			reg = <0x408 0xc6000000 0x0 0x40000>;
981		};
982	};
983
984	timer {
985		compatible = "arm,armv8-timer";
986		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
987			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
988			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
989			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
990	};
991
992	pmu {
993		compatible = "arm,cortex-a72-pmu";
994		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
995	};
996
997	p0_mbigen_peri_b: interrupt-controller@60080000 {
998		compatible = "hisilicon,mbigen-v2";
999		reg = <0x0 0x60080000 0x0 0x10000>;
1000
1001		mbigen_uart: uart_intc {
1002			msi-parent = <&p0_its_peri_b 0x120c7>;
1003			interrupt-controller;
1004			#interrupt-cells = <2>;
1005			num-pins = <1>;
1006		};
1007	};
1008
1009	p0_mbigen_pcie_a: interrupt-controller@a0080000 {
1010		compatible = "hisilicon,mbigen-v2";
1011		reg = <0x0 0xa0080000 0x0 0x10000>;
1012
1013		mbigen_pcie2_a: intc_pcie2_a {
1014			msi-parent = <&p0_its_dsa_a 0x40087>;
1015			interrupt-controller;
1016			#interrupt-cells = <2>;
1017			num-pins = <10>;
1018		};
1019
1020		mbigen_sas1: intc_sas1 {
1021			msi-parent = <&p0_its_dsa_a 0x40000>;
1022			interrupt-controller;
1023			#interrupt-cells = <2>;
1024			num-pins = <128>;
1025		};
1026
1027		mbigen_sas2: intc_sas2 {
1028			msi-parent = <&p0_its_dsa_a 0x40040>;
1029			interrupt-controller;
1030			#interrupt-cells = <2>;
1031			num-pins = <128>;
1032		};
1033
1034		mbigen_smmu_pcie: intc_smmu_pcie {
1035			msi-parent = <&p0_its_dsa_a 0x40b0c>;
1036			interrupt-controller;
1037			#interrupt-cells = <2>;
1038			num-pins = <3>;
1039		};
1040
1041		mbigen_usb: intc_usb {
1042			msi-parent = <&p0_its_dsa_a 0x40080>;
1043			interrupt-controller;
1044			#interrupt-cells = <2>;
1045			num-pins = <2>;
1046		};
1047	};
1048	p0_mbigen_alg_a:interrupt-controller@d0080000 {
1049		compatible = "hisilicon,mbigen-v2";
1050		reg = <0x0 0xd0080000 0x0 0x10000>;
1051
1052		p0_mbigen_sec_a: intc_sec {
1053			msi-parent = <&p0_its_dsa_a 0x40400>;
1054			interrupt-controller;
1055			#interrupt-cells = <2>;
1056			num-pins = <33>;
1057		};
1058		p0_mbigen_smmu_alg_a: intc_smmu_alg {
1059			msi-parent = <&p0_its_dsa_a 0x40b1b>;
1060			interrupt-controller;
1061			#interrupt-cells = <2>;
1062			num-pins = <3>;
1063		};
1064	};
1065	p0_mbigen_alg_b:interrupt-controller@8,d0080000 {
1066		compatible = "hisilicon,mbigen-v2";
1067		reg = <0x8 0xd0080000 0x0 0x10000>;
1068
1069		p0_mbigen_sec_b: intc_sec {
1070			msi-parent = <&p0_its_dsa_b 0x42400>;
1071			interrupt-controller;
1072			#interrupt-cells = <2>;
1073			num-pins = <33>;
1074		};
1075		p0_mbigen_smmu_alg_b: intc_smmu_alg {
1076			msi-parent = <&p0_its_dsa_b 0x42b1b>;
1077			interrupt-controller;
1078			#interrupt-cells = <2>;
1079			num-pins = <3>;
1080		};
1081	};
1082	p1_mbigen_alg_a:interrupt-controller@400,d0080000 {
1083		compatible = "hisilicon,mbigen-v2";
1084		reg = <0x400 0xd0080000 0x0 0x10000>;
1085
1086		p1_mbigen_sec_a: intc_sec {
1087			msi-parent = <&p1_its_dsa_a 0x44400>;
1088			interrupt-controller;
1089			#interrupt-cells = <2>;
1090			num-pins = <33>;
1091		};
1092		p1_mbigen_smmu_alg_a: intc_smmu_alg {
1093			msi-parent = <&p1_its_dsa_a 0x44b1b>;
1094			interrupt-controller;
1095			#interrupt-cells = <2>;
1096			num-pins = <3>;
1097		};
1098	};
1099	p1_mbigen_alg_b:interrupt-controller@408,d0080000 {
1100		compatible = "hisilicon,mbigen-v2";
1101		reg = <0x408 0xd0080000 0x0 0x10000>;
1102
1103		p1_mbigen_sec_b: intc_sec {
1104			msi-parent = <&p1_its_dsa_b 0x46400>;
1105			interrupt-controller;
1106			#interrupt-cells = <2>;
1107			num-pins = <33>;
1108		};
1109		p1_mbigen_smmu_alg_b: intc_smmu_alg {
1110			msi-parent = <&p1_its_dsa_b 0x46b1b>;
1111			interrupt-controller;
1112			#interrupt-cells = <2>;
1113			num-pins = <3>;
1114		};
1115	};
1116	p0_mbigen_dsa_a: interrupt-controller@c0080000 {
1117		compatible = "hisilicon,mbigen-v2";
1118		reg = <0x0 0xc0080000 0x0 0x10000>;
1119
1120		mbigen_dsaf0: intc_dsaf0 {
1121			msi-parent = <&p0_its_dsa_a 0x40800>;
1122			interrupt-controller;
1123			#interrupt-cells = <2>;
1124			num-pins = <409>;
1125		};
1126
1127		mbigen_dsa_roce: intc-roce {
1128			msi-parent = <&p0_its_dsa_a 0x40B1E>;
1129			interrupt-controller;
1130			#interrupt-cells = <2>;
1131			num-pins = <34>;
1132		};
1133
1134		mbigen_sas0: intc-sas0 {
1135			msi-parent = <&p0_its_dsa_a 0x40900>;
1136			interrupt-controller;
1137			#interrupt-cells = <2>;
1138			num-pins = <128>;
1139		};
1140
1141		mbigen_smmu_dsa: intc_smmu_dsa {
1142			msi-parent = <&p0_its_dsa_a 0x40b20>;
1143			interrupt-controller;
1144			#interrupt-cells = <2>;
1145			num-pins = <3>;
1146		};
1147	};
1148
1149	/**
1150	 *  HiSilicon erratum 161010801: This describes the limitation
1151	 *  of HiSilicon platforms hip06/hip07 to support the SMMUv3
1152	 *  mappings for PCIe MSI transactions.
1153	 *  PCIe controller on these platforms has to differentiate the
1154	 *  MSI payload against other DMA payload and has to modify the
1155	 *  MSI payload. This makes it difficult for these platforms to
1156	 *  have a SMMU translation for MSI. In order to workaround this,
1157	 *  ARM SMMUv3 driver requires a quirk to treat the MSI regions
1158	 *  separately. Such a quirk is currently missing for DT based
1159	 *  systems. Hence please make sure that the smmu pcie node on
1160	 *  hip07 is disabled as this will break the PCIe functionality
1161	 *  when iommu-map entry is used along with the PCIe node.
1162	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
1163	 */
1164	smmu0: iommu@a0040000 {
1165		compatible = "arm,smmu-v3";
1166		reg = <0x0 0xa0040000 0x0 0x20000>;
1167		#iommu-cells = <1>;
1168		dma-coherent;
1169		hisilicon,broken-prefetch-cmd;
1170		status = "disabled";
1171	};
1172	p0_smmu_alg_a: iommu@d0040000 {
1173		compatible = "arm,smmu-v3";
1174		reg = <0x0 0xd0040000 0x0 0x20000>;
1175		interrupt-parent = <&p0_mbigen_smmu_alg_a>;
1176		interrupts = <733 1>,
1177		<734 1>,
1178		<735 1>;
1179		interrupt-names = "eventq", "gerror", "priq";
1180		#iommu-cells = <1>;
1181		dma-coherent;
1182		hisilicon,broken-prefetch-cmd;
1183	};
1184	p0_smmu_alg_b: iommu@8d0040000 {
1185		compatible = "arm,smmu-v3";
1186		reg = <0x8 0xd0040000 0x0 0x20000>;
1187		interrupt-parent = <&p0_mbigen_smmu_alg_b>;
1188		interrupts = <733 1>,
1189		<734 1>,
1190		<735 1>;
1191		interrupt-names = "eventq", "gerror", "priq";
1192		#iommu-cells = <1>;
1193		dma-coherent;
1194		hisilicon,broken-prefetch-cmd;
1195	};
1196	p1_smmu_alg_a: iommu@400d0040000 {
1197		compatible = "arm,smmu-v3";
1198		reg = <0x400 0xd0040000 0x0 0x20000>;
1199		interrupt-parent = <&p1_mbigen_smmu_alg_a>;
1200		interrupts = <733 1>,
1201		<734 1>,
1202		<735 1>;
1203		interrupt-names = "eventq", "gerror", "priq";
1204		#iommu-cells = <1>;
1205		dma-coherent;
1206		hisilicon,broken-prefetch-cmd;
1207	};
1208	p1_smmu_alg_b: iommu@408d0040000 {
1209		compatible = "arm,smmu-v3";
1210		reg = <0x408 0xd0040000 0x0 0x20000>;
1211		interrupt-parent = <&p1_mbigen_smmu_alg_b>;
1212		interrupts = <733 1>,
1213		<734 1>,
1214		<735 1>;
1215		interrupt-names = "eventq", "gerror", "priq";
1216		#iommu-cells = <1>;
1217		dma-coherent;
1218		hisilicon,broken-prefetch-cmd;
1219	};
1220
1221	soc {
1222		compatible = "simple-bus";
1223		#address-cells = <2>;
1224		#size-cells = <2>;
1225		ranges;
1226
1227		isa@a01b0000 {
1228			compatible = "hisilicon,hip07-lpc";
1229			#size-cells = <1>;
1230			#address-cells = <2>;
1231			reg = <0x0 0xa01b0000 0x0 0x1000>;
1232
1233			ipmi0: bt@e4 {
1234				compatible = "ipmi-bt";
1235				device_type = "ipmi";
1236				reg = <0x01 0xe4 0x04>;
1237				status = "disabled";
1238			};
1239		};
1240
1241		uart0: uart@602b0000 {
1242			compatible = "arm,sbsa-uart";
1243			reg = <0x0 0x602b0000 0x0 0x1000>;
1244			interrupt-parent = <&mbigen_uart>;
1245			interrupts = <807 4>;
1246			current-speed = <115200>;
1247			reg-io-width = <4>;
1248			status = "disabled";
1249		};
1250
1251		usb_ohci: usb@a7030000 {
1252			compatible = "generic-ohci";
1253			reg = <0x0 0xa7030000 0x0 0x10000>;
1254			interrupt-parent = <&mbigen_usb>;
1255			interrupts = <640 4>;
1256			dma-coherent;
1257			status = "disabled";
1258		};
1259
1260		usb_ehci: usb@a7020000 {
1261			compatible = "generic-ehci";
1262			reg = <0x0 0xa7020000 0x0 0x10000>;
1263			interrupt-parent = <&mbigen_usb>;
1264			interrupts = <641 4>;
1265			dma-coherent;
1266			status = "disabled";
1267		};
1268
1269		peri_c_subctrl: sub_ctrl_c@60000000 {
1270			compatible = "hisilicon,peri-subctrl","syscon";
1271			reg = <0 0x60000000 0x0 0x10000>;
1272		};
1273
1274		dsa_subctrl: dsa_subctrl@c0000000 {
1275			compatible = "hisilicon,dsa-subctrl", "syscon";
1276			reg = <0x0 0xc0000000 0x0 0x10000>;
1277		};
1278
1279		dsa_cpld: dsa_cpld@78000010 {
1280			compatible = "syscon";
1281			reg = <0x0 0x78000010 0x0 0x100>;
1282			reg-io-width = <2>;
1283		};
1284
1285		pcie_subctl: pcie_subctl@a0000000 {
1286			compatible = "hisilicon,pcie-sas-subctrl", "syscon";
1287			reg = <0x0 0xa0000000 0x0 0x10000>;
1288		};
1289
1290		serdes_ctrl: sds_ctrl@c2200000 {
1291			compatible = "syscon";
1292			reg = <0 0xc2200000 0x0 0x80000>;
1293		};
1294
1295		mdio@603c0000 {
1296			compatible = "hisilicon,hns-mdio";
1297			reg = <0x0 0x603c0000 0x0 0x1000>;
1298			subctrl-vbase = <&peri_c_subctrl 0x338 0xa38
1299					 0x531c 0x5a1c>;
1300			#address-cells = <1>;
1301			#size-cells = <0>;
1302
1303			phy0: ethernet-phy@0 {
1304				compatible = "ethernet-phy-ieee802.3-c22";
1305				reg = <0>;
1306			};
1307
1308			phy1: ethernet-phy@1 {
1309				compatible = "ethernet-phy-ieee802.3-c22";
1310				reg = <1>;
1311			};
1312		};
1313
1314		dsaf0: dsa@c7000000 {
1315			#address-cells = <1>;
1316			#size-cells = <0>;
1317			compatible = "hisilicon,hns-dsaf-v2";
1318			mode = "6port-16rss";
1319			reg = <0x0 0xc5000000 0x0 0x890000>,
1320			      <0x0 0xc7000000 0x0 0x600000>;
1321			reg-names = "ppe-base", "dsaf-base";
1322			interrupt-parent = <&mbigen_dsaf0>;
1323			subctrl-syscon = <&dsa_subctrl>;
1324			reset-field-offset = <0>;
1325			interrupts =
1326			<576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
1327			<581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
1328			<586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
1329			<591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
1330			<596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
1331			<960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
1332			<965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
1333			<970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
1334			<975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
1335			<980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
1336			<985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
1337			<990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
1338			<995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
1339			<1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
1340			<1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
1341			<1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
1342			<1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
1343			<1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
1344			<1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
1345			<1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
1346			<1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
1347			<1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
1348			<1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
1349			<1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
1350			<1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
1351			<1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
1352			<1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
1353			<1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
1354			<1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
1355			<1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
1356			<1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
1357			<1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
1358			<1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
1359			<1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
1360			<1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
1361			<1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
1362			<1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
1363			<1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
1364			<1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
1365			<1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
1366			<1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
1367			<1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
1368			<1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
1369			<1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
1370			<1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
1371			<1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
1372			<1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
1373			<1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
1374			<1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
1375			<1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
1376			<1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
1377			<1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
1378			<1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
1379			<1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
1380			<1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
1381			<1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
1382			<1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
1383			<1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
1384			<1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
1385			<1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
1386			<1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
1387			<1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
1388			<1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
1389			<1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
1390			<1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
1391			<1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
1392			<1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
1393			<1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
1394			<1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
1395			<1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
1396			<1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
1397			<1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
1398			<1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
1399			<1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
1400			<1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
1401			<1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
1402			<1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
1403			<1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
1404			<1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
1405			<1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
1406			<1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
1407			<1340 1>, <1341 1>, <1342 1>, <1343 1>;
1408
1409			desc-num = <0x400>;
1410			buf-size = <0x1000>;
1411			dma-coherent;
1412
1413			port@0 {
1414				reg = <0>;
1415				serdes-syscon = <&serdes_ctrl>;
1416				cpld-syscon = <&dsa_cpld 0x0>;
1417				port-rst-offset = <0>;
1418				port-mode-offset = <0>;
1419				mc-mac-mask = [ff f0 00 00 00 00];
1420				media-type = "fiber";
1421			};
1422
1423			port@1 {
1424				reg = <1>;
1425				serdes-syscon= <&serdes_ctrl>;
1426				cpld-syscon = <&dsa_cpld 0x4>;
1427				port-rst-offset = <1>;
1428				port-mode-offset = <1>;
1429				mc-mac-mask = [ff f0 00 00 00 00];
1430				media-type = "fiber";
1431			};
1432
1433			port@4 {
1434				reg = <4>;
1435				phy-handle = <&phy0>;
1436				serdes-syscon= <&serdes_ctrl>;
1437				port-rst-offset = <4>;
1438				port-mode-offset = <2>;
1439				mc-mac-mask = [ff f0 00 00 00 00];
1440				media-type = "copper";
1441			};
1442
1443			port@5 {
1444				reg = <5>;
1445				phy-handle = <&phy1>;
1446				serdes-syscon= <&serdes_ctrl>;
1447				port-rst-offset = <5>;
1448				port-mode-offset = <3>;
1449				mc-mac-mask = [ff f0 00 00 00 00];
1450				media-type = "copper";
1451			};
1452		};
1453
1454		eth0: ethernet@4{
1455			compatible = "hisilicon,hns-nic-v2";
1456			ae-handle = <&dsaf0>;
1457			port-idx-in-ae = <4>;
1458			local-mac-address = [00 00 00 00 00 00];
1459			status = "disabled";
1460			dma-coherent;
1461		};
1462
1463		eth1: ethernet@5{
1464			compatible = "hisilicon,hns-nic-v2";
1465			ae-handle = <&dsaf0>;
1466			port-idx-in-ae = <5>;
1467			local-mac-address = [00 00 00 00 00 00];
1468			status = "disabled";
1469			dma-coherent;
1470		};
1471
1472		eth2: ethernet@0{
1473			compatible = "hisilicon,hns-nic-v2";
1474			ae-handle = <&dsaf0>;
1475			port-idx-in-ae = <0>;
1476			local-mac-address = [00 00 00 00 00 00];
1477			status = "disabled";
1478			dma-coherent;
1479		};
1480
1481		eth3: ethernet@1{
1482			compatible = "hisilicon,hns-nic-v2";
1483			ae-handle = <&dsaf0>;
1484			port-idx-in-ae = <1>;
1485			local-mac-address = [00 00 00 00 00 00];
1486			status = "disabled";
1487			dma-coherent;
1488		};
1489
1490		infiniband@c4000000 {
1491			compatible = "hisilicon,hns-roce-v1";
1492			reg = <0x0 0xc4000000 0x0 0x100000>;
1493			dma-coherent;
1494			eth-handle = <&eth2 &eth3 0 0 &eth0 &eth1>;
1495			dsaf-handle = <&dsaf0>;
1496			node-guid = [00 9A CD 00 00 01 02 03];
1497			#address-cells = <2>;
1498			#size-cells = <2>;
1499			interrupt-parent = <&mbigen_dsa_roce>;
1500			interrupts = <722 1>,
1501				     <723 1>,
1502				     <724 1>,
1503				     <725 1>,
1504				     <726 1>,
1505				     <727 1>,
1506				     <728 1>,
1507				     <729 1>,
1508				     <730 1>,
1509				     <731 1>,
1510				     <732 1>,
1511				     <733 1>,
1512				     <734 1>,
1513				     <735 1>,
1514				     <736 1>,
1515				     <737 1>,
1516				     <738 1>,
1517				     <739 1>,
1518				     <740 1>,
1519				     <741 1>,
1520				     <742 1>,
1521				     <743 1>,
1522				     <744 1>,
1523				     <745 1>,
1524				     <746 1>,
1525				     <747 1>,
1526				     <748 1>,
1527				     <749 1>,
1528				     <750 1>,
1529				     <751 1>,
1530				     <752 1>,
1531				     <753 1>,
1532				     <785 1>,
1533				     <754 4>;
1534
1535			interrupt-names = "hns-roce-comp-0",
1536					  "hns-roce-comp-1",
1537					  "hns-roce-comp-2",
1538					  "hns-roce-comp-3",
1539					  "hns-roce-comp-4",
1540					  "hns-roce-comp-5",
1541					  "hns-roce-comp-6",
1542					  "hns-roce-comp-7",
1543					  "hns-roce-comp-8",
1544					  "hns-roce-comp-9",
1545					  "hns-roce-comp-10",
1546					  "hns-roce-comp-11",
1547					  "hns-roce-comp-12",
1548					  "hns-roce-comp-13",
1549					  "hns-roce-comp-14",
1550					  "hns-roce-comp-15",
1551					  "hns-roce-comp-16",
1552					  "hns-roce-comp-17",
1553					  "hns-roce-comp-18",
1554					  "hns-roce-comp-19",
1555					  "hns-roce-comp-20",
1556					  "hns-roce-comp-21",
1557					  "hns-roce-comp-22",
1558					  "hns-roce-comp-23",
1559					  "hns-roce-comp-24",
1560					  "hns-roce-comp-25",
1561					  "hns-roce-comp-26",
1562					  "hns-roce-comp-27",
1563					  "hns-roce-comp-28",
1564					  "hns-roce-comp-29",
1565					  "hns-roce-comp-30",
1566					  "hns-roce-comp-31",
1567					  "hns-roce-async",
1568					  "hns-roce-common";
1569		};
1570
1571		sas0: sas@c3000000 {
1572			compatible = "hisilicon,hip07-sas-v2";
1573			reg = <0 0xc3000000 0 0x10000>;
1574			sas-addr = [50 01 88 20 16 00 00 00];
1575			hisilicon,sas-syscon = <&dsa_subctrl>;
1576			ctrl-reset-reg = <0xa60>;
1577			ctrl-reset-sts-reg = <0x5a30>;
1578			ctrl-clock-ena-reg = <0x338>;
1579			queue-count = <16>;
1580			phy-count = <8>;
1581			dma-coherent;
1582			interrupt-parent = <&mbigen_sas0>;
1583			interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
1584				     <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
1585				     <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
1586				     <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
1587				     <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
1588				     <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
1589				     <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
1590				     <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
1591				     <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
1592				     <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
1593				     <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
1594				     <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
1595				     <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
1596				     <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
1597				     <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
1598				     <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
1599				     <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
1600				     <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
1601				     <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
1602				     <159 4>,<601 1>,<602 1>,<603 1>,<604 1>,
1603				     <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
1604				     <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
1605				     <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
1606				     <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
1607				     <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
1608				     <630 1>,<631 1>,<632 1>;
1609			status = "disabled";
1610		};
1611
1612		sas1: sas@a2000000 {
1613			compatible = "hisilicon,hip07-sas-v2";
1614			reg = <0 0xa2000000 0 0x10000>;
1615			sas-addr = [50 01 88 20 16 00 00 00];
1616			hisilicon,sas-syscon = <&pcie_subctl>;
1617			hip06-sas-v2-quirk-amt;
1618			ctrl-reset-reg = <0xa18>;
1619			ctrl-reset-sts-reg = <0x5a0c>;
1620			ctrl-clock-ena-reg = <0x318>;
1621			queue-count = <16>;
1622			phy-count = <8>;
1623			dma-coherent;
1624			interrupt-parent = <&mbigen_sas1>;
1625			interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
1626				     <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
1627				     <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
1628				     <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
1629				     <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
1630				     <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
1631				     <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
1632				     <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
1633				     <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
1634				     <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
1635				     <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
1636				     <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
1637				     <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
1638				     <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
1639				     <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
1640				     <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
1641				     <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
1642				     <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
1643				     <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
1644				     <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
1645				     <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
1646				     <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
1647				     <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
1648				     <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
1649				     <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
1650				     <605 1>,<606 1>,<607 1>;
1651			status = "disabled";
1652		};
1653
1654		sas2: sas@a3000000 {
1655			compatible = "hisilicon,hip07-sas-v2";
1656			reg = <0 0xa3000000 0 0x10000>;
1657			sas-addr = [50 01 88 20 16 00 00 00];
1658			hisilicon,sas-syscon = <&pcie_subctl>;
1659			ctrl-reset-reg = <0xae0>;
1660			ctrl-reset-sts-reg = <0x5a70>;
1661			ctrl-clock-ena-reg = <0x3a8>;
1662			queue-count = <16>;
1663			phy-count = <9>;
1664			dma-coherent;
1665			interrupt-parent = <&mbigen_sas2>;
1666			interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
1667				     <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
1668				     <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
1669				     <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
1670				     <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
1671				     <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
1672				     <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
1673				     <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
1674				     <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
1675				     <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
1676				     <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
1677				     <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
1678				     <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
1679				     <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
1680				     <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
1681				     <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
1682				     <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
1683				     <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
1684				     <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
1685				     <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
1686				     <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
1687				     <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
1688				     <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
1689				     <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
1690				     <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
1691				     <637 1>,<638 1>,<639 1>;
1692			status = "disabled";
1693		};
1694
1695		p0_pcie2_a: pcie@a00a0000 {
1696			compatible = "hisilicon,hip07-pcie-ecam";
1697			reg = <0 0xaf800000 0 0x800000>,
1698			      <0 0xa00a0000 0 0x10000>;
1699			bus-range = <0xf8 0xff>;
1700			msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;
1701			msi-map-mask = <0xffff>;
1702			#address-cells = <3>;
1703			#size-cells = <2>;
1704			device_type = "pci";
1705			dma-coherent;
1706			ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000>,
1707				 <0x01000000 0 0 0 0xaf7f0000 0 0x10000>;
1708			#interrupt-cells = <1>;
1709			interrupt-map-mask = <0xf800 0 0 7>;
1710			interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
1711					 0x0 0 0 2 &mbigen_pcie2_a 671 4
1712					 0x0 0 0 3 &mbigen_pcie2_a 671 4
1713					 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
1714			status = "disabled";
1715		};
1716		p0_sec_a: crypto@d2000000 {
1717			compatible = "hisilicon,hip07-sec";
1718			reg = <0x0 0xd0000000 0x0 0x10000>,
1719			      <0x0 0xd2000000 0x0 0x10000>,
1720			      <0x0 0xd2010000 0x0 0x10000>,
1721			      <0x0 0xd2020000 0x0 0x10000>,
1722			      <0x0 0xd2030000 0x0 0x10000>,
1723			      <0x0 0xd2040000 0x0 0x10000>,
1724			      <0x0 0xd2050000 0x0 0x10000>,
1725			      <0x0 0xd2060000 0x0 0x10000>,
1726			      <0x0 0xd2070000 0x0 0x10000>,
1727			      <0x0 0xd2080000 0x0 0x10000>,
1728			      <0x0 0xd2090000 0x0 0x10000>,
1729			      <0x0 0xd20a0000 0x0 0x10000>,
1730			      <0x0 0xd20b0000 0x0 0x10000>,
1731			      <0x0 0xd20c0000 0x0 0x10000>,
1732			      <0x0 0xd20d0000 0x0 0x10000>,
1733			      <0x0 0xd20e0000 0x0 0x10000>,
1734			      <0x0 0xd20f0000 0x0 0x10000>,
1735			      <0x0 0xd2100000 0x0 0x10000>;
1736			interrupt-parent = <&p0_mbigen_sec_a>;
1737			iommus = <&p0_smmu_alg_a 0x600>;
1738			dma-coherent;
1739			interrupts = <576 4>,
1740				     <577 1>, <578 4>,
1741				     <579 1>, <580 4>,
1742				     <581 1>, <582 4>,
1743				     <583 1>, <584 4>,
1744				     <585 1>, <586 4>,
1745				     <587 1>, <588 4>,
1746				     <589 1>, <590 4>,
1747				     <591 1>, <592 4>,
1748				     <593 1>, <594 4>,
1749				     <595 1>, <596 4>,
1750				     <597 1>, <598 4>,
1751				     <599 1>, <600 4>,
1752				     <601 1>, <602 4>,
1753				     <603 1>, <604 4>,
1754				     <605 1>, <606 4>,
1755				     <607 1>, <608 4>;
1756		};
1757		p0_sec_b: crypto@8,d2000000 {
1758			compatible = "hisilicon,hip07-sec";
1759			reg = <0x8 0xd0000000 0x0 0x10000>,
1760			      <0x8 0xd2000000 0x0 0x10000>,
1761			      <0x8 0xd2010000 0x0 0x10000>,
1762			      <0x8 0xd2020000 0x0 0x10000>,
1763			      <0x8 0xd2030000 0x0 0x10000>,
1764			      <0x8 0xd2040000 0x0 0x10000>,
1765			      <0x8 0xd2050000 0x0 0x10000>,
1766			      <0x8 0xd2060000 0x0 0x10000>,
1767			      <0x8 0xd2070000 0x0 0x10000>,
1768			      <0x8 0xd2080000 0x0 0x10000>,
1769			      <0x8 0xd2090000 0x0 0x10000>,
1770			      <0x8 0xd20a0000 0x0 0x10000>,
1771			      <0x8 0xd20b0000 0x0 0x10000>,
1772			      <0x8 0xd20c0000 0x0 0x10000>,
1773			      <0x8 0xd20d0000 0x0 0x10000>,
1774			      <0x8 0xd20e0000 0x0 0x10000>,
1775			      <0x8 0xd20f0000 0x0 0x10000>,
1776			      <0x8 0xd2100000 0x0 0x10000>;
1777			interrupt-parent = <&p0_mbigen_sec_b>;
1778			iommus = <&p0_smmu_alg_b 0x600>;
1779			dma-coherent;
1780			interrupts = <576 4>,
1781				     <577 1>, <578 4>,
1782				     <579 1>, <580 4>,
1783				     <581 1>, <582 4>,
1784				     <583 1>, <584 4>,
1785				     <585 1>, <586 4>,
1786				     <587 1>, <588 4>,
1787				     <589 1>, <590 4>,
1788				     <591 1>, <592 4>,
1789				     <593 1>, <594 4>,
1790				     <595 1>, <596 4>,
1791				     <597 1>, <598 4>,
1792				     <599 1>, <600 4>,
1793				     <601 1>, <602 4>,
1794				     <603 1>, <604 4>,
1795				     <605 1>, <606 4>,
1796				     <607 1>, <608 4>;
1797		};
1798		p1_sec_a: crypto@400,d2000000 {
1799			compatible = "hisilicon,hip07-sec";
1800			reg = <0x400 0xd0000000 0x0 0x10000>,
1801			      <0x400 0xd2000000 0x0 0x10000>,
1802			      <0x400 0xd2010000 0x0 0x10000>,
1803			      <0x400 0xd2020000 0x0 0x10000>,
1804			      <0x400 0xd2030000 0x0 0x10000>,
1805			      <0x400 0xd2040000 0x0 0x10000>,
1806			      <0x400 0xd2050000 0x0 0x10000>,
1807			      <0x400 0xd2060000 0x0 0x10000>,
1808			      <0x400 0xd2070000 0x0 0x10000>,
1809			      <0x400 0xd2080000 0x0 0x10000>,
1810			      <0x400 0xd2090000 0x0 0x10000>,
1811			      <0x400 0xd20a0000 0x0 0x10000>,
1812			      <0x400 0xd20b0000 0x0 0x10000>,
1813			      <0x400 0xd20c0000 0x0 0x10000>,
1814			      <0x400 0xd20d0000 0x0 0x10000>,
1815			      <0x400 0xd20e0000 0x0 0x10000>,
1816			      <0x400 0xd20f0000 0x0 0x10000>,
1817			      <0x400 0xd2100000 0x0 0x10000>;
1818			interrupt-parent = <&p1_mbigen_sec_a>;
1819			iommus = <&p1_smmu_alg_a 0x600>;
1820			dma-coherent;
1821			interrupts = <576 4>,
1822				     <577 1>, <578 4>,
1823				     <579 1>, <580 4>,
1824				     <581 1>, <582 4>,
1825				     <583 1>, <584 4>,
1826				     <585 1>, <586 4>,
1827				     <587 1>, <588 4>,
1828				     <589 1>, <590 4>,
1829				     <591 1>, <592 4>,
1830				     <593 1>, <594 4>,
1831				     <595 1>, <596 4>,
1832				     <597 1>, <598 4>,
1833				     <599 1>, <600 4>,
1834				     <601 1>, <602 4>,
1835				     <603 1>, <604 4>,
1836				     <605 1>, <606 4>,
1837				     <607 1>, <608 4>;
1838		};
1839		p1_sec_b: crypto@408,d2000000 {
1840			compatible = "hisilicon,hip07-sec";
1841			reg = <0x408 0xd0000000 0x0 0x10000>,
1842			      <0x408 0xd2000000 0x0 0x10000>,
1843			      <0x408 0xd2010000 0x0 0x10000>,
1844			      <0x408 0xd2020000 0x0 0x10000>,
1845			      <0x408 0xd2030000 0x0 0x10000>,
1846			      <0x408 0xd2040000 0x0 0x10000>,
1847			      <0x408 0xd2050000 0x0 0x10000>,
1848			      <0x408 0xd2060000 0x0 0x10000>,
1849			      <0x408 0xd2070000 0x0 0x10000>,
1850			      <0x408 0xd2080000 0x0 0x10000>,
1851			      <0x408 0xd2090000 0x0 0x10000>,
1852			      <0x408 0xd20a0000 0x0 0x10000>,
1853			      <0x408 0xd20b0000 0x0 0x10000>,
1854			      <0x408 0xd20c0000 0x0 0x10000>,
1855			      <0x408 0xd20d0000 0x0 0x10000>,
1856			      <0x408 0xd20e0000 0x0 0x10000>,
1857			      <0x408 0xd20f0000 0x0 0x10000>,
1858			      <0x408 0xd2100000 0x0 0x10000>;
1859			interrupt-parent = <&p1_mbigen_sec_b>;
1860			iommus = <&p1_smmu_alg_b 0x600>;
1861			dma-coherent;
1862			interrupts = <576 4>,
1863				     <577 1>, <578 4>,
1864				     <579 1>, <580 4>,
1865				     <581 1>, <582 4>,
1866				     <583 1>, <584 4>,
1867				     <585 1>, <586 4>,
1868				     <587 1>, <588 4>,
1869				     <589 1>, <590 4>,
1870				     <591 1>, <592 4>,
1871				     <593 1>, <594 4>,
1872				     <595 1>, <596 4>,
1873				     <597 1>, <598 4>,
1874				     <599 1>, <600 4>,
1875				     <601 1>, <602 4>,
1876				     <603 1>, <604 4>,
1877				     <605 1>, <606 4>,
1878				     <607 1>, <608 4>;
1879		};
1880
1881	};
1882};
1883