1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for lg1312 SoC
4 *
5 * Copyright (C) 2016, LG Electronics
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	compatible = "lge,lg1312";
16	interrupt-parent = <&gic>;
17
18	cpus {
19		#address-cells = <2>;
20		#size-cells = <0>;
21
22		cpu0: cpu@0 {
23			device_type = "cpu";
24			compatible = "arm,cortex-a53";
25			reg = <0x0 0x0>;
26			next-level-cache = <&L2_0>;
27		};
28		cpu1: cpu@1 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a53";
31			reg = <0x0 0x1>;
32			enable-method = "psci";
33			next-level-cache = <&L2_0>;
34		};
35		cpu2: cpu@2 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53";
38			reg = <0x0 0x2>;
39			enable-method = "psci";
40			next-level-cache = <&L2_0>;
41		};
42		cpu3: cpu@3 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a53";
45			reg = <0x0 0x3>;
46			enable-method = "psci";
47			next-level-cache = <&L2_0>;
48		};
49		L2_0: l2-cache0 {
50			compatible = "cache";
51		};
52	};
53
54	psci {
55		compatible = "arm,psci-0.2", "arm,psci";
56		method = "smc";
57		cpu_suspend = <0x84000001>;
58		cpu_off = <0x84000002>;
59		cpu_on = <0x84000003>;
60	};
61
62	gic: interrupt-controller@c0001000 {
63		#interrupt-cells = <3>;
64		compatible = "arm,gic-400";
65		interrupt-controller;
66		reg = <0x0 0xc0001000 0x1000>,
67		      <0x0 0xc0002000 0x2000>,
68		      <0x0 0xc0004000 0x2000>,
69		      <0x0 0xc0006000 0x2000>;
70	};
71
72	pmu {
73		compatible = "arm,cortex-a53-pmu";
74		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
75			     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
76			     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
77			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
78		interrupt-affinity = <&cpu0>,
79				     <&cpu1>,
80				     <&cpu2>,
81				     <&cpu3>;
82	};
83
84	timer {
85		compatible = "arm,armv8-timer";
86		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
87			      IRQ_TYPE_LEVEL_LOW)>,
88			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
89			      IRQ_TYPE_LEVEL_LOW)>,
90			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
91			      IRQ_TYPE_LEVEL_LOW)>,
92			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
93			      IRQ_TYPE_LEVEL_LOW)>;
94	};
95
96	clk_bus: clk_bus {
97		#clock-cells = <0>;
98
99		compatible = "fixed-clock";
100		clock-frequency = <198000000>;
101		clock-output-names = "BUSCLK";
102	};
103
104	soc {
105		#address-cells = <2>;
106		#size-cells = <1>;
107
108		compatible = "simple-bus";
109		interrupt-parent = <&gic>;
110		ranges;
111
112		eth0: ethernet@c1b00000 {
113			compatible = "cdns,gem";
114			reg = <0x0 0xc1b00000 0x1000>;
115			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
116			clocks = <&clk_bus>, <&clk_bus>;
117			clock-names = "hclk", "pclk";
118			phy-mode = "rmii";
119			/* Filled in by boot */
120			mac-address = [ 00 00 00 00 00 00 ];
121		};
122	};
123
124	amba {
125		#address-cells = <2>;
126		#size-cells = <1>;
127		#interrupt-cells = <3>;
128
129		compatible = "simple-bus";
130		interrupt-parent = <&gic>;
131		ranges;
132
133		timers: timer@fd100000 {
134			compatible = "arm,sp804", "arm,primecell";
135			reg = <0x0 0xfd100000 0x1000>;
136			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
137			clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
138			clock-names = "timer0clk", "timer1clk", "apb_pclk";
139		};
140		wdog: watchdog@fd200000 {
141			compatible = "arm,sp805", "arm,primecell";
142			reg = <0x0 0xfd200000 0x1000>;
143			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
144			clocks = <&clk_bus>, <&clk_bus>;
145			clock-names = "wdog_clk", "apb_pclk";
146		};
147		uart0: serial@fe000000 {
148			compatible = "arm,pl011", "arm,primecell";
149			reg = <0x0 0xfe000000 0x1000>;
150			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
151			clocks = <&clk_bus>;
152			clock-names = "apb_pclk";
153			status = "disabled";
154		};
155		uart1: serial@fe100000 {
156			compatible = "arm,pl011", "arm,primecell";
157			reg = <0x0 0xfe100000 0x1000>;
158			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
159			clocks = <&clk_bus>;
160			clock-names = "apb_pclk";
161			status = "disabled";
162		};
163		uart2: serial@fe200000 {
164			compatible = "arm,pl011", "arm,primecell";
165			reg = <0x0 0xfe200000 0x1000>;
166			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
167			clocks = <&clk_bus>;
168			clock-names = "apb_pclk";
169			status = "disabled";
170		};
171		spi0: spi@fe800000 {
172			compatible = "arm,pl022", "arm,primecell";
173			reg = <0x0 0xfe800000 0x1000>;
174			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
175			clocks = <&clk_bus>;
176			clock-names = "apb_pclk";
177		};
178		spi1: spi@fe900000 {
179			compatible = "arm,pl022", "arm,primecell";
180			reg = <0x0 0xfe900000 0x1000>;
181			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
182			clocks = <&clk_bus>;
183			clock-names = "apb_pclk";
184		};
185		dmac0: dma-controller@c1128000 {
186			compatible = "arm,pl330", "arm,primecell";
187			reg = <0x0 0xc1128000 0x1000>;
188			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
189			clocks = <&clk_bus>;
190			clock-names = "apb_pclk";
191			#dma-cells = <1>;
192		};
193		gpio0: gpio@fd400000 {
194			#gpio-cells = <2>;
195			compatible = "arm,pl061", "arm,primecell";
196			gpio-controller;
197			reg = <0x0 0xfd400000 0x1000>;
198			clocks = <&clk_bus>;
199			clock-names = "apb_pclk";
200			status = "disabled";
201		};
202		gpio1: gpio@fd410000 {
203			#gpio-cells = <2>;
204			compatible = "arm,pl061", "arm,primecell";
205			gpio-controller;
206			reg = <0x0 0xfd410000 0x1000>;
207			clocks = <&clk_bus>;
208			clock-names = "apb_pclk";
209			status = "disabled";
210		};
211		gpio2: gpio@fd420000 {
212			#gpio-cells = <2>;
213			compatible = "arm,pl061", "arm,primecell";
214			gpio-controller;
215			reg = <0x0 0xfd420000 0x1000>;
216			clocks = <&clk_bus>;
217			clock-names = "apb_pclk";
218			status = "disabled";
219		};
220		gpio3: gpio@fd430000 {
221			#gpio-cells = <2>;
222			compatible = "arm,pl061", "arm,primecell";
223			gpio-controller;
224			reg = <0x0 0xfd430000 0x1000>;
225			clocks = <&clk_bus>;
226			clock-names = "apb_pclk";
227		};
228		gpio4: gpio@fd440000 {
229			#gpio-cells = <2>;
230			compatible = "arm,pl061", "arm,primecell";
231			gpio-controller;
232			reg = <0x0 0xfd440000 0x1000>;
233			clocks = <&clk_bus>;
234			clock-names = "apb_pclk";
235			status = "disabled";
236		};
237		gpio5: gpio@fd450000 {
238			#gpio-cells = <2>;
239			compatible = "arm,pl061", "arm,primecell";
240			gpio-controller;
241			reg = <0x0 0xfd450000 0x1000>;
242			clocks = <&clk_bus>;
243			clock-names = "apb_pclk";
244			status = "disabled";
245		};
246		gpio6: gpio@fd460000 {
247			#gpio-cells = <2>;
248			compatible = "arm,pl061", "arm,primecell";
249			gpio-controller;
250			reg = <0x0 0xfd460000 0x1000>;
251			clocks = <&clk_bus>;
252			clock-names = "apb_pclk";
253			status = "disabled";
254		};
255		gpio7: gpio@fd470000 {
256			#gpio-cells = <2>;
257			compatible = "arm,pl061", "arm,primecell";
258			gpio-controller;
259			reg = <0x0 0xfd470000 0x1000>;
260			clocks = <&clk_bus>;
261			clock-names = "apb_pclk";
262			status = "disabled";
263		};
264		gpio8: gpio@fd480000 {
265			#gpio-cells = <2>;
266			compatible = "arm,pl061", "arm,primecell";
267			gpio-controller;
268			reg = <0x0 0xfd480000 0x1000>;
269			clocks = <&clk_bus>;
270			clock-names = "apb_pclk";
271			status = "disabled";
272		};
273		gpio9: gpio@fd490000 {
274			#gpio-cells = <2>;
275			compatible = "arm,pl061", "arm,primecell";
276			gpio-controller;
277			reg = <0x0 0xfd490000 0x1000>;
278			clocks = <&clk_bus>;
279			clock-names = "apb_pclk";
280			status = "disabled";
281		};
282		gpio10: gpio@fd4a0000 {
283			#gpio-cells = <2>;
284			compatible = "arm,pl061", "arm,primecell";
285			gpio-controller;
286			reg = <0x0 0xfd4a0000 0x1000>;
287			clocks = <&clk_bus>;
288			clock-names = "apb_pclk";
289			status = "disabled";
290		};
291		gpio11: gpio@fd4b0000 {
292			#gpio-cells = <2>;
293			compatible = "arm,pl061", "arm,primecell";
294			gpio-controller;
295			reg = <0x0 0xfd4b0000 0x1000>;
296			clocks = <&clk_bus>;
297			clock-names = "apb_pclk";
298		};
299		gpio12: gpio@fd4c0000 {
300			#gpio-cells = <2>;
301			compatible = "arm,pl061", "arm,primecell";
302			gpio-controller;
303			reg = <0x0 0xfd4c0000 0x1000>;
304			clocks = <&clk_bus>;
305			clock-names = "apb_pclk";
306			status = "disabled";
307		};
308		gpio13: gpio@fd4d0000 {
309			#gpio-cells = <2>;
310			compatible = "arm,pl061", "arm,primecell";
311			gpio-controller;
312			reg = <0x0 0xfd4d0000 0x1000>;
313			clocks = <&clk_bus>;
314			clock-names = "apb_pclk";
315			status = "disabled";
316		};
317		gpio14: gpio@fd4e0000 {
318			#gpio-cells = <2>;
319			compatible = "arm,pl061", "arm,primecell";
320			gpio-controller;
321			reg = <0x0 0xfd4e0000 0x1000>;
322			clocks = <&clk_bus>;
323			clock-names = "apb_pclk";
324			status = "disabled";
325		};
326		gpio15: gpio@fd4f0000 {
327			#gpio-cells = <2>;
328			compatible = "arm,pl061", "arm,primecell";
329			gpio-controller;
330			reg = <0x0 0xfd4f0000 0x1000>;
331			clocks = <&clk_bus>;
332			clock-names = "apb_pclk";
333			status = "disabled";
334		};
335		gpio16: gpio@fd500000 {
336			#gpio-cells = <2>;
337			compatible = "arm,pl061", "arm,primecell";
338			gpio-controller;
339			reg = <0x0 0xfd500000 0x1000>;
340			clocks = <&clk_bus>;
341			clock-names = "apb_pclk";
342			status = "disabled";
343		};
344		gpio17: gpio@fd510000 {
345			#gpio-cells = <2>;
346			compatible = "arm,pl061", "arm,primecell";
347			gpio-controller;
348			reg = <0x0 0xfd510000 0x1000>;
349			clocks = <&clk_bus>;
350			clock-names = "apb_pclk";
351		};
352	};
353};
354