1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree For AC5.
4 *
5 * Copyright (C) 2021 Marvell
6 * Copyright (C) 2022 Allied Telesis Labs
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	model = "Marvell AC5 SoC";
14	compatible = "marvell,ac5";
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <2>;
21		#size-cells = <0>;
22
23		cpu-map {
24			cluster0 {
25				core0 {
26					cpu = <&cpu0>;
27				};
28				core1 {
29					cpu = <&cpu1>;
30				};
31			};
32		};
33
34		cpu0: cpu@0 {
35			device_type = "cpu";
36			compatible = "arm,cortex-a55";
37			reg = <0x0 0x0>;
38			enable-method = "psci";
39			next-level-cache = <&l2>;
40		};
41
42		cpu1: cpu@1 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a55";
45			reg = <0x0 0x100>;
46			enable-method = "psci";
47			next-level-cache = <&l2>;
48		};
49
50		l2: l2-cache {
51			compatible = "cache";
52		};
53	};
54
55	psci {
56		compatible = "arm,psci-0.2";
57		method = "smc";
58	};
59
60	timer {
61		compatible = "arm,armv8-timer";
62		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
63			     <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
64			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
65			     <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
66	};
67
68	pmu {
69		compatible = "arm,armv8-pmuv3";
70		interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
71	};
72
73	soc {
74		compatible = "simple-bus";
75		#address-cells = <2>;
76		#size-cells = <2>;
77		ranges;
78		dma-ranges;
79
80		internal-regs@7f000000 {
81			#address-cells = <1>;
82			#size-cells = <1>;
83			compatible = "simple-bus";
84			/* 16M internal register @ 0x7f00_0000 */
85			ranges = <0x0 0x0 0x7f000000 0x1000000>;
86			dma-coherent;
87
88			uart0: serial@12000 {
89				compatible = "snps,dw-apb-uart";
90				reg = <0x12000 0x100>;
91				reg-shift = <2>;
92				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
93				reg-io-width = <1>;
94				clocks = <&cnm_clock>;
95				status = "okay";
96			};
97
98			mdio: mdio@22004 {
99				#address-cells = <1>;
100				#size-cells = <0>;
101				compatible = "marvell,orion-mdio";
102				reg = <0x22004 0x4>;
103				clocks = <&cnm_clock>;
104			};
105
106			i2c0: i2c@11000{
107				compatible = "marvell,mv78230-i2c";
108				reg = <0x11000 0x20>;
109				#address-cells = <1>;
110				#size-cells = <0>;
111
112				clocks = <&cnm_clock>;
113				clock-names = "core";
114				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
115				clock-frequency=<100000>;
116
117				pinctrl-names = "default", "gpio";
118				pinctrl-0 = <&i2c0_pins>;
119				pinctrl-1 = <&i2c0_gpio>;
120				scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
121				sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
122				status = "disabled";
123			};
124
125			i2c1: i2c@11100{
126				compatible = "marvell,mv78230-i2c";
127				reg = <0x11100 0x20>;
128				#address-cells = <1>;
129				#size-cells = <0>;
130
131				clocks = <&cnm_clock>;
132				clock-names = "core";
133				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
134				clock-frequency=<100000>;
135
136				pinctrl-names = "default", "gpio";
137				pinctrl-0 = <&i2c1_pins>;
138				pinctrl-1 = <&i2c1_gpio>;
139				scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
140				sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
141				status = "disabled";
142			};
143
144			gpio0: gpio@18100 {
145				compatible = "marvell,orion-gpio";
146				reg = <0x18100 0x40>;
147				ngpios = <32>;
148				gpio-controller;
149				#gpio-cells = <2>;
150				gpio-ranges = <&pinctrl0 0 0 32>;
151				marvell,pwm-offset = <0x1f0>;
152				interrupt-controller;
153				#interrupt-cells = <2>;
154				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
155					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
156					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
157					     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
158			};
159
160			gpio1: gpio@18140 {
161				reg = <0x18140 0x40>;
162				compatible = "marvell,orion-gpio";
163				ngpios = <14>;
164				gpio-controller;
165				#gpio-cells = <2>;
166				gpio-ranges = <&pinctrl0 0 32 14>;
167				marvell,pwm-offset = <0x1f0>;
168				interrupt-controller;
169				#interrupt-cells = <2>;
170				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
171					     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
172			};
173		};
174
175		/*
176		 * Dedicated section for devices behind 32bit controllers so we
177		 * can configure specific DMA mapping for them
178		 */
179		behind-32bit-controller@7f000000 {
180			compatible = "simple-bus";
181			#address-cells = <0x2>;
182			#size-cells = <0x2>;
183			ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
184			/* Host phy ram starts at 0x200M */
185			dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
186			dma-coherent;
187
188			eth0: ethernet@20000 {
189				compatible = "marvell,armada-ac5-neta";
190				reg = <0x0 0x20000 0x0 0x4000>;
191				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
192				clocks = <&cnm_clock>;
193				phy-mode = "sgmii";
194				status = "disabled";
195			};
196
197			eth1: ethernet@24000 {
198				compatible = "marvell,armada-ac5-neta";
199				reg = <0x0 0x24000 0x0 0x4000>;
200				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
201				clocks = <&cnm_clock>;
202				phy-mode = "sgmii";
203				status = "disabled";
204			};
205
206			usb0: usb@80000 {
207				compatible = "marvell,orion-ehci";
208				reg = <0x0 0x80000 0x0 0x500>;
209				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
210				status = "disabled";
211			};
212
213			usb1: usb@a0000 {
214				compatible = "marvell,orion-ehci";
215				reg = <0x0 0xa0000 0x0 0x500>;
216				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
217				status = "disabled";
218			};
219		};
220
221		pinctrl0: pinctrl@80020100 {
222			compatible = "marvell,ac5-pinctrl";
223			reg = <0 0x80020100 0 0x20>;
224
225			i2c0_pins: i2c0-pins {
226				marvell,pins = "mpp26", "mpp27";
227				marvell,function = "i2c0";
228			};
229
230			i2c0_gpio: i2c0-gpio-pins {
231				marvell,pins = "mpp26", "mpp27";
232				marvell,function = "gpio";
233			};
234
235			i2c1_pins: i2c1-pins {
236				marvell,pins = "mpp20", "mpp21";
237				marvell,function = "i2c1";
238			};
239
240			i2c1_gpio: i2c1-gpio-pins {
241				marvell,pins = "mpp20", "mpp21";
242				marvell,function = "i2c1";
243			};
244		};
245
246		spi0: spi@805a0000 {
247			compatible = "marvell,armada-3700-spi";
248			reg = <0x0 0x805a0000 0x0 0x50>;
249			#address-cells = <0x1>;
250			#size-cells = <0x0>;
251			clocks = <&spi_clock>;
252			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
253			num-cs = <1>;
254			status = "disabled";
255		};
256
257		spi1: spi@805a8000 {
258			compatible = "marvell,armada-3700-spi";
259			reg = <0x0 0x805a8000 0x0 0x50>;
260			#address-cells = <0x1>;
261			#size-cells = <0x0>;
262			clocks = <&spi_clock>;
263			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
264			num-cs = <1>;
265			status = "disabled";
266		};
267
268		gic: interrupt-controller@80600000 {
269			compatible = "arm,gic-v3";
270			#interrupt-cells = <3>;
271			interrupt-controller;
272			reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
273			      <0x0 0x80660000 0x0 0x40000>; /* GICR */
274			interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
275		};
276	};
277
278	clocks {
279		cnm_clock: cnm-clock {
280			compatible = "fixed-clock";
281			#clock-cells = <0>;
282			clock-frequency = <328000000>;
283		};
284
285		spi_clock: spi-clock {
286			compatible = "fixed-clock";
287			#clock-cells = <0>;
288			clock-frequency = <200000000>;
289		};
290	};
291};
292