1*c66ec88fSEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*c66ec88fSEmmanuel Vadot/* 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2017 Marvell Technology Group Ltd. 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot * Device Tree file for the Armada 80x0 SoC family 6*c66ec88fSEmmanuel Vadot */ 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot/ { 9*c66ec88fSEmmanuel Vadot aliases { 10*c66ec88fSEmmanuel Vadot gpio1 = &cp1_gpio1; 11*c66ec88fSEmmanuel Vadot gpio2 = &cp0_gpio2; 12*c66ec88fSEmmanuel Vadot spi1 = &cp0_spi0; 13*c66ec88fSEmmanuel Vadot spi2 = &cp0_spi1; 14*c66ec88fSEmmanuel Vadot spi3 = &cp1_spi0; 15*c66ec88fSEmmanuel Vadot spi4 = &cp1_spi1; 16*c66ec88fSEmmanuel Vadot }; 17*c66ec88fSEmmanuel Vadot}; 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel Vadot/* 20*c66ec88fSEmmanuel Vadot * Instantiate the master CP110 21*c66ec88fSEmmanuel Vadot */ 22*c66ec88fSEmmanuel Vadot#define CP11X_NAME cp0 23*c66ec88fSEmmanuel Vadot#define CP11X_BASE f2000000 24*c66ec88fSEmmanuel Vadot#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) 25*c66ec88fSEmmanuel Vadot#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 26*c66ec88fSEmmanuel Vadot#define CP11X_PCIE0_BASE f2600000 27*c66ec88fSEmmanuel Vadot#define CP11X_PCIE1_BASE f2620000 28*c66ec88fSEmmanuel Vadot#define CP11X_PCIE2_BASE f2640000 29*c66ec88fSEmmanuel Vadot 30*c66ec88fSEmmanuel Vadot#include "armada-cp110.dtsi" 31*c66ec88fSEmmanuel Vadot 32*c66ec88fSEmmanuel Vadot#undef CP11X_NAME 33*c66ec88fSEmmanuel Vadot#undef CP11X_BASE 34*c66ec88fSEmmanuel Vadot#undef CP11X_PCIEx_MEM_BASE 35*c66ec88fSEmmanuel Vadot#undef CP11X_PCIEx_MEM_SIZE 36*c66ec88fSEmmanuel Vadot#undef CP11X_PCIE0_BASE 37*c66ec88fSEmmanuel Vadot#undef CP11X_PCIE1_BASE 38*c66ec88fSEmmanuel Vadot#undef CP11X_PCIE2_BASE 39*c66ec88fSEmmanuel Vadot 40*c66ec88fSEmmanuel Vadot/* 41*c66ec88fSEmmanuel Vadot * Instantiate the slave CP110 42*c66ec88fSEmmanuel Vadot */ 43*c66ec88fSEmmanuel Vadot#define CP11X_NAME cp1 44*c66ec88fSEmmanuel Vadot#define CP11X_BASE f4000000 45*c66ec88fSEmmanuel Vadot#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000)) 46*c66ec88fSEmmanuel Vadot#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 47*c66ec88fSEmmanuel Vadot#define CP11X_PCIE0_BASE f4600000 48*c66ec88fSEmmanuel Vadot#define CP11X_PCIE1_BASE f4620000 49*c66ec88fSEmmanuel Vadot#define CP11X_PCIE2_BASE f4640000 50*c66ec88fSEmmanuel Vadot 51*c66ec88fSEmmanuel Vadot#include "armada-cp110.dtsi" 52*c66ec88fSEmmanuel Vadot 53*c66ec88fSEmmanuel Vadot#undef CP11X_NAME 54*c66ec88fSEmmanuel Vadot#undef CP11X_BASE 55*c66ec88fSEmmanuel Vadot#undef CP11X_PCIEx_MEM_BASE 56*c66ec88fSEmmanuel Vadot#undef CP11X_PCIEx_MEM_SIZE 57*c66ec88fSEmmanuel Vadot#undef CP11X_PCIE0_BASE 58*c66ec88fSEmmanuel Vadot#undef CP11X_PCIE1_BASE 59*c66ec88fSEmmanuel Vadot#undef CP11X_PCIE2_BASE 60*c66ec88fSEmmanuel Vadot 61*c66ec88fSEmmanuel Vadot/* The 80x0 has two CP blocks, but uses only one block from each. */ 62*c66ec88fSEmmanuel Vadot&cp1_gpio1 { 63*c66ec88fSEmmanuel Vadot status = "okay"; 64*c66ec88fSEmmanuel Vadot}; 65*c66ec88fSEmmanuel Vadot 66*c66ec88fSEmmanuel Vadot&cp0_gpio2 { 67*c66ec88fSEmmanuel Vadot status = "okay"; 68*c66ec88fSEmmanuel Vadot}; 69*c66ec88fSEmmanuel Vadot 70*c66ec88fSEmmanuel Vadot&cp0_syscon0 { 71*c66ec88fSEmmanuel Vadot cp0_pinctrl: pinctrl { 72*c66ec88fSEmmanuel Vadot compatible = "marvell,armada-8k-cpm-pinctrl"; 73*c66ec88fSEmmanuel Vadot }; 74*c66ec88fSEmmanuel Vadot}; 75*c66ec88fSEmmanuel Vadot 76*c66ec88fSEmmanuel Vadot&cp1_syscon0 { 77*c66ec88fSEmmanuel Vadot cp1_pinctrl: pinctrl { 78*c66ec88fSEmmanuel Vadot compatible = "marvell,armada-8k-cps-pinctrl"; 79*c66ec88fSEmmanuel Vadot 80*c66ec88fSEmmanuel Vadot nand_pins: nand-pins { 81*c66ec88fSEmmanuel Vadot marvell,pins = 82*c66ec88fSEmmanuel Vadot "mpp0", "mpp1", "mpp2", "mpp3", 83*c66ec88fSEmmanuel Vadot "mpp4", "mpp5", "mpp6", "mpp7", 84*c66ec88fSEmmanuel Vadot "mpp8", "mpp9", "mpp10", "mpp11", 85*c66ec88fSEmmanuel Vadot "mpp15", "mpp16", "mpp17", "mpp18", 86*c66ec88fSEmmanuel Vadot "mpp19", "mpp20", "mpp21", "mpp22", 87*c66ec88fSEmmanuel Vadot "mpp23", "mpp24", "mpp25", "mpp26", 88*c66ec88fSEmmanuel Vadot "mpp27"; 89*c66ec88fSEmmanuel Vadot marvell,function = "dev"; 90*c66ec88fSEmmanuel Vadot }; 91*c66ec88fSEmmanuel Vadot 92*c66ec88fSEmmanuel Vadot nand_rb: nand-rb { 93*c66ec88fSEmmanuel Vadot marvell,pins = "mpp13", "mpp12"; 94*c66ec88fSEmmanuel Vadot marvell,function = "nf"; 95*c66ec88fSEmmanuel Vadot }; 96*c66ec88fSEmmanuel Vadot }; 97*c66ec88fSEmmanuel Vadot}; 98*c66ec88fSEmmanuel Vadot 99*c66ec88fSEmmanuel Vadot&cp1_crypto { 100*c66ec88fSEmmanuel Vadot /* 101*c66ec88fSEmmanuel Vadot * The cryptographic engine found on the cp110 102*c66ec88fSEmmanuel Vadot * master is enabled by default at the SoC 103*c66ec88fSEmmanuel Vadot * level. Because it is not possible as of now 104*c66ec88fSEmmanuel Vadot * to enable two cryptographic engines in 105*c66ec88fSEmmanuel Vadot * parallel, disable this one by default. 106*c66ec88fSEmmanuel Vadot */ 107*c66ec88fSEmmanuel Vadot status = "disabled"; 108*c66ec88fSEmmanuel Vadot}; 109