1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Mars.C <mars.cheng@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mediatek,mt6795-clk.h>
10#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
11#include <dt-bindings/power/mt6795-power.h>
12#include <dt-bindings/reset/mediatek,mt6795-resets.h>
13
14/ {
15	compatible = "mediatek,mt6795";
16	interrupt-parent = <&sysirq>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	psci {
21		compatible = "arm,psci-0.2";
22		method = "smc";
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@0 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a53";
32			enable-method = "psci";
33			reg = <0x000>;
34			cci-control-port = <&cci_control2>;
35			next-level-cache = <&l2_0>;
36		};
37
38		cpu1: cpu@1 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a53";
41			enable-method = "psci";
42			reg = <0x001>;
43			cci-control-port = <&cci_control2>;
44			i-cache-size = <32768>;
45			i-cache-line-size = <64>;
46			i-cache-sets = <256>;
47			d-cache-size = <32768>;
48			d-cache-line-size = <64>;
49			d-cache-sets = <128>;
50			next-level-cache = <&l2_0>;
51		};
52
53		cpu2: cpu@2 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a53";
56			enable-method = "psci";
57			reg = <0x002>;
58			cci-control-port = <&cci_control2>;
59			i-cache-size = <32768>;
60			i-cache-line-size = <64>;
61			i-cache-sets = <256>;
62			d-cache-size = <32768>;
63			d-cache-line-size = <64>;
64			d-cache-sets = <128>;
65			next-level-cache = <&l2_0>;
66		};
67
68		cpu3: cpu@3 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a53";
71			enable-method = "psci";
72			reg = <0x003>;
73			cci-control-port = <&cci_control2>;
74			i-cache-size = <32768>;
75			i-cache-line-size = <64>;
76			i-cache-sets = <256>;
77			d-cache-size = <32768>;
78			d-cache-line-size = <64>;
79			d-cache-sets = <128>;
80			next-level-cache = <&l2_0>;
81		};
82
83		cpu4: cpu@100 {
84			device_type = "cpu";
85			compatible = "arm,cortex-a53";
86			enable-method = "psci";
87			reg = <0x100>;
88			cci-control-port = <&cci_control1>;
89			i-cache-size = <32768>;
90			i-cache-line-size = <64>;
91			i-cache-sets = <256>;
92			d-cache-size = <32768>;
93			d-cache-line-size = <64>;
94			d-cache-sets = <128>;
95			next-level-cache = <&l2_1>;
96		};
97
98		cpu5: cpu@101 {
99			device_type = "cpu";
100			compatible = "arm,cortex-a53";
101			enable-method = "psci";
102			reg = <0x101>;
103			cci-control-port = <&cci_control1>;
104			i-cache-size = <32768>;
105			i-cache-line-size = <64>;
106			i-cache-sets = <256>;
107			d-cache-size = <32768>;
108			d-cache-line-size = <64>;
109			d-cache-sets = <128>;
110			next-level-cache = <&l2_1>;
111		};
112
113		cpu6: cpu@102 {
114			device_type = "cpu";
115			compatible = "arm,cortex-a53";
116			enable-method = "psci";
117			reg = <0x102>;
118			cci-control-port = <&cci_control1>;
119			i-cache-size = <32768>;
120			i-cache-line-size = <64>;
121			i-cache-sets = <256>;
122			d-cache-size = <32768>;
123			d-cache-line-size = <64>;
124			d-cache-sets = <128>;
125			next-level-cache = <&l2_1>;
126		};
127
128		cpu7: cpu@103 {
129			device_type = "cpu";
130			compatible = "arm,cortex-a53";
131			enable-method = "psci";
132			reg = <0x103>;
133			cci-control-port = <&cci_control1>;
134			i-cache-size = <32768>;
135			i-cache-line-size = <64>;
136			i-cache-sets = <256>;
137			d-cache-size = <32768>;
138			d-cache-line-size = <64>;
139			d-cache-sets = <128>;
140			next-level-cache = <&l2_1>;
141		};
142
143		cpu-map {
144			cluster0 {
145				core0 {
146					cpu = <&cpu0>;
147				};
148
149				core1 {
150					cpu = <&cpu1>;
151				};
152
153				core2 {
154					cpu = <&cpu2>;
155				};
156
157				core3 {
158					cpu = <&cpu3>;
159				};
160			};
161
162			cluster1 {
163				core0 {
164					cpu = <&cpu4>;
165				};
166
167				core1 {
168					cpu = <&cpu5>;
169				};
170
171				core2 {
172					cpu = <&cpu6>;
173				};
174
175				core3 {
176					cpu = <&cpu7>;
177				};
178			};
179		};
180
181		l2_0: l2-cache0 {
182			compatible = "cache";
183			cache-level = <2>;
184			cache-size = <1048576>;
185			cache-line-size = <64>;
186			cache-sets = <1024>;
187			cache-unified;
188		};
189
190		l2_1: l2-cache1 {
191			compatible = "cache";
192			cache-level = <2>;
193			cache-size = <1048576>;
194			cache-line-size = <64>;
195			cache-sets = <1024>;
196			cache-unified;
197		};
198	};
199
200	clk26m: oscillator-26m {
201		compatible = "fixed-clock";
202		#clock-cells = <0>;
203		clock-frequency = <26000000>;
204		clock-output-names = "clk26m";
205	};
206
207	clk32k: oscillator-32k {
208		compatible = "fixed-clock";
209		#clock-cells = <0>;
210		clock-frequency = <32000>;
211		clock-output-names = "clk32k";
212	};
213
214	system_clk: dummy13m {
215		compatible = "fixed-clock";
216		clock-frequency = <13000000>;
217		#clock-cells = <0>;
218	};
219
220	pmu {
221		compatible = "arm,cortex-a53-pmu";
222		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
223			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
224			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
225			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
226		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
227	};
228
229	timer {
230		compatible = "arm,armv8-timer";
231		interrupt-parent = <&gic>;
232		interrupts = <GIC_PPI 13
233			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
234			     <GIC_PPI 14
235			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
236			     <GIC_PPI 11
237			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
238			     <GIC_PPI 10
239			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
240	};
241
242	soc {
243		#address-cells = <2>;
244		#size-cells = <2>;
245		compatible = "simple-bus";
246		ranges;
247
248		topckgen: syscon@10000000 {
249			compatible = "mediatek,mt6795-topckgen", "syscon";
250			reg = <0 0x10000000 0 0x1000>;
251			#clock-cells = <1>;
252		};
253
254		infracfg: syscon@10001000 {
255			compatible = "mediatek,mt6795-infracfg", "syscon";
256			reg = <0 0x10001000 0 0x1000>;
257			#clock-cells = <1>;
258			#reset-cells = <1>;
259		};
260
261		pericfg: syscon@10003000 {
262			compatible = "mediatek,mt6795-pericfg", "syscon";
263			reg = <0 0x10003000 0 0x1000>;
264			#clock-cells = <1>;
265			#reset-cells = <1>;
266		};
267
268		scpsys: syscon@10006000 {
269			compatible = "syscon", "simple-mfd";
270			reg = <0 0x10006000 0 0x1000>;
271			#power-domain-cells = <1>;
272
273			/* System Power Manager */
274			spm: power-controller {
275				compatible = "mediatek,mt6795-power-controller";
276				#address-cells = <1>;
277				#size-cells = <0>;
278				#power-domain-cells = <1>;
279
280				/* power domains of the SoC */
281				power-domain@MT6795_POWER_DOMAIN_VDEC {
282					reg = <MT6795_POWER_DOMAIN_VDEC>;
283					clocks = <&topckgen CLK_TOP_MM_SEL>;
284					clock-names = "mm";
285					#power-domain-cells = <0>;
286				};
287				power-domain@MT6795_POWER_DOMAIN_VENC {
288					reg = <MT6795_POWER_DOMAIN_VENC>;
289					clocks = <&topckgen CLK_TOP_MM_SEL>,
290						 <&topckgen CLK_TOP_VENC_SEL>;
291					clock-names = "mm", "venc";
292					#power-domain-cells = <0>;
293				};
294				power-domain@MT6795_POWER_DOMAIN_ISP {
295					reg = <MT6795_POWER_DOMAIN_ISP>;
296					clocks = <&topckgen CLK_TOP_MM_SEL>;
297					clock-names = "mm";
298					#power-domain-cells = <0>;
299				};
300
301				power-domain@MT6795_POWER_DOMAIN_MM {
302					reg = <MT6795_POWER_DOMAIN_MM>;
303					clocks = <&topckgen CLK_TOP_MM_SEL>;
304					clock-names = "mm";
305					#power-domain-cells = <0>;
306					mediatek,infracfg = <&infracfg>;
307				};
308
309				power-domain@MT6795_POWER_DOMAIN_MJC {
310					reg = <MT6795_POWER_DOMAIN_MJC>;
311					clocks = <&topckgen CLK_TOP_MM_SEL>,
312						 <&topckgen CLK_TOP_MJC_SEL>;
313					clock-names = "mm", "mjc";
314					#power-domain-cells = <0>;
315				};
316
317				power-domain@MT6795_POWER_DOMAIN_AUDIO {
318					reg = <MT6795_POWER_DOMAIN_AUDIO>;
319					#power-domain-cells = <0>;
320				};
321
322				mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC {
323					reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>;
324					clocks = <&clk26m>;
325					clock-names = "mfg";
326					#address-cells = <1>;
327					#size-cells = <0>;
328					#power-domain-cells = <1>;
329
330					power-domain@MT6795_POWER_DOMAIN_MFG_2D {
331						reg = <MT6795_POWER_DOMAIN_MFG_2D>;
332						#address-cells = <1>;
333						#size-cells = <0>;
334						#power-domain-cells = <1>;
335
336						power-domain@MT6795_POWER_DOMAIN_MFG {
337							reg = <MT6795_POWER_DOMAIN_MFG>;
338							#power-domain-cells = <0>;
339							mediatek,infracfg = <&infracfg>;
340						};
341					};
342				};
343			};
344		};
345
346		pio: pinctrl@10005000 {
347			compatible = "mediatek,mt6795-pinctrl";
348			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
349			reg-names = "base", "eint";
350			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
351				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
352			gpio-controller;
353			#gpio-cells = <2>;
354			gpio-ranges = <&pio 0 0 196>;
355			interrupt-controller;
356			#interrupt-cells = <2>;
357		};
358
359		watchdog: watchdog@10007000 {
360			compatible = "mediatek,mt6795-wdt";
361			reg = <0 0x10007000 0 0x100>;
362			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
363			#reset-cells = <1>;
364			timeout-sec = <20>;
365		};
366
367		timer: timer@10008000 {
368			compatible = "mediatek,mt6795-timer",
369				     "mediatek,mt6577-timer";
370			reg = <0 0x10008000 0 0x1000>;
371			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
372			clocks = <&system_clk>, <&clk32k>;
373		};
374
375		sysirq: intpol-controller@10200620 {
376			compatible = "mediatek,mt6795-sysirq",
377				     "mediatek,mt6577-sysirq";
378			interrupt-controller;
379			#interrupt-cells = <3>;
380			interrupt-parent = <&gic>;
381			reg = <0 0x10200620 0 0x20>;
382		};
383
384		systimer: timer@10200670 {
385			compatible = "mediatek,mt6795-systimer";
386			reg = <0 0x10200670 0 0x10>;
387			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
388			clocks = <&system_clk>;
389			clock-names = "clk13m";
390		};
391
392		apmixedsys: syscon@10209000 {
393			compatible = "mediatek,mt6795-apmixedsys", "syscon";
394			reg = <0 0x10209000 0 0x1000>;
395			#clock-cells = <1>;
396		};
397
398		fhctl: clock-controller@10209f00 {
399			compatible = "mediatek,mt6795-fhctl";
400			reg = <0 0x10209f00 0 0x100>;
401			status = "disabled";
402		};
403
404		gic: interrupt-controller@10221000 {
405			compatible = "arm,gic-400";
406			#interrupt-cells = <3>;
407			interrupt-parent = <&gic>;
408			interrupt-controller;
409			reg = <0 0x10221000 0 0x1000>,
410			      <0 0x10222000 0 0x2000>,
411			      <0 0x10224000 0 0x2000>,
412			      <0 0x10226000 0 0x2000>;
413			interrupts = <GIC_PPI 9
414				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
415		};
416
417		cci: cci@10390000 {
418			compatible = "arm,cci-400";
419			#address-cells = <1>;
420			#size-cells = <1>;
421			reg = <0 0x10390000 0 0x1000>;
422			ranges = <0 0 0x10390000 0x10000>;
423
424			cci_control0: slave-if@1000 {
425				compatible = "arm,cci-400-ctrl-if";
426				interface-type = "ace-lite";
427				reg = <0x1000 0x1000>;
428			};
429
430			cci_control1: slave-if@4000 {
431				compatible = "arm,cci-400-ctrl-if";
432				interface-type = "ace";
433				reg = <0x4000 0x1000>;
434			};
435
436			cci_control2: slave-if@5000 {
437				compatible = "arm,cci-400-ctrl-if";
438				interface-type = "ace";
439				reg = <0x5000 0x1000>;
440			};
441
442			pmu@9000 {
443				compatible = "arm,cci-400-pmu,r1";
444				reg = <0x9000 0x5000>;
445				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
446					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
447					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
448					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
449					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
450			};
451		};
452
453		uart0: serial@11002000 {
454			compatible = "mediatek,mt6795-uart",
455				     "mediatek,mt6577-uart";
456			reg = <0 0x11002000 0 0x400>;
457			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
458			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
459			clock-names = "baud", "bus";
460			dmas = <&apdma 0>, <&apdma 1>;
461			dma-names = "tx", "rx";
462			status = "disabled";
463		};
464
465		uart1: serial@11003000 {
466			compatible = "mediatek,mt6795-uart",
467				     "mediatek,mt6577-uart";
468			reg = <0 0x11003000 0 0x400>;
469			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
470			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
471			clock-names = "baud", "bus";
472			dmas = <&apdma 2>, <&apdma 3>;
473			dma-names = "tx", "rx";
474			status = "disabled";
475		};
476
477		apdma: dma-controller@11000380 {
478			compatible = "mediatek,mt6795-uart-dma",
479				     "mediatek,mt6577-uart-dma";
480			reg = <0 0x11000380 0 0x60>,
481			      <0 0x11000400 0 0x60>,
482			      <0 0x11000480 0 0x60>,
483			      <0 0x11000500 0 0x60>,
484			      <0 0x11000580 0 0x60>,
485			      <0 0x11000600 0 0x60>,
486			      <0 0x11000680 0 0x60>,
487			      <0 0x11000700 0 0x60>;
488			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
489				     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
490				     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
491				     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
492				     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
493				     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
494				     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
495				     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
496			dma-requests = <8>;
497			clocks = <&pericfg CLK_PERI_AP_DMA>;
498			clock-names = "apdma";
499			mediatek,dma-33bits;
500			#dma-cells = <1>;
501		};
502
503		uart2: serial@11004000 {
504			compatible = "mediatek,mt6795-uart",
505				     "mediatek,mt6577-uart";
506			reg = <0 0x11004000 0 0x400>;
507			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
508			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
509			clock-names = "baud", "bus";
510			dmas = <&apdma 4>, <&apdma 5>;
511			dma-names = "tx", "rx";
512			status = "disabled";
513		};
514
515		uart3: serial@11005000 {
516			compatible = "mediatek,mt6795-uart",
517				     "mediatek,mt6577-uart";
518			reg = <0 0x11005000 0 0x400>;
519			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
520			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
521			clock-names = "baud", "bus";
522			dmas = <&apdma 6>, <&apdma 7>;
523			dma-names = "tx", "rx";
524			status = "disabled";
525		};
526
527		pwm2: pwm@11006000 {
528			compatible = "mediatek,mt6795-pwm";
529			reg = <0 0x11006000 0 0x1000>;
530			#pwm-cells = <2>;
531			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
532			clocks = <&topckgen CLK_TOP_PWM_SEL>,
533				 <&pericfg CLK_PERI_PWM>,
534				 <&pericfg CLK_PERI_PWM1>,
535				 <&pericfg CLK_PERI_PWM2>,
536				 <&pericfg CLK_PERI_PWM3>,
537				 <&pericfg CLK_PERI_PWM4>,
538				 <&pericfg CLK_PERI_PWM5>,
539				 <&pericfg CLK_PERI_PWM6>,
540				 <&pericfg CLK_PERI_PWM7>;
541			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
542				      "pwm4", "pwm5", "pwm6", "pwm7";
543			status = "disabled";
544		};
545
546		i2c0: i2c@11007000 {
547			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
548			reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
549			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
550			clock-div = <16>;
551			clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
552			clock-names = "main", "dma";
553			#address-cells = <1>;
554			#size-cells = <0>;
555			status = "disabled";
556		};
557
558		i2c1: i2c@11008000 {
559			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
560			reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>;
561			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
562			clock-div = <16>;
563			clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
564			clock-names = "main", "dma";
565			#address-cells = <1>;
566			#size-cells = <0>;
567			status = "disabled";
568		};
569
570		i2c2: i2c@11009000 {
571			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
572			reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>;
573			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
574			clock-div = <16>;
575			clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
576			clock-names = "main", "dma";
577			#address-cells = <1>;
578			#size-cells = <0>;
579			status = "disabled";
580		};
581
582		i2c3: i2c@11010000 {
583			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
584			reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>;
585			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
586			clock-div = <16>;
587			clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>;
588			clock-names = "main", "dma";
589			#address-cells = <1>;
590			#size-cells = <0>;
591			status = "disabled";
592		};
593
594		i2c4: i2c@11011000 {
595			compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
596			reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>;
597			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
598			clock-div = <16>;
599			clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>;
600			clock-names = "main", "dma";
601			#address-cells = <1>;
602			#size-cells = <0>;
603			status = "disabled";
604		};
605
606		mmc0: mmc@11230000 {
607			compatible = "mediatek,mt6795-mmc";
608			reg = <0 0x11230000 0 0x1000>;
609			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
610			clocks = <&pericfg CLK_PERI_MSDC30_0>,
611				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
612				 <&topckgen CLK_TOP_MSDC50_0_SEL>;
613			clock-names = "source", "hclk", "source_cg";
614			status = "disabled";
615		};
616
617		mmc1: mmc@11240000 {
618			compatible = "mediatek,mt6795-mmc";
619			reg = <0 0x11240000 0 0x1000>;
620			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
621			clocks = <&pericfg CLK_PERI_MSDC30_1>,
622				 <&topckgen CLK_TOP_AXI_SEL>;
623			clock-names = "source", "hclk";
624			status = "disabled";
625		};
626
627		mmc2: mmc@11250000 {
628			compatible = "mediatek,mt6795-mmc";
629			reg = <0 0x11250000 0 0x1000>;
630			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
631			clocks = <&pericfg CLK_PERI_MSDC30_2>,
632				 <&topckgen CLK_TOP_AXI_SEL>;
633			clock-names = "source", "hclk";
634			status = "disabled";
635		};
636
637		mmc3: mmc@11260000 {
638			compatible = "mediatek,mt6795-mmc";
639			reg = <0 0x11260000 0 0x1000>;
640			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
641			clocks = <&pericfg CLK_PERI_MSDC30_3>,
642				 <&topckgen CLK_TOP_AXI_SEL>;
643			clock-names = "source", "hclk";
644			status = "disabled";
645		};
646
647		vdecsys: clock-controller@16000000 {
648			compatible = "mediatek,mt6795-vdecsys";
649			reg = <0 0x16000000 0 0x1000>;
650			#clock-cells = <1>;
651		};
652
653		vencsys: clock-controller@18000000 {
654			compatible = "mediatek,mt6795-vencsys";
655			reg = <0 0x18000000 0 0x1000>;
656			#clock-cells = <1>;
657		};
658	};
659};
660