1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Mars.C <mars.cheng@mediatek.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/mediatek,mt6795-clk.h> 10#include <dt-bindings/gce/mediatek,mt6795-gce.h> 11#include <dt-bindings/memory/mt6795-larb-port.h> 12#include <dt-bindings/pinctrl/mt6795-pinfunc.h> 13#include <dt-bindings/power/mt6795-power.h> 14#include <dt-bindings/reset/mediatek,mt6795-resets.h> 15 16/ { 17 compatible = "mediatek,mt6795"; 18 interrupt-parent = <&sysirq>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 psci { 23 compatible = "arm,psci-0.2"; 24 method = "smc"; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 enable-method = "psci"; 35 reg = <0x000>; 36 cci-control-port = <&cci_control2>; 37 next-level-cache = <&l2_0>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 reg = <0x001>; 45 cci-control-port = <&cci_control2>; 46 i-cache-size = <32768>; 47 i-cache-line-size = <64>; 48 i-cache-sets = <256>; 49 d-cache-size = <32768>; 50 d-cache-line-size = <64>; 51 d-cache-sets = <128>; 52 next-level-cache = <&l2_0>; 53 }; 54 55 cpu2: cpu@2 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x002>; 60 cci-control-port = <&cci_control2>; 61 i-cache-size = <32768>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <256>; 64 d-cache-size = <32768>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <128>; 67 next-level-cache = <&l2_0>; 68 }; 69 70 cpu3: cpu@3 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 enable-method = "psci"; 74 reg = <0x003>; 75 cci-control-port = <&cci_control2>; 76 i-cache-size = <32768>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <256>; 79 d-cache-size = <32768>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <128>; 82 next-level-cache = <&l2_0>; 83 }; 84 85 cpu4: cpu@100 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 enable-method = "psci"; 89 reg = <0x100>; 90 cci-control-port = <&cci_control1>; 91 i-cache-size = <32768>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <32768>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <128>; 97 next-level-cache = <&l2_1>; 98 }; 99 100 cpu5: cpu@101 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 enable-method = "psci"; 104 reg = <0x101>; 105 cci-control-port = <&cci_control1>; 106 i-cache-size = <32768>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <256>; 109 d-cache-size = <32768>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&l2_1>; 113 }; 114 115 cpu6: cpu@102 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 enable-method = "psci"; 119 reg = <0x102>; 120 cci-control-port = <&cci_control1>; 121 i-cache-size = <32768>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <256>; 124 d-cache-size = <32768>; 125 d-cache-line-size = <64>; 126 d-cache-sets = <128>; 127 next-level-cache = <&l2_1>; 128 }; 129 130 cpu7: cpu@103 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53"; 133 enable-method = "psci"; 134 reg = <0x103>; 135 cci-control-port = <&cci_control1>; 136 i-cache-size = <32768>; 137 i-cache-line-size = <64>; 138 i-cache-sets = <256>; 139 d-cache-size = <32768>; 140 d-cache-line-size = <64>; 141 d-cache-sets = <128>; 142 next-level-cache = <&l2_1>; 143 }; 144 145 cpu-map { 146 cluster0 { 147 core0 { 148 cpu = <&cpu0>; 149 }; 150 151 core1 { 152 cpu = <&cpu1>; 153 }; 154 155 core2 { 156 cpu = <&cpu2>; 157 }; 158 159 core3 { 160 cpu = <&cpu3>; 161 }; 162 }; 163 164 cluster1 { 165 core0 { 166 cpu = <&cpu4>; 167 }; 168 169 core1 { 170 cpu = <&cpu5>; 171 }; 172 173 core2 { 174 cpu = <&cpu6>; 175 }; 176 177 core3 { 178 cpu = <&cpu7>; 179 }; 180 }; 181 }; 182 183 l2_0: l2-cache0 { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-size = <1048576>; 187 cache-line-size = <64>; 188 cache-sets = <1024>; 189 cache-unified; 190 }; 191 192 l2_1: l2-cache1 { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-size = <1048576>; 196 cache-line-size = <64>; 197 cache-sets = <1024>; 198 cache-unified; 199 }; 200 }; 201 202 clk26m: oscillator-26m { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <26000000>; 206 clock-output-names = "clk26m"; 207 }; 208 209 clk32k: oscillator-32k { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32000>; 213 clock-output-names = "clk32k"; 214 }; 215 216 system_clk: dummy13m { 217 compatible = "fixed-clock"; 218 clock-frequency = <13000000>; 219 #clock-cells = <0>; 220 }; 221 222 pmu { 223 compatible = "arm,cortex-a53-pmu"; 224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 225 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 226 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 227 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 228 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 229 }; 230 231 timer { 232 compatible = "arm,armv8-timer"; 233 interrupt-parent = <&gic>; 234 interrupts = <GIC_PPI 13 235 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 14 237 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 11 239 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 10 241 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 242 }; 243 244 soc { 245 #address-cells = <2>; 246 #size-cells = <2>; 247 compatible = "simple-bus"; 248 ranges; 249 250 topckgen: syscon@10000000 { 251 compatible = "mediatek,mt6795-topckgen", "syscon"; 252 reg = <0 0x10000000 0 0x1000>; 253 #clock-cells = <1>; 254 }; 255 256 infracfg: syscon@10001000 { 257 compatible = "mediatek,mt6795-infracfg", "syscon"; 258 reg = <0 0x10001000 0 0x1000>; 259 #clock-cells = <1>; 260 #reset-cells = <1>; 261 }; 262 263 pericfg: syscon@10003000 { 264 compatible = "mediatek,mt6795-pericfg", "syscon"; 265 reg = <0 0x10003000 0 0x1000>; 266 #clock-cells = <1>; 267 #reset-cells = <1>; 268 }; 269 270 scpsys: syscon@10006000 { 271 compatible = "syscon", "simple-mfd"; 272 reg = <0 0x10006000 0 0x1000>; 273 #power-domain-cells = <1>; 274 275 /* System Power Manager */ 276 spm: power-controller { 277 compatible = "mediatek,mt6795-power-controller"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 #power-domain-cells = <1>; 281 282 /* power domains of the SoC */ 283 power-domain@MT6795_POWER_DOMAIN_VDEC { 284 reg = <MT6795_POWER_DOMAIN_VDEC>; 285 clocks = <&topckgen CLK_TOP_MM_SEL>; 286 clock-names = "mm"; 287 #power-domain-cells = <0>; 288 }; 289 power-domain@MT6795_POWER_DOMAIN_VENC { 290 reg = <MT6795_POWER_DOMAIN_VENC>; 291 clocks = <&topckgen CLK_TOP_MM_SEL>, 292 <&topckgen CLK_TOP_VENC_SEL>; 293 clock-names = "mm", "venc"; 294 #power-domain-cells = <0>; 295 }; 296 power-domain@MT6795_POWER_DOMAIN_ISP { 297 reg = <MT6795_POWER_DOMAIN_ISP>; 298 clocks = <&topckgen CLK_TOP_MM_SEL>; 299 clock-names = "mm"; 300 #power-domain-cells = <0>; 301 }; 302 303 power-domain@MT6795_POWER_DOMAIN_MM { 304 reg = <MT6795_POWER_DOMAIN_MM>; 305 clocks = <&topckgen CLK_TOP_MM_SEL>; 306 clock-names = "mm"; 307 #power-domain-cells = <0>; 308 mediatek,infracfg = <&infracfg>; 309 }; 310 311 power-domain@MT6795_POWER_DOMAIN_MJC { 312 reg = <MT6795_POWER_DOMAIN_MJC>; 313 clocks = <&topckgen CLK_TOP_MM_SEL>, 314 <&topckgen CLK_TOP_MJC_SEL>; 315 clock-names = "mm", "mjc"; 316 #power-domain-cells = <0>; 317 }; 318 319 power-domain@MT6795_POWER_DOMAIN_AUDIO { 320 reg = <MT6795_POWER_DOMAIN_AUDIO>; 321 #power-domain-cells = <0>; 322 }; 323 324 mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC { 325 reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>; 326 clocks = <&clk26m>; 327 clock-names = "mfg"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 #power-domain-cells = <1>; 331 332 power-domain@MT6795_POWER_DOMAIN_MFG_2D { 333 reg = <MT6795_POWER_DOMAIN_MFG_2D>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 #power-domain-cells = <1>; 337 338 power-domain@MT6795_POWER_DOMAIN_MFG { 339 reg = <MT6795_POWER_DOMAIN_MFG>; 340 #power-domain-cells = <0>; 341 mediatek,infracfg = <&infracfg>; 342 }; 343 }; 344 }; 345 }; 346 }; 347 348 pio: pinctrl@10005000 { 349 compatible = "mediatek,mt6795-pinctrl"; 350 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; 351 reg-names = "base", "eint"; 352 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 gpio-ranges = <&pio 0 0 196>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 }; 360 361 watchdog: watchdog@10007000 { 362 compatible = "mediatek,mt6795-wdt"; 363 reg = <0 0x10007000 0 0x100>; 364 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 365 #reset-cells = <1>; 366 timeout-sec = <20>; 367 }; 368 369 timer: timer@10008000 { 370 compatible = "mediatek,mt6795-timer", 371 "mediatek,mt6577-timer"; 372 reg = <0 0x10008000 0 0x1000>; 373 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 374 clocks = <&system_clk>, <&clk32k>; 375 }; 376 377 pwrap: pwrap@1000d000 { 378 compatible = "mediatek,mt6795-pwrap"; 379 reg = <0 0x1000d000 0 0x1000>; 380 reg-names = "pwrap"; 381 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 382 resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>; 383 reset-names = "pwrap"; 384 clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>; 385 clock-names = "spi", "wrap"; 386 }; 387 388 sysirq: intpol-controller@10200620 { 389 compatible = "mediatek,mt6795-sysirq", 390 "mediatek,mt6577-sysirq"; 391 interrupt-controller; 392 #interrupt-cells = <3>; 393 interrupt-parent = <&gic>; 394 reg = <0 0x10200620 0 0x20>; 395 }; 396 397 systimer: timer@10200670 { 398 compatible = "mediatek,mt6795-systimer"; 399 reg = <0 0x10200670 0 0x10>; 400 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&system_clk>; 402 clock-names = "clk13m"; 403 }; 404 405 iommu: iommu@10205000 { 406 compatible = "mediatek,mt6795-m4u"; 407 reg = <0 0x10205000 0 0x1000>; 408 clocks = <&infracfg CLK_INFRA_M4U>; 409 clock-names = "bclk"; 410 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; 411 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; 412 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 413 #iommu-cells = <1>; 414 }; 415 416 apmixedsys: syscon@10209000 { 417 compatible = "mediatek,mt6795-apmixedsys", "syscon"; 418 reg = <0 0x10209000 0 0x1000>; 419 #clock-cells = <1>; 420 }; 421 422 fhctl: clock-controller@10209f00 { 423 compatible = "mediatek,mt6795-fhctl"; 424 reg = <0 0x10209f00 0 0x100>; 425 status = "disabled"; 426 }; 427 428 gce: mailbox@10212000 { 429 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce"; 430 reg = <0 0x10212000 0 0x1000>; 431 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 432 clocks = <&infracfg CLK_INFRA_GCE>; 433 clock-names = "gce"; 434 #mbox-cells = <2>; 435 }; 436 437 gic: interrupt-controller@10221000 { 438 compatible = "arm,gic-400"; 439 #interrupt-cells = <3>; 440 interrupt-parent = <&gic>; 441 interrupt-controller; 442 reg = <0 0x10221000 0 0x1000>, 443 <0 0x10222000 0 0x2000>, 444 <0 0x10224000 0 0x2000>, 445 <0 0x10226000 0 0x2000>; 446 interrupts = <GIC_PPI 9 447 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 448 }; 449 450 cci: cci@10390000 { 451 compatible = "arm,cci-400"; 452 #address-cells = <1>; 453 #size-cells = <1>; 454 reg = <0 0x10390000 0 0x1000>; 455 ranges = <0 0 0x10390000 0x10000>; 456 457 cci_control0: slave-if@1000 { 458 compatible = "arm,cci-400-ctrl-if"; 459 interface-type = "ace-lite"; 460 reg = <0x1000 0x1000>; 461 }; 462 463 cci_control1: slave-if@4000 { 464 compatible = "arm,cci-400-ctrl-if"; 465 interface-type = "ace"; 466 reg = <0x4000 0x1000>; 467 }; 468 469 cci_control2: slave-if@5000 { 470 compatible = "arm,cci-400-ctrl-if"; 471 interface-type = "ace"; 472 reg = <0x5000 0x1000>; 473 }; 474 475 pmu@9000 { 476 compatible = "arm,cci-400-pmu,r1"; 477 reg = <0x9000 0x5000>; 478 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 483 }; 484 }; 485 486 uart0: serial@11002000 { 487 compatible = "mediatek,mt6795-uart", 488 "mediatek,mt6577-uart"; 489 reg = <0 0x11002000 0 0x400>; 490 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 491 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 492 clock-names = "baud", "bus"; 493 dmas = <&apdma 0>, <&apdma 1>; 494 dma-names = "tx", "rx"; 495 status = "disabled"; 496 }; 497 498 uart1: serial@11003000 { 499 compatible = "mediatek,mt6795-uart", 500 "mediatek,mt6577-uart"; 501 reg = <0 0x11003000 0 0x400>; 502 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 503 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 504 clock-names = "baud", "bus"; 505 dmas = <&apdma 2>, <&apdma 3>; 506 dma-names = "tx", "rx"; 507 status = "disabled"; 508 }; 509 510 apdma: dma-controller@11000380 { 511 compatible = "mediatek,mt6795-uart-dma", 512 "mediatek,mt6577-uart-dma"; 513 reg = <0 0x11000380 0 0x60>, 514 <0 0x11000400 0 0x60>, 515 <0 0x11000480 0 0x60>, 516 <0 0x11000500 0 0x60>, 517 <0 0x11000580 0 0x60>, 518 <0 0x11000600 0 0x60>, 519 <0 0x11000680 0 0x60>, 520 <0 0x11000700 0 0x60>; 521 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 522 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 523 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 524 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 525 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 526 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 527 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 528 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 529 dma-requests = <8>; 530 clocks = <&pericfg CLK_PERI_AP_DMA>; 531 clock-names = "apdma"; 532 mediatek,dma-33bits; 533 #dma-cells = <1>; 534 }; 535 536 uart2: serial@11004000 { 537 compatible = "mediatek,mt6795-uart", 538 "mediatek,mt6577-uart"; 539 reg = <0 0x11004000 0 0x400>; 540 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 541 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 542 clock-names = "baud", "bus"; 543 dmas = <&apdma 4>, <&apdma 5>; 544 dma-names = "tx", "rx"; 545 status = "disabled"; 546 }; 547 548 uart3: serial@11005000 { 549 compatible = "mediatek,mt6795-uart", 550 "mediatek,mt6577-uart"; 551 reg = <0 0x11005000 0 0x400>; 552 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 553 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 554 clock-names = "baud", "bus"; 555 dmas = <&apdma 6>, <&apdma 7>; 556 dma-names = "tx", "rx"; 557 status = "disabled"; 558 }; 559 560 pwm2: pwm@11006000 { 561 compatible = "mediatek,mt6795-pwm"; 562 reg = <0 0x11006000 0 0x1000>; 563 #pwm-cells = <2>; 564 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 565 clocks = <&topckgen CLK_TOP_PWM_SEL>, 566 <&pericfg CLK_PERI_PWM>, 567 <&pericfg CLK_PERI_PWM1>, 568 <&pericfg CLK_PERI_PWM2>, 569 <&pericfg CLK_PERI_PWM3>, 570 <&pericfg CLK_PERI_PWM4>, 571 <&pericfg CLK_PERI_PWM5>, 572 <&pericfg CLK_PERI_PWM6>, 573 <&pericfg CLK_PERI_PWM7>; 574 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 575 "pwm4", "pwm5", "pwm6", "pwm7"; 576 status = "disabled"; 577 }; 578 579 i2c0: i2c@11007000 { 580 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 581 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; 582 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 583 clock-div = <16>; 584 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; 585 clock-names = "main", "dma"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 i2c1: i2c@11008000 { 592 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 593 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>; 594 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 595 clock-div = <16>; 596 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; 597 clock-names = "main", "dma"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 i2c2: i2c@11009000 { 604 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 605 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>; 606 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 607 clock-div = <16>; 608 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; 609 clock-names = "main", "dma"; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 status = "disabled"; 613 }; 614 615 i2c3: i2c@11010000 { 616 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 617 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>; 618 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 619 clock-div = <16>; 620 clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>; 621 clock-names = "main", "dma"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 status = "disabled"; 625 }; 626 627 i2c4: i2c@11011000 { 628 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 629 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>; 630 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 631 clock-div = <16>; 632 clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>; 633 clock-names = "main", "dma"; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 status = "disabled"; 637 }; 638 639 mmc0: mmc@11230000 { 640 compatible = "mediatek,mt6795-mmc"; 641 reg = <0 0x11230000 0 0x1000>; 642 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 643 clocks = <&pericfg CLK_PERI_MSDC30_0>, 644 <&topckgen CLK_TOP_MSDC50_0_H_SEL>, 645 <&topckgen CLK_TOP_MSDC50_0_SEL>; 646 clock-names = "source", "hclk", "source_cg"; 647 status = "disabled"; 648 }; 649 650 mmc1: mmc@11240000 { 651 compatible = "mediatek,mt6795-mmc"; 652 reg = <0 0x11240000 0 0x1000>; 653 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 654 clocks = <&pericfg CLK_PERI_MSDC30_1>, 655 <&topckgen CLK_TOP_AXI_SEL>; 656 clock-names = "source", "hclk"; 657 status = "disabled"; 658 }; 659 660 mmc2: mmc@11250000 { 661 compatible = "mediatek,mt6795-mmc"; 662 reg = <0 0x11250000 0 0x1000>; 663 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 664 clocks = <&pericfg CLK_PERI_MSDC30_2>, 665 <&topckgen CLK_TOP_AXI_SEL>; 666 clock-names = "source", "hclk"; 667 status = "disabled"; 668 }; 669 670 mmc3: mmc@11260000 { 671 compatible = "mediatek,mt6795-mmc"; 672 reg = <0 0x11260000 0 0x1000>; 673 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 674 clocks = <&pericfg CLK_PERI_MSDC30_3>, 675 <&topckgen CLK_TOP_AXI_SEL>; 676 clock-names = "source", "hclk"; 677 status = "disabled"; 678 }; 679 680 mmsys: syscon@14000000 { 681 compatible = "mediatek,mt6795-mmsys", "syscon"; 682 reg = <0 0x14000000 0 0x1000>; 683 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 684 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 685 assigned-clock-rates = <400000000>; 686 #clock-cells = <1>; 687 #reset-cells = <1>; 688 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 689 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 690 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 691 }; 692 693 larb0: larb@14021000 { 694 compatible = "mediatek,mt6795-smi-larb"; 695 reg = <0 0x14021000 0 0x1000>; 696 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>; 697 clock-names = "apb", "smi"; 698 mediatek,smi = <&smi_common>; 699 mediatek,larb-id = <0>; 700 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 701 }; 702 703 smi_common: smi@14022000 { 704 compatible = "mediatek,mt6795-smi-common"; 705 reg = <0 0x14022000 0 0x1000>; 706 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 707 clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>; 708 clock-names = "apb", "smi"; 709 }; 710 711 larb2: larb@15001000 { 712 compatible = "mediatek,mt6795-smi-larb"; 713 reg = <0 0x15001000 0 0x1000>; 714 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>; 715 clock-names = "apb", "smi"; 716 mediatek,smi = <&smi_common>; 717 mediatek,larb-id = <2>; 718 power-domains = <&spm MT6795_POWER_DOMAIN_ISP>; 719 }; 720 721 vdecsys: clock-controller@16000000 { 722 compatible = "mediatek,mt6795-vdecsys"; 723 reg = <0 0x16000000 0 0x1000>; 724 #clock-cells = <1>; 725 }; 726 727 larb1: larb@16010000 { 728 compatible = "mediatek,mt6795-smi-larb"; 729 reg = <0 0x16010000 0 0x1000>; 730 mediatek,smi = <&smi_common>; 731 mediatek,larb-id = <1>; 732 clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; 733 clock-names = "apb", "smi"; 734 power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>; 735 }; 736 737 vencsys: clock-controller@18000000 { 738 compatible = "mediatek,mt6795-vencsys"; 739 reg = <0 0x18000000 0 0x1000>; 740 #clock-cells = <1>; 741 }; 742 743 larb3: larb@18001000 { 744 compatible = "mediatek,mt6795-smi-larb"; 745 reg = <0 0x18001000 0 0x1000>; 746 clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>; 747 clock-names = "apb", "smi"; 748 mediatek,smi = <&smi_common>; 749 mediatek,larb-id = <3>; 750 power-domains = <&spm MT6795_POWER_DOMAIN_VENC>; 751 }; 752 }; 753}; 754