1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2016 MediaTek Inc.
4 */
5
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/regulator/dlg,da9211-regulator.h>
9#include <dt-bindings/gpio/gpio.h>
10#include "mt8173.dtsi"
11
12/ {
13	aliases {
14		mmc0 = &mmc0;
15		mmc1 = &mmc1;
16		mmc2 = &mmc3;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0 0x40000000 0 0x80000000>;
22	};
23
24	backlight: backlight {
25		compatible = "pwm-backlight";
26		pwms = <&pwm0 0 1000000>;
27		power-supply = <&bl_fixed_reg>;
28		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
29
30		pinctrl-names = "default";
31		pinctrl-0 = <&panel_backlight_en_pins>;
32		status = "okay";
33	};
34
35	bl_fixed_reg: fixedregulator2 {
36		compatible = "regulator-fixed";
37		regulator-name = "bl_fixed";
38		regulator-min-microvolt = <1800000>;
39		regulator-max-microvolt = <1800000>;
40		startup-delay-us = <1000>;
41		enable-active-high;
42		gpio = <&pio 32 GPIO_ACTIVE_HIGH>;
43		pinctrl-names = "default";
44		pinctrl-0 = <&bl_fixed_pins>;
45	};
46
47	chosen {
48		stdout-path = "serial0:115200n8";
49	};
50
51	gpio_keys: gpio-keys {
52		compatible = "gpio-keys";
53		pinctrl-names = "default";
54		pinctrl-0 = <&gpio_keys_pins>;
55
56		switch-lid {
57			label = "Lid";
58			gpios = <&pio 69 GPIO_ACTIVE_LOW>;
59			linux,code = <SW_LID>;
60			linux,input-type = <EV_SW>;
61			wakeup-source;
62		};
63
64		switch-power {
65			label = "Power";
66			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
67			linux,code = <KEY_POWER>;
68			debounce-interval = <30>;
69			wakeup-source;
70		};
71
72		switch-tablet-mode {
73			label = "Tablet_mode";
74			gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
75			linux,code = <SW_TABLET_MODE>;
76			linux,input-type = <EV_SW>;
77			wakeup-source;
78		};
79
80		switch-volume-down {
81			label = "Volume_down";
82			gpios = <&pio 123 GPIO_ACTIVE_LOW>;
83			linux,code = <KEY_VOLUMEDOWN>;
84		};
85
86		switch-volume-up {
87			label = "Volume_up";
88			gpios = <&pio 124 GPIO_ACTIVE_LOW>;
89			linux,code = <KEY_VOLUMEUP>;
90		};
91	};
92
93	panel_fixed_3v3: regulator1 {
94		compatible = "regulator-fixed";
95		regulator-name = "PANEL_3V3";
96		regulator-min-microvolt = <3300000>;
97		regulator-max-microvolt = <3300000>;
98		enable-active-high;
99		regulator-boot-on;
100		off-on-delay-us = <500000>;
101		gpio = <&pio 41 GPIO_ACTIVE_HIGH>;
102		pinctrl-names = "default";
103		pinctrl-0 = <&panel_fixed_pins>;
104	};
105
106	ps8640_fixed_1v2: regulator2 {
107		compatible = "regulator-fixed";
108		regulator-name = "PS8640_1V2";
109		regulator-min-microvolt = <1200000>;
110		regulator-max-microvolt = <1200000>;
111		regulator-enable-ramp-delay = <2000>;
112		enable-active-high;
113		regulator-boot-on;
114		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
115		pinctrl-names = "default";
116		pinctrl-0 = <&ps8640_fixed_pins>;
117	};
118
119	sdio_fixed_3v3: fixedregulator0 {
120		compatible = "regulator-fixed";
121		regulator-name = "3V3";
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124		gpio = <&pio 85 GPIO_ACTIVE_HIGH>;
125		pinctrl-names = "default";
126		pinctrl-0 = <&sdio_fixed_3v3_pins>;
127	};
128
129	sound: sound {
130		compatible = "mediatek,mt8173-rt5650";
131		mediatek,audio-codec = <&rt5650 &hdmi0>;
132		mediatek,platform = <&afe>;
133		pinctrl-names = "default";
134		pinctrl-0 = <&aud_i2s2>;
135
136		mediatek,mclk = <1>;
137		codec-capture {
138			sound-dai = <&rt5650 1>;
139		};
140	};
141
142	hdmicon: connector {
143		compatible = "hdmi-connector";
144		label = "hdmi";
145		type = "a";
146		ddc-i2c-bus = <&hdmiddc0>;
147
148		port {
149			hdmi_connector_in: endpoint {
150				remote-endpoint = <&hdmi0_out>;
151			};
152		};
153	};
154
155	watchdog {
156		compatible = "arm,smc-wdt";
157	};
158};
159
160/*
161 * Disable the original MMIO watch dog and switch to the SMC watchdog, which
162 * operates on the same MMIO.
163 */
164&watchdog {
165	status = "disabled";
166};
167
168&mfg_async {
169	domain-supply = <&da9211_vgpu_reg>;
170};
171
172&cec {
173	status = "okay";
174};
175
176&cpu0 {
177	proc-supply = <&mt6397_vpca15_reg>;
178};
179
180&cpu1 {
181	proc-supply = <&mt6397_vpca15_reg>;
182};
183
184&cpu2 {
185	proc-supply = <&da9211_vcpu_reg>;
186	sram-supply = <&mt6397_vsramca7_reg>;
187};
188
189&cpu3 {
190	proc-supply = <&da9211_vcpu_reg>;
191	sram-supply = <&mt6397_vsramca7_reg>;
192};
193
194&cpu_thermal {
195	sustainable-power = <4500>; /* milliwatts */
196	trips {
197		threshold: trip-point0 {
198			temperature = <60000>;
199		};
200
201		target: trip-point1 {
202			temperature = <65000>;
203		};
204	};
205};
206
207&dsi0 {
208	status = "okay";
209	ports {
210		port {
211			dsi0_out: endpoint {
212				remote-endpoint = <&ps8640_in>;
213			};
214		};
215	};
216};
217
218&dpi0 {
219	status = "okay";
220};
221
222&hdmi0 {
223	status = "okay";
224	ports {
225		port@1 {
226			reg = <1>;
227
228			hdmi0_out: endpoint {
229				remote-endpoint = <&hdmi_connector_in>;
230			};
231		};
232	};
233};
234
235&hdmi_phy {
236	status = "okay";
237	mediatek,ibias = <0xc>;
238};
239
240&i2c0 {
241	status = "okay";
242
243	rt5650: audio-codec@1a {
244		compatible = "realtek,rt5650";
245		reg = <0x1a>;
246		avdd-supply = <&mt6397_vgp1_reg>;
247		cpvdd-supply = <&mt6397_vcama_reg>;
248		interrupt-parent = <&pio>;
249		interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
250		pinctrl-names = "default";
251		pinctrl-0 = <&rt5650_irq>;
252		#sound-dai-cells = <1>;
253		realtek,dmic1-data-pin = <2>;
254		realtek,jd-mode = <2>;
255	};
256
257	ps8640: edp-bridge@8 {
258		compatible = "parade,ps8640";
259		reg = <0x8>;
260		powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>;
261		reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
262		pinctrl-names = "default";
263		pinctrl-0 = <&ps8640_pins>;
264		vdd12-supply = <&ps8640_fixed_1v2>;
265		vdd33-supply = <&mt6397_vgp2_reg>;
266
267		ports {
268			#address-cells = <1>;
269			#size-cells = <0>;
270
271			port@0 {
272				reg = <0>;
273
274				ps8640_in: endpoint {
275					remote-endpoint = <&dsi0_out>;
276				};
277			};
278
279			port@1 {
280				reg = <1>;
281
282				ps8640_out: endpoint {
283					remote-endpoint = <&panel_in>;
284				};
285			};
286		};
287
288		aux-bus {
289			panel: panel {
290				compatible = "edp-panel";
291				power-supply = <&panel_fixed_3v3>;
292				backlight = <&backlight>;
293
294				port {
295					panel_in: endpoint {
296						remote-endpoint = <&ps8640_out>;
297					};
298				};
299			};
300		};
301	};
302};
303
304&i2c1 {
305	clock-frequency = <1500000>;
306	status = "okay";
307
308	da9211: da9211@68 {
309		compatible = "dlg,da9211";
310		reg = <0x68>;
311		interrupt-parent = <&pio>;
312		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
313
314		regulators {
315			da9211_vcpu_reg: BUCKA {
316				regulator-name = "VBUCKA";
317				regulator-min-microvolt = < 700000>;
318				regulator-max-microvolt = <1310000>;
319				regulator-min-microamp = <2000000>;
320				regulator-max-microamp = <4400000>;
321				regulator-ramp-delay = <10000>;
322				regulator-always-on;
323				regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
324							   DA9211_BUCK_MODE_AUTO>;
325			};
326
327			da9211_vgpu_reg: BUCKB {
328				regulator-name = "VBUCKB";
329				regulator-min-microvolt = < 700000>;
330				regulator-max-microvolt = <1310000>;
331				regulator-min-microamp = <2000000>;
332				regulator-max-microamp = <3000000>;
333				regulator-ramp-delay = <10000>;
334			};
335		};
336	};
337};
338
339&i2c2 {
340	status = "okay";
341
342	tpm: tpm@20 {
343		compatible = "infineon,slb9645tt";
344		reg = <0x20>;
345		powered-while-suspended;
346	};
347};
348
349&i2c3 {
350	clock-frequency = <400000>;
351	status = "okay";
352
353	touchscreen: touchscreen@10 {
354		compatible = "elan,ekth3500";
355		reg = <0x10>;
356		interrupt-parent = <&pio>;
357		interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
358	};
359};
360
361&i2c4 {
362	clock-frequency = <400000>;
363	status = "okay";
364	pinctrl-names = "default";
365	pinctrl-0 = <&trackpad_irq>;
366
367	trackpad: trackpad@15 {
368		compatible = "elan,ekth3000";
369		interrupt-parent = <&pio>;
370		interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
371		reg = <0x15>;
372		vcc-supply = <&mt6397_vgp6_reg>;
373		wakeup-source;
374	};
375};
376
377&mipi_tx0 {
378	status = "okay";
379};
380
381&mmc0 {
382	status = "okay";
383	pinctrl-names = "default", "state_uhs";
384	pinctrl-0 = <&mmc0_pins_default>;
385	pinctrl-1 = <&mmc0_pins_uhs>;
386	bus-width = <8>;
387	max-frequency = <200000000>;
388	cap-mmc-highspeed;
389	mmc-hs200-1_8v;
390	mmc-hs400-1_8v;
391	cap-mmc-hw-reset;
392	hs400-ds-delay = <0x14015>;
393	mediatek,hs200-cmd-int-delay = <30>;
394	mediatek,hs400-cmd-int-delay = <14>;
395	mediatek,hs400-cmd-resp-sel-rising;
396	vmmc-supply = <&mt6397_vemc_3v3_reg>;
397	vqmmc-supply = <&mt6397_vio18_reg>;
398	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
399	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
400	non-removable;
401};
402
403&mmc1 {
404	status = "okay";
405	pinctrl-names = "default", "state_uhs";
406	pinctrl-0 = <&mmc1_pins_default>;
407	pinctrl-1 = <&mmc1_pins_uhs>;
408	bus-width = <4>;
409	max-frequency = <200000000>;
410	cap-sd-highspeed;
411	sd-uhs-sdr50;
412	sd-uhs-sdr104;
413	cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
414	vmmc-supply = <&mt6397_vmch_reg>;
415	vqmmc-supply = <&mt6397_vmc_reg>;
416};
417
418&mmc3 {
419	status = "okay";
420	pinctrl-names = "default", "state_uhs";
421	pinctrl-0 = <&mmc3_pins_default>;
422	pinctrl-1 = <&mmc3_pins_uhs>;
423	bus-width = <4>;
424	max-frequency = <200000000>;
425	cap-sd-highspeed;
426	sd-uhs-sdr50;
427	sd-uhs-sdr104;
428	keep-power-in-suspend;
429	wakeup-source;
430	cap-sdio-irq;
431	vmmc-supply = <&sdio_fixed_3v3>;
432	vqmmc-supply = <&mt6397_vgp3_reg>;
433	non-removable;
434	cap-power-off-card;
435
436	#address-cells = <1>;
437	#size-cells = <0>;
438
439	btmrvl: btmrvl@2 {
440		compatible = "marvell,sd8897-bt";
441		reg = <2>;
442		interrupt-parent = <&pio>;
443		interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
444		marvell,wakeup-pin = /bits/ 16 <0x0d>;
445		marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
446	};
447
448	mwifiex: mwifiex@1 {
449		compatible = "marvell,sd8897";
450		reg = <1>;
451		interrupt-parent = <&pio>;
452		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
453		marvell,wakeup-pin = <3>;
454	};
455};
456
457&nor_flash {
458	status = "okay";
459	pinctrl-names = "default";
460	pinctrl-0 = <&nor_gpio1_pins>;
461
462	flash@0 {
463		compatible = "jedec,spi-nor";
464		reg = <0>;
465		spi-max-frequency = <50000000>;
466	};
467};
468
469&pio {
470	gpio-line-names = "EC_INT_1V8",
471			  "SD_CD_L",
472			  "ALC5514_IRQ",
473			  "ALC5650_IRQ",
474			  /*
475			   * AP_FLASH_WP_L is crossystem ABI. Schematics
476			   * call it SFWP_B.
477			   */
478			  "AP_FLASH_WP_L",
479			  "SFIN",
480			  "SFCS0",
481			  "SFHOLD",
482			  "SFOUT",
483			  "SFCK",
484			  "WRAP_EVENT_S_EINT10",
485			  "PMU_INT",
486			  "I2S2_WS_ALC5650",
487			  "I2S2_BCK_ALC5650",
488			  "PWR_BTN_1V8",
489			  "DA9212_IRQ",
490			  "IDDIG",
491			  "WATCHDOG",
492			  "CEC",
493			  "HDMISCK",
494			  "HDMISD",
495			  "HTPLG",
496			  "MSDC3_DAT0",
497			  "MSDC3_DAT1",
498			  "MSDC3_DAT2",
499			  "MSDC3_DAT3",
500			  "MSDC3_CLK",
501			  "MSDC3_CMD",
502			  "USB_C0_OC_FLAGB",
503			  "USBA_OC1_L",
504			  "PS8640_1V2_ENABLE",
505			  "THERM_ALERT_N",
506			  "PANEL_LCD_POWER_EN",
507			  "ANX7688_CHIP_PD_C",
508			  "EC_IN_RW_1V8",
509			  "ANX7688_1V_EN_C",
510			  "USB_DP_HPD_C",
511			  "TPM_DAVINT_N",
512			  "MARVELL8897_IRQ",
513			  "EN_USB_A0_PWR",
514			  "USBA_A0_OC_L",
515			  "EN_PP3300_DX_EDP",
516			  "",
517			  "SOC_I2C2_1V8_SDA_400K",
518			  "SOC_I2C2_1V8_SCL_400K",
519			  "SOC_I2C0_1V8_SDA_400K",
520			  "SOC_I2C0_1V8_SCL_400K",
521			  "EMMC_ID1",
522			  "EMMC_ID0",
523			  "MEM_CONFIG3",
524			  "EMMC_ID2",
525			  "MEM_CONFIG1",
526			  "MEM_CONFIG2",
527			  "BRD_ID2",
528			  "MEM_CONFIG0",
529			  "BRD_ID0",
530			  "BRD_ID1",
531			  "EMMC_DAT0",
532			  "EMMC_DAT1",
533			  "EMMC_DAT2",
534			  "EMMC_DAT3",
535			  "EMMC_DAT4",
536			  "EMMC_DAT5",
537			  "EMMC_DAT6",
538			  "EMMC_DAT7",
539			  "EMMC_CLK",
540			  "EMMC_CMD",
541			  "EMMC_RCLK",
542			  "PLT_RST_L",
543			  "LID_OPEN_1V8_L",
544			  "AUDIO_SPI_MISO_R",
545			  "",
546			  "AC_OK_1V8",
547			  "SD_DATA0",
548			  "SD_DATA1",
549			  "SD_DATA2",
550			  "SD_DATA3",
551			  "SD_CLK",
552			  "SD_CMD",
553			  "PWRAP_SPI0_MI",
554			  "PWRAP_SPI0_MO",
555			  "PWRAP_SPI0_CK",
556			  "PWRAP_SPI0_CSN",
557			  "",
558			  "",
559			  "WIFI_PDN",
560			  "RTC32K_1V8",
561			  "DISP_PWM0",
562			  "TOUCHSCREEN_INT_L",
563			  "",
564			  "SRCLKENA0",
565			  "SRCLKENA1",
566			  "PS8640_MODE_CONF",
567			  "TOUCHSCREEN_RESET_R",
568			  "PLATFORM_PROCHOT_L",
569			  "PANEL_POWER_EN",
570			  "REC_MODE_L",
571			  "EC_FW_UPDATE_L",
572			  "ACCEL2_INT_L",
573			  "HDMI_DP_INT",
574			  "ACCELGYRO3_INT_L",
575			  "ACCELGYRO4_INT_L",
576			  "SPI_EC_CLK",
577			  "SPI_EC_MI",
578			  "SPI_EC_MO",
579			  "SPI_EC_CSN",
580			  "SOC_I2C3_1V8_SDA_400K",
581			  "SOC_I2C3_1V8_SCL_400K",
582			  "",
583			  "",
584			  "",
585			  "",
586			  "",
587			  "",
588			  "",
589			  "PS8640_SYSRSTN_1V8",
590			  "APIN_MAX98090_DOUT2",
591			  "TP_INT_1V8_L_R",
592			  "RST_USB_HUB_R",
593			  "BT_WAKE_L",
594			  "ACCEL1_INT_L",
595			  "TABLET_MODE_L",
596			  "",
597			  "V_UP_IN_L_R",
598			  "V_DOWN_IN_L_R",
599			  "SOC_I2C1_1V8_SDA_1M",
600			  "SOC_I2C1_1V8_SCL_1M",
601			  "PS8640_PDN_1V8",
602			  "MAX98090_LRCLK",
603			  "MAX98090_BCLK",
604			  "MAX98090_MCLK",
605			  "APOUT_MAX98090_DIN",
606			  "APIN_MAX98090_DOUT",
607			  "SOC_I2C4_1V8_SDA_400K",
608			  "SOC_I2C4_1V8_SCL_400K";
609
610	aud_i2s2: aud_i2s2 {
611		pins1 {
612			pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>,
613				 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>,
614				 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>,
615				 <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>,
616				 <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>,
617				 <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>,
618				 <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>;
619			bias-pull-down;
620		};
621	};
622
623	bl_fixed_pins: bl_fixed_pins {
624		pins1 {
625			pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>;
626			output-low;
627		};
628	};
629
630	bt_wake_pins: bt_wake_pins {
631		pins1 {
632			pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>;
633			bias-pull-up;
634		};
635	};
636
637	disp_pwm0_pins: disp_pwm0_pins {
638		pins1 {
639			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
640			output-low;
641		};
642	};
643
644	gpio_keys_pins: gpio_keys_pins {
645		volume_pins {
646			pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>,
647				 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>;
648			bias-pull-up;
649		};
650
651		tablet_mode_pins {
652			pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>;
653			bias-pull-up;
654		};
655	};
656
657	hdmi_mux_pins: hdmi_mux_pins {
658		pins1 {
659			pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>;
660		};
661	};
662
663	i2c1_pins_a: i2c1 {
664		da9211_pins {
665			pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
666			bias-pull-up;
667		};
668	};
669
670	mmc0_pins_default: mmc0default {
671		pins_cmd_dat {
672			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
673				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
674				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
675				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
676				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
677				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
678				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
679				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
680				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
681			bias-pull-up;
682		};
683
684		pins_clk {
685			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
686			bias-pull-down;
687		};
688
689		pins_rst {
690			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
691			bias-pull-up;
692		};
693	};
694
695	mmc1_pins_default: mmc1default {
696		pins_cmd_dat {
697			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
698				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
699				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
700				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
701				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
702			input-enable;
703			drive-strength = <MTK_DRIVE_4mA>;
704			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
705		};
706
707		pins_clk {
708			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
709			bias-pull-down;
710			drive-strength = <MTK_DRIVE_4mA>;
711		};
712
713		pins_insert {
714			pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>;
715			bias-pull-up;
716		};
717	};
718
719	mmc3_pins_default: mmc3default {
720		pins_dat {
721			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
722				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
723				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
724				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
725			input-enable;
726			drive-strength = <MTK_DRIVE_8mA>;
727			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
728		};
729
730		pins_cmd {
731			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
732			input-enable;
733			drive-strength = <MTK_DRIVE_8mA>;
734			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
735		};
736
737		pins_clk {
738			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
739			bias-pull-down;
740			drive-strength = <MTK_DRIVE_8mA>;
741		};
742	};
743
744	mmc0_pins_uhs: mmc0 {
745		pins_cmd_dat {
746			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
747				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
748				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
749				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
750				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
751				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
752				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
753				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
754				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
755			input-enable;
756			drive-strength = <MTK_DRIVE_6mA>;
757			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
758		};
759
760		pins_clk {
761			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
762			drive-strength = <MTK_DRIVE_6mA>;
763			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
764		};
765
766		pins_ds {
767			pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
768			drive-strength = <MTK_DRIVE_10mA>;
769			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
770		};
771
772		pins_rst {
773			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
774			bias-pull-up;
775		};
776	};
777
778	mmc1_pins_uhs: mmc1 {
779		pins_cmd_dat {
780			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
781				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
782				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
783				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
784				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
785			input-enable;
786			drive-strength = <MTK_DRIVE_6mA>;
787			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
788		};
789
790		pins_clk {
791			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
792			drive-strength = <MTK_DRIVE_8mA>;
793			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
794		};
795	};
796
797	mmc3_pins_uhs: mmc3 {
798		pins_dat {
799			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
800				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
801				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
802				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
803			input-enable;
804			drive-strength = <MTK_DRIVE_8mA>;
805			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
806		};
807
808		pins_cmd {
809			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
810			input-enable;
811			drive-strength = <MTK_DRIVE_8mA>;
812			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
813		};
814
815		pins_clk {
816			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
817			drive-strength = <MTK_DRIVE_8mA>;
818			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
819		};
820	};
821
822	nor_gpio1_pins: nor {
823		pins1 {
824			pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>,
825				 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>,
826				 <MT8173_PIN_8_EINT8__FUNC_SFIN>;
827			input-enable;
828			drive-strength = <MTK_DRIVE_4mA>;
829			bias-pull-up;
830		};
831
832		pins2 {
833			pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>;
834			drive-strength = <MTK_DRIVE_4mA>;
835			bias-pull-up;
836		};
837
838		pins_clk {
839			pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>;
840			input-enable;
841			drive-strength = <MTK_DRIVE_4mA>;
842			bias-pull-up;
843		};
844	};
845
846	panel_backlight_en_pins: panel_backlight_en_pins {
847		pins1 {
848			pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>;
849		};
850	};
851
852	panel_fixed_pins: panel_fixed_pins {
853		pins1 {
854			pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
855		};
856	};
857
858	ps8640_pins: ps8640_pins {
859		pins1 {
860			pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>,
861				 <MT8173_PIN_115_URTS0__FUNC_GPIO115>,
862				 <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>;
863		};
864	};
865
866	ps8640_fixed_pins: ps8640_fixed_pins {
867		pins1 {
868			pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>;
869		};
870	};
871
872	rt5650_irq: rt5650_irq {
873		pins1 {
874			pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>;
875			bias-pull-down;
876		};
877	};
878
879	sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {
880		pins1 {
881			pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>;
882			output-low;
883		};
884	};
885
886	spi_pins_a: spi1 {
887		pins1 {
888			pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>;
889			bias-pull-up;
890		};
891
892		pins_spi {
893			pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>,
894				 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>,
895				 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>,
896				 <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>;
897			bias-disable;
898		};
899	};
900
901	trackpad_irq: trackpad_irq {
902		pins1 {
903			pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>;
904			input-enable;
905			bias-pull-up;
906		};
907	};
908
909	usb_pins: usb {
910		pins1 {
911			pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>;
912			output-high;
913			bias-disable;
914		};
915	};
916
917	wifi_wake_pins: wifi_wake_pins {
918		pins1 {
919			pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>;
920			bias-pull-up;
921		};
922	};
923};
924
925&pwm0 {
926	pinctrl-names = "default";
927	pinctrl-0 = <&disp_pwm0_pins>;
928	status = "okay";
929};
930
931&pwrap {
932	pmic: pmic {
933		compatible = "mediatek,mt6397";
934		#address-cells = <1>;
935		#size-cells = <1>;
936		interrupt-parent = <&pio>;
937		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
938		interrupt-controller;
939		#interrupt-cells = <2>;
940
941		clock: mt6397clock {
942			compatible = "mediatek,mt6397-clk";
943			#clock-cells = <1>;
944		};
945
946		pio6397: pinctrl {
947			compatible = "mediatek,mt6397-pinctrl";
948			gpio-controller;
949			#gpio-cells = <2>;
950		};
951
952		regulator: mt6397regulator {
953			compatible = "mediatek,mt6397-regulator";
954
955			mt6397_vpca15_reg: buck_vpca15 {
956				regulator-compatible = "buck_vpca15";
957				regulator-name = "vpca15";
958				regulator-min-microvolt = < 700000>;
959				regulator-max-microvolt = <1350000>;
960				regulator-ramp-delay = <12500>;
961				regulator-always-on;
962				regulator-allowed-modes = <0 1>;
963			};
964
965			mt6397_vpca7_reg: buck_vpca7 {
966				regulator-compatible = "buck_vpca7";
967				regulator-name = "vpca7";
968				regulator-min-microvolt = < 700000>;
969				regulator-max-microvolt = <1350000>;
970				regulator-ramp-delay = <12500>;
971				regulator-enable-ramp-delay = <115>;
972				regulator-always-on;
973			};
974
975			mt6397_vsramca15_reg: buck_vsramca15 {
976				regulator-compatible = "buck_vsramca15";
977				regulator-name = "vsramca15";
978				regulator-min-microvolt = < 700000>;
979				regulator-max-microvolt = <1350000>;
980				regulator-ramp-delay = <12500>;
981				regulator-always-on;
982			};
983
984			mt6397_vsramca7_reg: buck_vsramca7 {
985				regulator-compatible = "buck_vsramca7";
986				regulator-name = "vsramca7";
987				regulator-min-microvolt = < 700000>;
988				regulator-max-microvolt = <1350000>;
989				regulator-ramp-delay = <12500>;
990				regulator-always-on;
991			};
992
993			mt6397_vcore_reg: buck_vcore {
994				regulator-compatible = "buck_vcore";
995				regulator-name = "vcore";
996				regulator-min-microvolt = < 700000>;
997				regulator-max-microvolt = <1350000>;
998				regulator-ramp-delay = <12500>;
999				regulator-always-on;
1000			};
1001
1002			mt6397_vgpu_reg: buck_vgpu {
1003				regulator-compatible = "buck_vgpu";
1004				regulator-name = "vgpu";
1005				regulator-min-microvolt = < 700000>;
1006				regulator-max-microvolt = <1350000>;
1007				regulator-ramp-delay = <12500>;
1008				regulator-enable-ramp-delay = <115>;
1009			};
1010
1011			mt6397_vdrm_reg: buck_vdrm {
1012				regulator-compatible = "buck_vdrm";
1013				regulator-name = "vdrm";
1014				regulator-min-microvolt = <1200000>;
1015				regulator-max-microvolt = <1400000>;
1016				regulator-ramp-delay = <12500>;
1017				regulator-always-on;
1018			};
1019
1020			mt6397_vio18_reg: buck_vio18 {
1021				regulator-compatible = "buck_vio18";
1022				regulator-name = "vio18";
1023				regulator-min-microvolt = <1620000>;
1024				regulator-max-microvolt = <1980000>;
1025				regulator-ramp-delay = <12500>;
1026				regulator-always-on;
1027			};
1028
1029			mt6397_vtcxo_reg: ldo_vtcxo {
1030				regulator-compatible = "ldo_vtcxo";
1031				regulator-name = "vtcxo";
1032				regulator-always-on;
1033			};
1034
1035			mt6397_va28_reg: ldo_va28 {
1036				regulator-compatible = "ldo_va28";
1037				regulator-name = "va28";
1038			};
1039
1040			mt6397_vcama_reg: ldo_vcama {
1041				regulator-compatible = "ldo_vcama";
1042				regulator-name = "vcama";
1043				regulator-min-microvolt = <1800000>;
1044				regulator-max-microvolt = <1800000>;
1045				regulator-enable-ramp-delay = <218>;
1046			};
1047
1048			mt6397_vio28_reg: ldo_vio28 {
1049				regulator-compatible = "ldo_vio28";
1050				regulator-name = "vio28";
1051				regulator-always-on;
1052			};
1053
1054			mt6397_vusb_reg: ldo_vusb {
1055				regulator-compatible = "ldo_vusb";
1056				regulator-name = "vusb";
1057			};
1058
1059			mt6397_vmc_reg: ldo_vmc {
1060				regulator-compatible = "ldo_vmc";
1061				regulator-name = "vmc";
1062				regulator-min-microvolt = <1800000>;
1063				regulator-max-microvolt = <3300000>;
1064				regulator-enable-ramp-delay = <218>;
1065			};
1066
1067			mt6397_vmch_reg: ldo_vmch {
1068				regulator-compatible = "ldo_vmch";
1069				regulator-name = "vmch";
1070				regulator-min-microvolt = <3000000>;
1071				regulator-max-microvolt = <3300000>;
1072				regulator-enable-ramp-delay = <218>;
1073			};
1074
1075			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
1076				regulator-compatible = "ldo_vemc3v3";
1077				regulator-name = "vemc_3v3";
1078				regulator-min-microvolt = <3000000>;
1079				regulator-max-microvolt = <3300000>;
1080				regulator-enable-ramp-delay = <218>;
1081			};
1082
1083			mt6397_vgp1_reg: ldo_vgp1 {
1084				regulator-compatible = "ldo_vgp1";
1085				regulator-name = "vcamd";
1086				regulator-min-microvolt = <1800000>;
1087				regulator-max-microvolt = <1800000>;
1088				regulator-enable-ramp-delay = <240>;
1089			};
1090
1091			mt6397_vgp2_reg: ldo_vgp2 {
1092				regulator-compatible = "ldo_vgp2";
1093				regulator-name = "vcamio";
1094				regulator-min-microvolt = <3300000>;
1095				regulator-max-microvolt = <3300000>;
1096				regulator-enable-ramp-delay = <218>;
1097			};
1098
1099			mt6397_vgp3_reg: ldo_vgp3 {
1100				regulator-compatible = "ldo_vgp3";
1101				regulator-name = "vcamaf";
1102				regulator-min-microvolt = <1800000>;
1103				regulator-max-microvolt = <1800000>;
1104				regulator-enable-ramp-delay = <218>;
1105			};
1106
1107			mt6397_vgp4_reg: ldo_vgp4 {
1108				regulator-compatible = "ldo_vgp4";
1109				regulator-name = "vgp4";
1110				regulator-min-microvolt = <1200000>;
1111				regulator-max-microvolt = <3300000>;
1112				regulator-enable-ramp-delay = <218>;
1113			};
1114
1115			mt6397_vgp5_reg: ldo_vgp5 {
1116				regulator-compatible = "ldo_vgp5";
1117				regulator-name = "vgp5";
1118				regulator-min-microvolt = <1200000>;
1119				regulator-max-microvolt = <3000000>;
1120				regulator-enable-ramp-delay = <218>;
1121			};
1122
1123			mt6397_vgp6_reg: ldo_vgp6 {
1124				regulator-compatible = "ldo_vgp6";
1125				regulator-name = "vgp6";
1126				regulator-min-microvolt = <3300000>;
1127				regulator-max-microvolt = <3300000>;
1128				regulator-enable-ramp-delay = <218>;
1129				regulator-always-on;
1130			};
1131
1132			mt6397_vibr_reg: ldo_vibr {
1133				regulator-compatible = "ldo_vibr";
1134				regulator-name = "vibr";
1135				regulator-min-microvolt = <1300000>;
1136				regulator-max-microvolt = <3300000>;
1137				regulator-enable-ramp-delay = <218>;
1138			};
1139		};
1140
1141		rtc: mt6397rtc {
1142			compatible = "mediatek,mt6397-rtc";
1143		};
1144
1145		syscfg_pctl_pmic: syscfg_pctl_pmic@c000 {
1146			compatible = "mediatek,mt6397-pctl-pmic-syscfg",
1147				     "syscon";
1148			reg = <0 0x0000c000 0 0x0108>;
1149		};
1150	};
1151};
1152
1153&spi {
1154	pinctrl-names = "default";
1155	pinctrl-0 = <&spi_pins_a>;
1156	mediatek,pad-select = <1>;
1157	status = "okay";
1158	/* clients */
1159	cros_ec: ec@0 {
1160		compatible = "google,cros-ec-spi";
1161		reg = <0x0>;
1162		spi-max-frequency = <12000000>;
1163		interrupt-parent = <&pio>;
1164		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
1165		google,cros-ec-spi-msg-delay = <500>;
1166
1167		i2c_tunnel: i2c-tunnel0 {
1168			compatible = "google,cros-ec-i2c-tunnel";
1169			google,remote-bus = <0>;
1170			#address-cells = <1>;
1171			#size-cells = <0>;
1172
1173			battery: sbs-battery@b {
1174				compatible = "sbs,sbs-battery";
1175				reg = <0xb>;
1176				sbs,i2c-retry-count = <2>;
1177				sbs,poll-retry-count = <1>;
1178			};
1179		};
1180	};
1181};
1182
1183&ssusb {
1184	dr_mode = "host";
1185	wakeup-source;
1186	vusb33-supply = <&mt6397_vusb_reg>;
1187	status = "okay";
1188};
1189
1190&thermal {
1191	bank0-supply = <&mt6397_vpca15_reg>;
1192	bank1-supply = <&da9211_vcpu_reg>;
1193};
1194
1195&uart0 {
1196	status = "okay";
1197};
1198
1199&usb_host {
1200	pinctrl-names = "default";
1201	pinctrl-0 = <&usb_pins>;
1202	vusb33-supply = <&mt6397_vusb_reg>;
1203	status = "okay";
1204};
1205
1206#include <arm/cros-ec-keyboard.dtsi>
1207