1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <&bl_pp5000>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 regulator-min-microvolt = <1800000>; 51 regulator-max-microvolt = <1800000>; 52 gpio = <&pio 178 0>; 53 enable-active-high; 54 }; 55 56 lcd_pp3300: regulator1 { 57 compatible = "regulator-fixed"; 58 regulator-name = "lcd_pp3300"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 bl_pp5000: regulator2 { 66 compatible = "regulator-fixed"; 67 regulator-name = "bl_pp5000"; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 mmc1_fixed_power: regulator3 { 75 compatible = "regulator-fixed"; 76 regulator-name = "mmc1_power"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 }; 80 81 mmc1_fixed_io: regulator4 { 82 compatible = "regulator-fixed"; 83 regulator-name = "mmc1_io"; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <1800000>; 86 }; 87 88 pp1800_alw: regulator5 { 89 compatible = "regulator-fixed"; 90 regulator-name = "pp1800_alw"; 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <1800000>; 94 regulator-max-microvolt = <1800000>; 95 }; 96 97 pp3300_alw: regulator6 { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp3300_alw"; 100 regulator-always-on; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 }; 105 106 reserved_memory: reserved-memory { 107 #address-cells = <2>; 108 #size-cells = <2>; 109 ranges; 110 111 scp_mem_reserved: scp_mem_region { 112 compatible = "shared-dma-pool"; 113 reg = <0 0x50000000 0 0x2900000>; 114 no-map; 115 }; 116 }; 117 118 sound: mt8183-sound { 119 mediatek,platform = <&afe>; 120 pinctrl-names = "default", 121 "aud_tdm_out_on", 122 "aud_tdm_out_off"; 123 pinctrl-0 = <&aud_pins_default>; 124 pinctrl-1 = <&aud_pins_tdm_out_on>; 125 pinctrl-2 = <&aud_pins_tdm_out_off>; 126 status = "okay"; 127 }; 128 129 btsco: bt-sco { 130 compatible = "linux,bt-sco"; 131 }; 132 133 wifi_pwrseq: wifi-pwrseq { 134 compatible = "mmc-pwrseq-simple"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&wifi_pins_pwrseq>; 137 138 /* Toggle WIFI_ENABLE to reset the chip. */ 139 reset-gpios = <&pio 119 1>; 140 }; 141 142 wifi_wakeup: wifi-wakeup { 143 compatible = "gpio-keys"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&wifi_pins_wakeup>; 146 147 button-wowlan { 148 label = "Wake on WiFi"; 149 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 150 linux,code = <KEY_WAKEUP>; 151 wakeup-source; 152 }; 153 }; 154 155 tboard_thermistor1: thermal-sensor1 { 156 compatible = "generic-adc-thermal"; 157 #thermal-sensor-cells = <0>; 158 io-channels = <&auxadc 0>; 159 io-channel-names = "sensor-channel"; 160 temperature-lookup-table = < (-5000) 1553 161 0 1488 162 5000 1412 163 10000 1326 164 15000 1232 165 20000 1132 166 25000 1029 167 30000 925 168 35000 823 169 40000 726 170 45000 635 171 50000 552 172 55000 478 173 60000 411 174 65000 353 175 70000 303 176 75000 260 177 80000 222 178 85000 190 179 90000 163 180 95000 140 181 100000 121 182 105000 104 183 110000 90 184 115000 78 185 120000 67 186 125000 59>; 187 }; 188 189 tboard_thermistor2: thermal-sensor2 { 190 compatible = "generic-adc-thermal"; 191 #thermal-sensor-cells = <0>; 192 io-channels = <&auxadc 1>; 193 io-channel-names = "sensor-channel"; 194 temperature-lookup-table = < (-5000) 1553 195 0 1488 196 5000 1412 197 10000 1326 198 15000 1232 199 20000 1132 200 25000 1029 201 30000 925 202 35000 823 203 40000 726 204 45000 635 205 50000 552 206 55000 478 207 60000 411 208 65000 353 209 70000 303 210 75000 260 211 80000 222 212 85000 190 213 90000 163 214 95000 140 215 100000 121 216 105000 104 217 110000 90 218 115000 78 219 120000 67 220 125000 59>; 221 }; 222}; 223 224&auxadc { 225 status = "okay"; 226}; 227 228&cci { 229 proc-supply = <&mt6358_vproc12_reg>; 230}; 231 232&cpu0 { 233 proc-supply = <&mt6358_vproc12_reg>; 234}; 235 236&cpu1 { 237 proc-supply = <&mt6358_vproc12_reg>; 238}; 239 240&cpu2 { 241 proc-supply = <&mt6358_vproc12_reg>; 242}; 243 244&cpu3 { 245 proc-supply = <&mt6358_vproc12_reg>; 246}; 247 248&cpu4 { 249 proc-supply = <&mt6358_vproc11_reg>; 250}; 251 252&cpu5 { 253 proc-supply = <&mt6358_vproc11_reg>; 254}; 255 256&cpu6 { 257 proc-supply = <&mt6358_vproc11_reg>; 258}; 259 260&cpu7 { 261 proc-supply = <&mt6358_vproc11_reg>; 262}; 263 264&dsi0 { 265 status = "okay"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 panel: panel@0 { 269 /* compatible will be set in board dts */ 270 reg = <0>; 271 enable-gpios = <&pio 45 0>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&panel_pins_default>; 274 avdd-supply = <&ppvarn_lcd>; 275 avee-supply = <&ppvarp_lcd>; 276 pp1800-supply = <&pp1800_lcd>; 277 backlight = <&backlight_lcd0>; 278 rotation = <270>; 279 port { 280 panel_in: endpoint { 281 remote-endpoint = <&dsi_out>; 282 }; 283 }; 284 }; 285 286 ports { 287 port { 288 dsi_out: endpoint { 289 remote-endpoint = <&panel_in>; 290 }; 291 }; 292 }; 293}; 294 295&gpu { 296 mali-supply = <&mt6358_vgpu_reg>; 297}; 298 299&i2c0 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c0_pins>; 302 status = "okay"; 303 clock-frequency = <400000>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306}; 307 308&i2c1 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&i2c1_pins>; 311 status = "okay"; 312 clock-frequency = <100000>; 313}; 314 315&i2c3 { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&i2c3_pins>; 318 status = "okay"; 319 clock-frequency = <100000>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322}; 323 324&i2c5 { 325 pinctrl-names = "default"; 326 pinctrl-0 = <&i2c5_pins>; 327 status = "okay"; 328 clock-frequency = <100000>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331}; 332 333&i2c6 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&i2c6_pins>; 336 status = "okay"; 337 clock-frequency = <100000>; 338}; 339 340&mipi_tx0 { 341 status = "okay"; 342}; 343 344&mmc0 { 345 status = "okay"; 346 pinctrl-names = "default", "state_uhs"; 347 pinctrl-0 = <&mmc0_pins_default>; 348 pinctrl-1 = <&mmc0_pins_uhs>; 349 bus-width = <8>; 350 max-frequency = <200000000>; 351 cap-mmc-highspeed; 352 mmc-hs200-1_8v; 353 mmc-hs400-1_8v; 354 cap-mmc-hw-reset; 355 no-sdio; 356 no-sd; 357 hs400-ds-delay = <0x12814>; 358 vmmc-supply = <&mt6358_vemc_reg>; 359 vqmmc-supply = <&mt6358_vio18_reg>; 360 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 361 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 362 non-removable; 363}; 364 365&mmc1 { 366 status = "okay"; 367 pinctrl-names = "default", "state_uhs"; 368 pinctrl-0 = <&mmc1_pins_default>; 369 pinctrl-1 = <&mmc1_pins_uhs>; 370 vmmc-supply = <&mmc1_fixed_power>; 371 vqmmc-supply = <&mmc1_fixed_io>; 372 mmc-pwrseq = <&wifi_pwrseq>; 373 bus-width = <4>; 374 max-frequency = <200000000>; 375 cap-sd-highspeed; 376 sd-uhs-sdr50; 377 sd-uhs-sdr104; 378 keep-power-in-suspend; 379 wakeup-source; 380 cap-sdio-irq; 381 non-removable; 382 no-mmc; 383 no-sd; 384 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 385 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 389 qca_wifi: qca-wifi@1 { 390 compatible = "qcom,ath10k"; 391 reg = <1>; 392 }; 393}; 394 395&mt6358_vdram2_reg { 396 regulator-always-on; 397}; 398 399&mt6358codec { 400 Avdd-supply = <&mt6358_vaud28_reg>; 401}; 402 403&mt6358_vgpu_reg { 404 regulator-min-microvolt = <625000>; 405 regulator-max-microvolt = <900000>; 406 407 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 408 regulator-coupled-max-spread = <100000>; 409}; 410 411&mt6358_vsim1_reg { 412 regulator-min-microvolt = <2700000>; 413 regulator-max-microvolt = <2700000>; 414}; 415 416&mt6358_vsim2_reg { 417 regulator-min-microvolt = <2700000>; 418 regulator-max-microvolt = <2700000>; 419}; 420 421&mt6358_vsram_gpu_reg { 422 regulator-min-microvolt = <850000>; 423 regulator-max-microvolt = <1000000>; 424 425 regulator-coupled-with = <&mt6358_vgpu_reg>; 426 regulator-coupled-max-spread = <100000>; 427}; 428 429&pio { 430 aud_pins_default: audiopins { 431 pins_bus { 432 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, 433 <PINMUX_GPIO98__FUNC_I2S2_BCK>, 434 <PINMUX_GPIO101__FUNC_I2S2_LRCK>, 435 <PINMUX_GPIO102__FUNC_I2S2_DI>, 436 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ 437 <PINMUX_GPIO89__FUNC_I2S5_BCK>, 438 <PINMUX_GPIO90__FUNC_I2S5_LRCK>, 439 <PINMUX_GPIO91__FUNC_I2S5_DO>, 440 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ 441 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, 442 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, 443 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, 444 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, 445 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, 446 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, 447 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, 448 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ 449 }; 450 }; 451 452 aud_pins_tdm_out_on: audiotdmouton { 453 pins_bus { 454 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, 455 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, 456 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, 457 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, 458 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, 459 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ 460 drive-strength = <MTK_DRIVE_6mA>; 461 }; 462 }; 463 464 aud_pins_tdm_out_off: audiotdmoutoff { 465 pins_bus { 466 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, 467 <PINMUX_GPIO170__FUNC_GPIO170>, 468 <PINMUX_GPIO171__FUNC_GPIO171>, 469 <PINMUX_GPIO172__FUNC_GPIO172>, 470 <PINMUX_GPIO173__FUNC_GPIO173>, 471 <PINMUX_GPIO10__FUNC_GPIO10>; 472 input-enable; 473 bias-pull-down; 474 drive-strength = <MTK_DRIVE_2mA>; 475 }; 476 }; 477 478 bt_pins: bt-pins { 479 pins_bt_en { 480 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 481 output-low; 482 }; 483 }; 484 485 ec_ap_int_odl: ec_ap_int_odl { 486 pins1 { 487 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 488 input-enable; 489 bias-pull-up; 490 }; 491 }; 492 493 h1_int_od_l: h1_int_od_l { 494 pins1 { 495 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 496 input-enable; 497 }; 498 }; 499 500 i2c0_pins: i2c0 { 501 pins_bus { 502 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 503 <PINMUX_GPIO83__FUNC_SCL0>; 504 mediatek,pull-up-adv = <3>; 505 mediatek,drive-strength-adv = <00>; 506 }; 507 }; 508 509 i2c1_pins: i2c1 { 510 pins_bus { 511 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 512 <PINMUX_GPIO84__FUNC_SCL1>; 513 mediatek,pull-up-adv = <3>; 514 mediatek,drive-strength-adv = <00>; 515 }; 516 }; 517 518 i2c2_pins: i2c2 { 519 pins_bus { 520 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 521 <PINMUX_GPIO104__FUNC_SDA2>; 522 bias-disable; 523 mediatek,drive-strength-adv = <00>; 524 }; 525 }; 526 527 i2c3_pins: i2c3 { 528 pins_bus { 529 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 530 <PINMUX_GPIO51__FUNC_SDA3>; 531 mediatek,pull-up-adv = <3>; 532 mediatek,drive-strength-adv = <00>; 533 }; 534 }; 535 536 i2c4_pins: i2c4 { 537 pins_bus { 538 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 539 <PINMUX_GPIO106__FUNC_SDA4>; 540 bias-disable; 541 mediatek,drive-strength-adv = <00>; 542 }; 543 }; 544 545 i2c5_pins: i2c5 { 546 pins_bus { 547 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 548 <PINMUX_GPIO49__FUNC_SDA5>; 549 mediatek,pull-up-adv = <3>; 550 mediatek,drive-strength-adv = <00>; 551 }; 552 }; 553 554 i2c6_pins: i2c6 { 555 pins_bus { 556 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 557 <PINMUX_GPIO12__FUNC_SDA6>; 558 bias-disable; 559 }; 560 }; 561 562 mmc0_pins_default: mmc0-pins-default { 563 pins_cmd_dat { 564 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 565 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 566 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 567 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 568 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 569 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 570 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 571 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 572 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 573 input-enable; 574 drive-strength = <MTK_DRIVE_14mA>; 575 mediatek,pull-up-adv = <01>; 576 }; 577 578 pins_clk { 579 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 580 drive-strength = <MTK_DRIVE_14mA>; 581 mediatek,pull-down-adv = <10>; 582 }; 583 584 pins_rst { 585 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 586 drive-strength = <MTK_DRIVE_14mA>; 587 mediatek,pull-down-adv = <01>; 588 }; 589 }; 590 591 mmc0_pins_uhs: mmc0-pins-uhs { 592 pins_cmd_dat { 593 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 594 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 595 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 596 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 597 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 598 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 599 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 600 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 601 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 602 input-enable; 603 drive-strength = <MTK_DRIVE_14mA>; 604 mediatek,pull-up-adv = <01>; 605 }; 606 607 pins_clk { 608 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 609 drive-strength = <MTK_DRIVE_14mA>; 610 mediatek,pull-down-adv = <10>; 611 }; 612 613 pins_ds { 614 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 615 drive-strength = <MTK_DRIVE_14mA>; 616 mediatek,pull-down-adv = <10>; 617 }; 618 619 pins_rst { 620 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 621 drive-strength = <MTK_DRIVE_14mA>; 622 mediatek,pull-up-adv = <01>; 623 }; 624 }; 625 626 mmc1_pins_default: mmc1-pins-default { 627 pins_cmd_dat { 628 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 629 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 630 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 631 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 632 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 633 input-enable; 634 mediatek,pull-up-adv = <10>; 635 }; 636 637 pins_clk { 638 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 639 input-enable; 640 mediatek,pull-down-adv = <10>; 641 }; 642 }; 643 644 mmc1_pins_uhs: mmc1-pins-uhs { 645 pins_cmd_dat { 646 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 647 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 648 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 649 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 650 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 651 drive-strength = <MTK_DRIVE_6mA>; 652 input-enable; 653 mediatek,pull-up-adv = <10>; 654 }; 655 656 pins_clk { 657 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 658 drive-strength = <MTK_DRIVE_8mA>; 659 mediatek,pull-down-adv = <10>; 660 input-enable; 661 }; 662 }; 663 664 panel_pins_default: panel_pins_default { 665 panel_reset { 666 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 667 output-low; 668 bias-pull-up; 669 }; 670 }; 671 672 pwm0_pin_default: pwm0_pin_default { 673 pins1 { 674 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 675 output-high; 676 bias-pull-up; 677 }; 678 pins2 { 679 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 680 }; 681 }; 682 683 scp_pins: scp { 684 pins_scp_uart { 685 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 686 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 687 }; 688 }; 689 690 spi0_pins: spi0 { 691 pins_spi{ 692 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 693 <PINMUX_GPIO86__FUNC_GPIO86>, 694 <PINMUX_GPIO87__FUNC_SPI0_MO>, 695 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 696 bias-disable; 697 }; 698 }; 699 700 spi1_pins: spi1 { 701 pins_spi{ 702 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 703 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 704 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 705 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 706 bias-disable; 707 }; 708 }; 709 710 spi2_pins: spi2 { 711 pins_spi{ 712 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 713 <PINMUX_GPIO1__FUNC_SPI2_MO>, 714 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 715 bias-disable; 716 }; 717 pins_spi_mi { 718 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 719 mediatek,pull-down-adv = <00>; 720 }; 721 }; 722 723 spi3_pins: spi3 { 724 pins_spi{ 725 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 726 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 727 <PINMUX_GPIO23__FUNC_SPI3_MO>, 728 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 729 bias-disable; 730 }; 731 }; 732 733 spi4_pins: spi4 { 734 pins_spi{ 735 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 736 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 737 <PINMUX_GPIO19__FUNC_SPI4_MO>, 738 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 739 bias-disable; 740 }; 741 }; 742 743 spi5_pins: spi5 { 744 pins_spi{ 745 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 746 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 747 <PINMUX_GPIO15__FUNC_SPI5_MO>, 748 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 749 bias-disable; 750 }; 751 }; 752 753 uart0_pins_default: uart0-pins-default { 754 pins_rx { 755 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 756 input-enable; 757 bias-pull-up; 758 }; 759 pins_tx { 760 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 761 }; 762 }; 763 764 uart1_pins_default: uart1-pins-default { 765 pins_rx { 766 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 767 input-enable; 768 bias-pull-up; 769 }; 770 pins_tx { 771 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 772 }; 773 pins_rts { 774 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 775 output-enable; 776 }; 777 pins_cts { 778 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 779 input-enable; 780 }; 781 }; 782 783 uart1_pins_sleep: uart1-pins-sleep { 784 pins_rx { 785 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 786 input-enable; 787 bias-pull-up; 788 }; 789 pins_tx { 790 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 791 }; 792 pins_rts { 793 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 794 output-enable; 795 }; 796 pins_cts { 797 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 798 input-enable; 799 }; 800 }; 801 802 wifi_pins_pwrseq: wifi-pins-pwrseq { 803 pins_wifi_enable { 804 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 805 output-low; 806 }; 807 }; 808 809 wifi_pins_wakeup: wifi-pins-wakeup { 810 pins_wifi_wakeup { 811 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 812 input-enable; 813 }; 814 }; 815}; 816 817&pwm0 { 818 status = "okay"; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&pwm0_pin_default>; 821}; 822 823&scp { 824 status = "okay"; 825 pinctrl-names = "default"; 826 pinctrl-0 = <&scp_pins>; 827 828 cros_ec { 829 compatible = "google,cros-ec-rpmsg"; 830 mediatek,rpmsg-name = "cros-ec-rpmsg"; 831 }; 832}; 833 834&mfg_async { 835 domain-supply = <&mt6358_vsram_gpu_reg>; 836}; 837 838&mfg { 839 domain-supply = <&mt6358_vgpu_reg>; 840}; 841 842&soc_data { 843 status = "okay"; 844}; 845 846&spi0 { 847 pinctrl-names = "default"; 848 pinctrl-0 = <&spi0_pins>; 849 mediatek,pad-select = <0>; 850 status = "okay"; 851 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 852 853 cr50@0 { 854 compatible = "google,cr50"; 855 reg = <0>; 856 spi-max-frequency = <1000000>; 857 pinctrl-names = "default"; 858 pinctrl-0 = <&h1_int_od_l>; 859 interrupt-parent = <&pio>; 860 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 861 }; 862}; 863 864&spi1 { 865 pinctrl-names = "default"; 866 pinctrl-0 = <&spi1_pins>; 867 mediatek,pad-select = <0>; 868 status = "okay"; 869 870 w25q64dw: flash@0 { 871 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 872 reg = <0>; 873 spi-max-frequency = <25000000>; 874 }; 875}; 876 877&spi2 { 878 pinctrl-names = "default"; 879 pinctrl-0 = <&spi2_pins>; 880 mediatek,pad-select = <0>; 881 status = "okay"; 882 883 cros_ec: cros-ec@0 { 884 compatible = "google,cros-ec-spi"; 885 reg = <0>; 886 spi-max-frequency = <3000000>; 887 interrupt-parent = <&pio>; 888 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&ec_ap_int_odl>; 891 892 i2c_tunnel: i2c-tunnel { 893 compatible = "google,cros-ec-i2c-tunnel"; 894 google,remote-bus = <1>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 }; 898 899 usbc_extcon: extcon0 { 900 compatible = "google,extcon-usbc-cros-ec"; 901 google,usb-port-id = <0>; 902 }; 903 904 cbas { 905 compatible = "google,cros-cbas"; 906 }; 907 908 typec { 909 compatible = "google,cros-ec-typec"; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 913 usb_c0: connector@0 { 914 compatible = "usb-c-connector"; 915 reg = <0>; 916 power-role = "dual"; 917 data-role = "host"; 918 try-power-role = "sink"; 919 }; 920 }; 921 }; 922}; 923 924&spi3 { 925 pinctrl-names = "default"; 926 pinctrl-0 = <&spi3_pins>; 927 mediatek,pad-select = <0>; 928 status = "disabled"; 929}; 930 931&spi4 { 932 pinctrl-names = "default"; 933 pinctrl-0 = <&spi4_pins>; 934 mediatek,pad-select = <0>; 935 status = "disabled"; 936}; 937 938&spi5 { 939 pinctrl-names = "default"; 940 pinctrl-0 = <&spi5_pins>; 941 mediatek,pad-select = <0>; 942 status = "disabled"; 943}; 944 945&ssusb { 946 dr_mode = "host"; 947 wakeup-source; 948 vusb33-supply = <&mt6358_vusb_reg>; 949 status = "okay"; 950}; 951 952&thermal_zones { 953 tboard1 { 954 polling-delay = <1000>; /* milliseconds */ 955 polling-delay-passive = <0>; /* milliseconds */ 956 thermal-sensors = <&tboard_thermistor1>; 957 }; 958 959 tboard2 { 960 polling-delay = <1000>; /* milliseconds */ 961 polling-delay-passive = <0>; /* milliseconds */ 962 thermal-sensors = <&tboard_thermistor2>; 963 }; 964}; 965 966&u3phy { 967 status = "okay"; 968}; 969 970&uart0 { 971 pinctrl-names = "default"; 972 pinctrl-0 = <&uart0_pins_default>; 973 status = "okay"; 974}; 975 976&uart1 { 977 pinctrl-names = "default", "sleep"; 978 pinctrl-0 = <&uart1_pins_default>; 979 pinctrl-1 = <&uart1_pins_sleep>; 980 status = "okay"; 981 /delete-property/ interrupts; 982 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 983 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 984 985 bluetooth: bluetooth { 986 pinctrl-names = "default"; 987 pinctrl-0 = <&bt_pins>; 988 status = "okay"; 989 compatible = "qcom,qca6174-bt"; 990 enable-gpios = <&pio 120 0>; 991 clocks = <&clk32k>; 992 firmware-name = "nvm_00440302_i2s.bin"; 993 }; 994}; 995 996&usb_host { 997 #address-cells = <1>; 998 #size-cells = <0>; 999 vusb33-supply = <&mt6358_vusb_reg>; 1000 status = "okay"; 1001 1002 hub@1 { 1003 compatible = "usb5e3,610"; 1004 reg = <1>; 1005 }; 1006}; 1007 1008#include <arm/cros-ec-sbs.dtsi> 1009