1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 112 #dma-cells = <1>; 113 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 114 dma-coherent; 115 status = "okay"; 116 }; 117 118 aconnect@2900000 { 119 compatible = "nvidia,tegra186-aconnect", 120 "nvidia,tegra210-aconnect"; 121 clocks = <&bpmp TEGRA186_CLK_APE>, 122 <&bpmp TEGRA186_CLK_APB2APE>; 123 clock-names = "ape", "apb2ape"; 124 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x02900000 0x0 0x02900000 0x200000>; 128 status = "disabled"; 129 130 adma: dma-controller@2930000 { 131 compatible = "nvidia,tegra186-adma"; 132 reg = <0x02930000 0x20000>; 133 interrupt-parent = <&agic>; 134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 clocks = <&bpmp TEGRA186_CLK_AHUB>; 168 clock-names = "d_audio"; 169 status = "disabled"; 170 }; 171 172 agic: interrupt-controller@2a40000 { 173 compatible = "nvidia,tegra186-agic", 174 "nvidia,tegra210-agic"; 175 #interrupt-cells = <3>; 176 interrupt-controller; 177 reg = <0x02a41000 0x1000>, 178 <0x02a42000 0x2000>; 179 interrupts = <GIC_SPI 145 180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 181 clocks = <&bpmp TEGRA186_CLK_APE>; 182 clock-names = "clk"; 183 status = "disabled"; 184 }; 185 186 tegra_ahub: ahub@2900800 { 187 compatible = "nvidia,tegra186-ahub"; 188 reg = <0x02900800 0x800>; 189 clocks = <&bpmp TEGRA186_CLK_AHUB>; 190 clock-names = "ahub"; 191 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 192 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 ranges = <0x02900800 0x02900800 0x11800>; 196 status = "disabled"; 197 198 tegra_admaif: admaif@290f000 { 199 compatible = "nvidia,tegra186-admaif"; 200 reg = <0x0290f000 0x1000>; 201 dmas = <&adma 1>, <&adma 1>, 202 <&adma 2>, <&adma 2>, 203 <&adma 3>, <&adma 3>, 204 <&adma 4>, <&adma 4>, 205 <&adma 5>, <&adma 5>, 206 <&adma 6>, <&adma 6>, 207 <&adma 7>, <&adma 7>, 208 <&adma 8>, <&adma 8>, 209 <&adma 9>, <&adma 9>, 210 <&adma 10>, <&adma 10>, 211 <&adma 11>, <&adma 11>, 212 <&adma 12>, <&adma 12>, 213 <&adma 13>, <&adma 13>, 214 <&adma 14>, <&adma 14>, 215 <&adma 15>, <&adma 15>, 216 <&adma 16>, <&adma 16>, 217 <&adma 17>, <&adma 17>, 218 <&adma 18>, <&adma 18>, 219 <&adma 19>, <&adma 19>, 220 <&adma 20>, <&adma 20>; 221 dma-names = "rx1", "tx1", 222 "rx2", "tx2", 223 "rx3", "tx3", 224 "rx4", "tx4", 225 "rx5", "tx5", 226 "rx6", "tx6", 227 "rx7", "tx7", 228 "rx8", "tx8", 229 "rx9", "tx9", 230 "rx10", "tx10", 231 "rx11", "tx11", 232 "rx12", "tx12", 233 "rx13", "tx13", 234 "rx14", "tx14", 235 "rx15", "tx15", 236 "rx16", "tx16", 237 "rx17", "tx17", 238 "rx18", "tx18", 239 "rx19", "tx19", 240 "rx20", "tx20"; 241 status = "disabled"; 242 }; 243 244 tegra_i2s1: i2s@2901000 { 245 compatible = "nvidia,tegra186-i2s", 246 "nvidia,tegra210-i2s"; 247 reg = <0x2901000 0x100>; 248 clocks = <&bpmp TEGRA186_CLK_I2S1>, 249 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 250 clock-names = "i2s", "sync_input"; 251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253 assigned-clock-rates = <1536000>; 254 sound-name-prefix = "I2S1"; 255 status = "disabled"; 256 }; 257 258 tegra_i2s2: i2s@2901100 { 259 compatible = "nvidia,tegra186-i2s", 260 "nvidia,tegra210-i2s"; 261 reg = <0x2901100 0x100>; 262 clocks = <&bpmp TEGRA186_CLK_I2S2>, 263 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 264 clock-names = "i2s", "sync_input"; 265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267 assigned-clock-rates = <1536000>; 268 sound-name-prefix = "I2S2"; 269 status = "disabled"; 270 }; 271 272 tegra_i2s3: i2s@2901200 { 273 compatible = "nvidia,tegra186-i2s", 274 "nvidia,tegra210-i2s"; 275 reg = <0x2901200 0x100>; 276 clocks = <&bpmp TEGRA186_CLK_I2S3>, 277 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 278 clock-names = "i2s", "sync_input"; 279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281 assigned-clock-rates = <1536000>; 282 sound-name-prefix = "I2S3"; 283 status = "disabled"; 284 }; 285 286 tegra_i2s4: i2s@2901300 { 287 compatible = "nvidia,tegra186-i2s", 288 "nvidia,tegra210-i2s"; 289 reg = <0x2901300 0x100>; 290 clocks = <&bpmp TEGRA186_CLK_I2S4>, 291 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 292 clock-names = "i2s", "sync_input"; 293 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 294 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 295 assigned-clock-rates = <1536000>; 296 sound-name-prefix = "I2S4"; 297 status = "disabled"; 298 }; 299 300 tegra_i2s5: i2s@2901400 { 301 compatible = "nvidia,tegra186-i2s", 302 "nvidia,tegra210-i2s"; 303 reg = <0x2901400 0x100>; 304 clocks = <&bpmp TEGRA186_CLK_I2S5>, 305 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 306 clock-names = "i2s", "sync_input"; 307 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 308 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 309 assigned-clock-rates = <1536000>; 310 sound-name-prefix = "I2S5"; 311 status = "disabled"; 312 }; 313 314 tegra_i2s6: i2s@2901500 { 315 compatible = "nvidia,tegra186-i2s", 316 "nvidia,tegra210-i2s"; 317 reg = <0x2901500 0x100>; 318 clocks = <&bpmp TEGRA186_CLK_I2S6>, 319 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 320 clock-names = "i2s", "sync_input"; 321 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 322 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 323 assigned-clock-rates = <1536000>; 324 sound-name-prefix = "I2S6"; 325 status = "disabled"; 326 }; 327 328 tegra_dmic1: dmic@2904000 { 329 compatible = "nvidia,tegra210-dmic"; 330 reg = <0x2904000 0x100>; 331 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 332 clock-names = "dmic"; 333 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 335 assigned-clock-rates = <3072000>; 336 sound-name-prefix = "DMIC1"; 337 status = "disabled"; 338 }; 339 340 tegra_dmic2: dmic@2904100 { 341 compatible = "nvidia,tegra210-dmic"; 342 reg = <0x2904100 0x100>; 343 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 344 clock-names = "dmic"; 345 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 347 assigned-clock-rates = <3072000>; 348 sound-name-prefix = "DMIC2"; 349 status = "disabled"; 350 }; 351 352 tegra_dmic3: dmic@2904200 { 353 compatible = "nvidia,tegra210-dmic"; 354 reg = <0x2904200 0x100>; 355 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 356 clock-names = "dmic"; 357 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 359 assigned-clock-rates = <3072000>; 360 sound-name-prefix = "DMIC3"; 361 status = "disabled"; 362 }; 363 364 tegra_dmic4: dmic@2904300 { 365 compatible = "nvidia,tegra210-dmic"; 366 reg = <0x2904300 0x100>; 367 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 368 clock-names = "dmic"; 369 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 371 assigned-clock-rates = <3072000>; 372 sound-name-prefix = "DMIC4"; 373 status = "disabled"; 374 }; 375 376 tegra_dspk1: dspk@2905000 { 377 compatible = "nvidia,tegra186-dspk"; 378 reg = <0x2905000 0x100>; 379 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 380 clock-names = "dspk"; 381 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 383 assigned-clock-rates = <12288000>; 384 sound-name-prefix = "DSPK1"; 385 status = "disabled"; 386 }; 387 388 tegra_dspk2: dspk@2905100 { 389 compatible = "nvidia,tegra186-dspk"; 390 reg = <0x2905100 0x100>; 391 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 392 clock-names = "dspk"; 393 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 395 assigned-clock-rates = <12288000>; 396 sound-name-prefix = "DSPK2"; 397 status = "disabled"; 398 }; 399 400 tegra_sfc1: sfc@2902000 { 401 compatible = "nvidia,tegra186-sfc", 402 "nvidia,tegra210-sfc"; 403 reg = <0x2902000 0x200>; 404 sound-name-prefix = "SFC1"; 405 status = "disabled"; 406 }; 407 408 tegra_sfc2: sfc@2902200 { 409 compatible = "nvidia,tegra186-sfc", 410 "nvidia,tegra210-sfc"; 411 reg = <0x2902200 0x200>; 412 sound-name-prefix = "SFC2"; 413 status = "disabled"; 414 }; 415 416 tegra_sfc3: sfc@2902400 { 417 compatible = "nvidia,tegra186-sfc", 418 "nvidia,tegra210-sfc"; 419 reg = <0x2902400 0x200>; 420 sound-name-prefix = "SFC3"; 421 status = "disabled"; 422 }; 423 424 tegra_sfc4: sfc@2902600 { 425 compatible = "nvidia,tegra186-sfc", 426 "nvidia,tegra210-sfc"; 427 reg = <0x2902600 0x200>; 428 sound-name-prefix = "SFC4"; 429 status = "disabled"; 430 }; 431 432 tegra_mvc1: mvc@290a000 { 433 compatible = "nvidia,tegra186-mvc", 434 "nvidia,tegra210-mvc"; 435 reg = <0x290a000 0x200>; 436 sound-name-prefix = "MVC1"; 437 status = "disabled"; 438 }; 439 440 tegra_mvc2: mvc@290a200 { 441 compatible = "nvidia,tegra186-mvc", 442 "nvidia,tegra210-mvc"; 443 reg = <0x290a200 0x200>; 444 sound-name-prefix = "MVC2"; 445 status = "disabled"; 446 }; 447 448 tegra_amx1: amx@2903000 { 449 compatible = "nvidia,tegra186-amx", 450 "nvidia,tegra210-amx"; 451 reg = <0x2903000 0x100>; 452 sound-name-prefix = "AMX1"; 453 status = "disabled"; 454 }; 455 456 tegra_amx2: amx@2903100 { 457 compatible = "nvidia,tegra186-amx", 458 "nvidia,tegra210-amx"; 459 reg = <0x2903100 0x100>; 460 sound-name-prefix = "AMX2"; 461 status = "disabled"; 462 }; 463 464 tegra_amx3: amx@2903200 { 465 compatible = "nvidia,tegra186-amx", 466 "nvidia,tegra210-amx"; 467 reg = <0x2903200 0x100>; 468 sound-name-prefix = "AMX3"; 469 status = "disabled"; 470 }; 471 472 tegra_amx4: amx@2903300 { 473 compatible = "nvidia,tegra186-amx", 474 "nvidia,tegra210-amx"; 475 reg = <0x2903300 0x100>; 476 sound-name-prefix = "AMX4"; 477 status = "disabled"; 478 }; 479 480 tegra_adx1: adx@2903800 { 481 compatible = "nvidia,tegra186-adx", 482 "nvidia,tegra210-adx"; 483 reg = <0x2903800 0x100>; 484 sound-name-prefix = "ADX1"; 485 status = "disabled"; 486 }; 487 488 tegra_adx2: adx@2903900 { 489 compatible = "nvidia,tegra186-adx", 490 "nvidia,tegra210-adx"; 491 reg = <0x2903900 0x100>; 492 sound-name-prefix = "ADX2"; 493 status = "disabled"; 494 }; 495 496 tegra_adx3: adx@2903a00 { 497 compatible = "nvidia,tegra186-adx", 498 "nvidia,tegra210-adx"; 499 reg = <0x2903a00 0x100>; 500 sound-name-prefix = "ADX3"; 501 status = "disabled"; 502 }; 503 504 tegra_adx4: adx@2903b00 { 505 compatible = "nvidia,tegra186-adx", 506 "nvidia,tegra210-adx"; 507 reg = <0x2903b00 0x100>; 508 sound-name-prefix = "ADX4"; 509 status = "disabled"; 510 }; 511 512 tegra_ope1: processing-engine@2908000 { 513 compatible = "nvidia,tegra186-ope", 514 "nvidia,tegra210-ope"; 515 reg = <0x2908000 0x100>; 516 #address-cells = <1>; 517 #size-cells = <1>; 518 ranges; 519 sound-name-prefix = "OPE1"; 520 status = "disabled"; 521 522 equalizer@2908100 { 523 compatible = "nvidia,tegra186-peq", 524 "nvidia,tegra210-peq"; 525 reg = <0x2908100 0x100>; 526 }; 527 528 dynamic-range-compressor@2908200 { 529 compatible = "nvidia,tegra186-mbdrc", 530 "nvidia,tegra210-mbdrc"; 531 reg = <0x2908200 0x200>; 532 }; 533 }; 534 535 tegra_amixer: amixer@290bb00 { 536 compatible = "nvidia,tegra186-amixer", 537 "nvidia,tegra210-amixer"; 538 reg = <0x290bb00 0x800>; 539 sound-name-prefix = "MIXER1"; 540 status = "disabled"; 541 }; 542 543 tegra_asrc: asrc@2910000 { 544 compatible = "nvidia,tegra186-asrc"; 545 reg = <0x2910000 0x2000>; 546 sound-name-prefix = "ASRC1"; 547 status = "disabled"; 548 }; 549 }; 550 }; 551 552 mc: memory-controller@2c00000 { 553 compatible = "nvidia,tegra186-mc"; 554 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 555 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 556 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 557 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 558 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 559 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 560 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 561 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 562 status = "disabled"; 563 564 #interconnect-cells = <1>; 565 #address-cells = <2>; 566 #size-cells = <2>; 567 568 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 569 570 /* 571 * Memory clients have access to all 40 bits that the memory 572 * controller can address. 573 */ 574 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 575 576 emc: external-memory-controller@2c60000 { 577 compatible = "nvidia,tegra186-emc"; 578 reg = <0x0 0x02c60000 0x0 0x50000>; 579 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&bpmp TEGRA186_CLK_EMC>; 581 clock-names = "emc"; 582 583 #interconnect-cells = <0>; 584 585 nvidia,bpmp = <&bpmp>; 586 }; 587 }; 588 589 timer@3010000 { 590 compatible = "nvidia,tegra186-timer"; 591 reg = <0x0 0x03010000 0x0 0x000e0000>; 592 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 602 status = "okay"; 603 }; 604 605 uarta: serial@3100000 { 606 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 607 reg = <0x0 0x03100000 0x0 0x40>; 608 reg-shift = <2>; 609 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&bpmp TEGRA186_CLK_UARTA>; 611 clock-names = "serial"; 612 resets = <&bpmp TEGRA186_RESET_UARTA>; 613 reset-names = "serial"; 614 status = "disabled"; 615 }; 616 617 uartb: serial@3110000 { 618 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 619 reg = <0x0 0x03110000 0x0 0x40>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA186_CLK_UARTB>; 623 clock-names = "serial"; 624 resets = <&bpmp TEGRA186_RESET_UARTB>; 625 reset-names = "serial"; 626 status = "disabled"; 627 }; 628 629 uartd: serial@3130000 { 630 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 631 reg = <0x0 0x03130000 0x0 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA186_CLK_UARTD>; 635 clock-names = "serial"; 636 resets = <&bpmp TEGRA186_RESET_UARTD>; 637 reset-names = "serial"; 638 status = "disabled"; 639 }; 640 641 uarte: serial@3140000 { 642 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 643 reg = <0x0 0x03140000 0x0 0x40>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA186_CLK_UARTE>; 647 clock-names = "serial"; 648 resets = <&bpmp TEGRA186_RESET_UARTE>; 649 reset-names = "serial"; 650 status = "disabled"; 651 }; 652 653 uartf: serial@3150000 { 654 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 655 reg = <0x0 0x03150000 0x0 0x40>; 656 reg-shift = <2>; 657 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA186_CLK_UARTF>; 659 clock-names = "serial"; 660 resets = <&bpmp TEGRA186_RESET_UARTF>; 661 reset-names = "serial"; 662 status = "disabled"; 663 }; 664 665 gen1_i2c: i2c@3160000 { 666 compatible = "nvidia,tegra186-i2c"; 667 reg = <0x0 0x03160000 0x0 0x10000>; 668 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&bpmp TEGRA186_CLK_I2C1>; 672 clock-names = "div-clk"; 673 resets = <&bpmp TEGRA186_RESET_I2C1>; 674 reset-names = "i2c"; 675 status = "disabled"; 676 }; 677 678 cam_i2c: i2c@3180000 { 679 compatible = "nvidia,tegra186-i2c"; 680 reg = <0x0 0x03180000 0x0 0x10000>; 681 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 clocks = <&bpmp TEGRA186_CLK_I2C3>; 685 clock-names = "div-clk"; 686 resets = <&bpmp TEGRA186_RESET_I2C3>; 687 reset-names = "i2c"; 688 status = "disabled"; 689 }; 690 691 /* shares pads with dpaux1 */ 692 dp_aux_ch1_i2c: i2c@3190000 { 693 compatible = "nvidia,tegra186-i2c"; 694 reg = <0x0 0x03190000 0x0 0x10000>; 695 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 clocks = <&bpmp TEGRA186_CLK_I2C4>; 699 clock-names = "div-clk"; 700 resets = <&bpmp TEGRA186_RESET_I2C4>; 701 reset-names = "i2c"; 702 pinctrl-names = "default", "idle"; 703 pinctrl-0 = <&state_dpaux1_i2c>; 704 pinctrl-1 = <&state_dpaux1_off>; 705 status = "disabled"; 706 }; 707 708 /* controlled by BPMP, should not be enabled */ 709 pwr_i2c: i2c@31a0000 { 710 compatible = "nvidia,tegra186-i2c"; 711 reg = <0x0 0x031a0000 0x0 0x10000>; 712 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 clocks = <&bpmp TEGRA186_CLK_I2C5>; 716 clock-names = "div-clk"; 717 resets = <&bpmp TEGRA186_RESET_I2C5>; 718 reset-names = "i2c"; 719 status = "disabled"; 720 }; 721 722 /* shares pads with dpaux0 */ 723 dp_aux_ch0_i2c: i2c@31b0000 { 724 compatible = "nvidia,tegra186-i2c"; 725 reg = <0x0 0x031b0000 0x0 0x10000>; 726 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&bpmp TEGRA186_CLK_I2C6>; 730 clock-names = "div-clk"; 731 resets = <&bpmp TEGRA186_RESET_I2C6>; 732 reset-names = "i2c"; 733 pinctrl-names = "default", "idle"; 734 pinctrl-0 = <&state_dpaux_i2c>; 735 pinctrl-1 = <&state_dpaux_off>; 736 status = "disabled"; 737 }; 738 739 gen7_i2c: i2c@31c0000 { 740 compatible = "nvidia,tegra186-i2c"; 741 reg = <0x0 0x031c0000 0x0 0x10000>; 742 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 clocks = <&bpmp TEGRA186_CLK_I2C7>; 746 clock-names = "div-clk"; 747 resets = <&bpmp TEGRA186_RESET_I2C7>; 748 reset-names = "i2c"; 749 status = "disabled"; 750 }; 751 752 gen9_i2c: i2c@31e0000 { 753 compatible = "nvidia,tegra186-i2c"; 754 reg = <0x0 0x031e0000 0x0 0x10000>; 755 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 clocks = <&bpmp TEGRA186_CLK_I2C9>; 759 clock-names = "div-clk"; 760 resets = <&bpmp TEGRA186_RESET_I2C9>; 761 reset-names = "i2c"; 762 status = "disabled"; 763 }; 764 765 pwm1: pwm@3280000 { 766 compatible = "nvidia,tegra186-pwm"; 767 reg = <0x0 0x3280000 0x0 0x10000>; 768 clocks = <&bpmp TEGRA186_CLK_PWM1>; 769 clock-names = "pwm"; 770 resets = <&bpmp TEGRA186_RESET_PWM1>; 771 reset-names = "pwm"; 772 status = "disabled"; 773 #pwm-cells = <2>; 774 }; 775 776 pwm2: pwm@3290000 { 777 compatible = "nvidia,tegra186-pwm"; 778 reg = <0x0 0x3290000 0x0 0x10000>; 779 clocks = <&bpmp TEGRA186_CLK_PWM2>; 780 clock-names = "pwm"; 781 resets = <&bpmp TEGRA186_RESET_PWM2>; 782 reset-names = "pwm"; 783 status = "disabled"; 784 #pwm-cells = <2>; 785 }; 786 787 pwm3: pwm@32a0000 { 788 compatible = "nvidia,tegra186-pwm"; 789 reg = <0x0 0x32a0000 0x0 0x10000>; 790 clocks = <&bpmp TEGRA186_CLK_PWM3>; 791 clock-names = "pwm"; 792 resets = <&bpmp TEGRA186_RESET_PWM3>; 793 reset-names = "pwm"; 794 status = "disabled"; 795 #pwm-cells = <2>; 796 }; 797 798 pwm5: pwm@32c0000 { 799 compatible = "nvidia,tegra186-pwm"; 800 reg = <0x0 0x32c0000 0x0 0x10000>; 801 clocks = <&bpmp TEGRA186_CLK_PWM5>; 802 clock-names = "pwm"; 803 resets = <&bpmp TEGRA186_RESET_PWM5>; 804 reset-names = "pwm"; 805 status = "disabled"; 806 #pwm-cells = <2>; 807 }; 808 809 pwm6: pwm@32d0000 { 810 compatible = "nvidia,tegra186-pwm"; 811 reg = <0x0 0x32d0000 0x0 0x10000>; 812 clocks = <&bpmp TEGRA186_CLK_PWM6>; 813 clock-names = "pwm"; 814 resets = <&bpmp TEGRA186_RESET_PWM6>; 815 reset-names = "pwm"; 816 status = "disabled"; 817 #pwm-cells = <2>; 818 }; 819 820 pwm7: pwm@32e0000 { 821 compatible = "nvidia,tegra186-pwm"; 822 reg = <0x0 0x32e0000 0x0 0x10000>; 823 clocks = <&bpmp TEGRA186_CLK_PWM7>; 824 clock-names = "pwm"; 825 resets = <&bpmp TEGRA186_RESET_PWM7>; 826 reset-names = "pwm"; 827 status = "disabled"; 828 #pwm-cells = <2>; 829 }; 830 831 pwm8: pwm@32f0000 { 832 compatible = "nvidia,tegra186-pwm"; 833 reg = <0x0 0x32f0000 0x0 0x10000>; 834 clocks = <&bpmp TEGRA186_CLK_PWM8>; 835 clock-names = "pwm"; 836 resets = <&bpmp TEGRA186_RESET_PWM8>; 837 reset-names = "pwm"; 838 status = "disabled"; 839 #pwm-cells = <2>; 840 }; 841 842 sdmmc1: mmc@3400000 { 843 compatible = "nvidia,tegra186-sdhci"; 844 reg = <0x0 0x03400000 0x0 0x10000>; 845 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 847 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 848 clock-names = "sdhci", "tmclk"; 849 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 850 reset-names = "sdhci"; 851 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 852 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 853 interconnect-names = "dma-mem", "write"; 854 iommus = <&smmu TEGRA186_SID_SDMMC1>; 855 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 856 pinctrl-0 = <&sdmmc1_3v3>; 857 pinctrl-1 = <&sdmmc1_1v8>; 858 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 859 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 860 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 861 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 862 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 863 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 864 nvidia,default-tap = <0x5>; 865 nvidia,default-trim = <0xb>; 866 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 867 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 868 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 869 status = "disabled"; 870 }; 871 872 sdmmc2: mmc@3420000 { 873 compatible = "nvidia,tegra186-sdhci"; 874 reg = <0x0 0x03420000 0x0 0x10000>; 875 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 877 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 878 clock-names = "sdhci", "tmclk"; 879 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 880 reset-names = "sdhci"; 881 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 882 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 883 interconnect-names = "dma-mem", "write"; 884 iommus = <&smmu TEGRA186_SID_SDMMC2>; 885 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 886 pinctrl-0 = <&sdmmc2_3v3>; 887 pinctrl-1 = <&sdmmc2_1v8>; 888 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 889 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 890 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 891 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 892 nvidia,default-tap = <0x5>; 893 nvidia,default-trim = <0xb>; 894 status = "disabled"; 895 }; 896 897 sdmmc3: mmc@3440000 { 898 compatible = "nvidia,tegra186-sdhci"; 899 reg = <0x0 0x03440000 0x0 0x10000>; 900 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 902 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 903 clock-names = "sdhci", "tmclk"; 904 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 905 reset-names = "sdhci"; 906 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 907 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 908 interconnect-names = "dma-mem", "write"; 909 iommus = <&smmu TEGRA186_SID_SDMMC3>; 910 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 911 pinctrl-0 = <&sdmmc3_3v3>; 912 pinctrl-1 = <&sdmmc3_1v8>; 913 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 914 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 915 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 916 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 917 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 918 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 919 nvidia,default-tap = <0x5>; 920 nvidia,default-trim = <0xb>; 921 status = "disabled"; 922 }; 923 924 sdmmc4: mmc@3460000 { 925 compatible = "nvidia,tegra186-sdhci"; 926 reg = <0x0 0x03460000 0x0 0x10000>; 927 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 929 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 930 clock-names = "sdhci", "tmclk"; 931 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 932 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 933 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 934 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 935 reset-names = "sdhci"; 936 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 937 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 938 interconnect-names = "dma-mem", "write"; 939 iommus = <&smmu TEGRA186_SID_SDMMC4>; 940 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 941 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 942 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 943 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 944 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 945 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 946 nvidia,default-tap = <0x9>; 947 nvidia,default-trim = <0x5>; 948 nvidia,dqs-trim = <63>; 949 mmc-hs400-1_8v; 950 supports-cqe; 951 status = "disabled"; 952 }; 953 954 hda@3510000 { 955 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 956 reg = <0x0 0x03510000 0x0 0x10000>; 957 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&bpmp TEGRA186_CLK_HDA>, 959 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 960 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 961 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 962 resets = <&bpmp TEGRA186_RESET_HDA>, 963 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 964 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 965 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 966 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 967 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 968 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 969 interconnect-names = "dma-mem", "write"; 970 iommus = <&smmu TEGRA186_SID_HDA>; 971 status = "disabled"; 972 }; 973 974 padctl: padctl@3520000 { 975 compatible = "nvidia,tegra186-xusb-padctl"; 976 reg = <0x0 0x03520000 0x0 0x1000>, 977 <0x0 0x03540000 0x0 0x1000>; 978 reg-names = "padctl", "ao"; 979 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 980 981 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 982 reset-names = "padctl"; 983 984 status = "disabled"; 985 986 pads { 987 usb2 { 988 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 989 clock-names = "trk"; 990 status = "disabled"; 991 992 lanes { 993 usb2-0 { 994 status = "disabled"; 995 #phy-cells = <0>; 996 }; 997 998 usb2-1 { 999 status = "disabled"; 1000 #phy-cells = <0>; 1001 }; 1002 1003 usb2-2 { 1004 status = "disabled"; 1005 #phy-cells = <0>; 1006 }; 1007 }; 1008 }; 1009 1010 hsic { 1011 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1012 clock-names = "trk"; 1013 status = "disabled"; 1014 1015 lanes { 1016 hsic-0 { 1017 status = "disabled"; 1018 #phy-cells = <0>; 1019 }; 1020 }; 1021 }; 1022 1023 usb3 { 1024 status = "disabled"; 1025 1026 lanes { 1027 usb3-0 { 1028 status = "disabled"; 1029 #phy-cells = <0>; 1030 }; 1031 1032 usb3-1 { 1033 status = "disabled"; 1034 #phy-cells = <0>; 1035 }; 1036 1037 usb3-2 { 1038 status = "disabled"; 1039 #phy-cells = <0>; 1040 }; 1041 }; 1042 }; 1043 }; 1044 1045 ports { 1046 usb2-0 { 1047 status = "disabled"; 1048 }; 1049 1050 usb2-1 { 1051 status = "disabled"; 1052 }; 1053 1054 usb2-2 { 1055 status = "disabled"; 1056 }; 1057 1058 hsic-0 { 1059 status = "disabled"; 1060 }; 1061 1062 usb3-0 { 1063 status = "disabled"; 1064 }; 1065 1066 usb3-1 { 1067 status = "disabled"; 1068 }; 1069 1070 usb3-2 { 1071 status = "disabled"; 1072 }; 1073 }; 1074 }; 1075 1076 usb@3530000 { 1077 compatible = "nvidia,tegra186-xusb"; 1078 reg = <0x0 0x03530000 0x0 0x8000>, 1079 <0x0 0x03538000 0x0 0x1000>; 1080 reg-names = "hcd", "fpci"; 1081 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1084 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1085 <&bpmp TEGRA186_CLK_XUSB_SS>, 1086 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1087 <&bpmp TEGRA186_CLK_CLK_M>, 1088 <&bpmp TEGRA186_CLK_XUSB_FS>, 1089 <&bpmp TEGRA186_CLK_PLLU>, 1090 <&bpmp TEGRA186_CLK_CLK_M>, 1091 <&bpmp TEGRA186_CLK_PLLE>; 1092 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1093 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1094 "pll_u_480m", "clk_m", "pll_e"; 1095 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1096 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1097 power-domain-names = "xusb_host", "xusb_ss"; 1098 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1099 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1100 interconnect-names = "dma-mem", "write"; 1101 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 status = "disabled"; 1105 1106 nvidia,xusb-padctl = <&padctl>; 1107 }; 1108 1109 usb@3550000 { 1110 compatible = "nvidia,tegra186-xudc"; 1111 reg = <0x0 0x03550000 0x0 0x8000>, 1112 <0x0 0x03558000 0x0 0x1000>; 1113 reg-names = "base", "fpci"; 1114 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1116 <&bpmp TEGRA186_CLK_XUSB_SS>, 1117 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1118 <&bpmp TEGRA186_CLK_XUSB_FS>; 1119 clock-names = "dev", "ss", "ss_src", "fs_src"; 1120 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1121 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1122 interconnect-names = "dma-mem", "write"; 1123 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1124 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1125 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1126 power-domain-names = "dev", "ss"; 1127 nvidia,xusb-padctl = <&padctl>; 1128 status = "disabled"; 1129 }; 1130 1131 fuse@3820000 { 1132 compatible = "nvidia,tegra186-efuse"; 1133 reg = <0x0 0x03820000 0x0 0x10000>; 1134 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1135 clock-names = "fuse"; 1136 }; 1137 1138 gic: interrupt-controller@3881000 { 1139 compatible = "arm,gic-400"; 1140 #interrupt-cells = <3>; 1141 interrupt-controller; 1142 reg = <0x0 0x03881000 0x0 0x1000>, 1143 <0x0 0x03882000 0x0 0x2000>, 1144 <0x0 0x03884000 0x0 0x2000>, 1145 <0x0 0x03886000 0x0 0x2000>; 1146 interrupts = <GIC_PPI 9 1147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1148 interrupt-parent = <&gic>; 1149 }; 1150 1151 cec@3960000 { 1152 compatible = "nvidia,tegra186-cec"; 1153 reg = <0x0 0x03960000 0x0 0x10000>; 1154 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&bpmp TEGRA186_CLK_CEC>; 1156 clock-names = "cec"; 1157 status = "disabled"; 1158 }; 1159 1160 hsp_top0: hsp@3c00000 { 1161 compatible = "nvidia,tegra186-hsp"; 1162 reg = <0x0 0x03c00000 0x0 0xa0000>; 1163 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1164 interrupt-names = "doorbell"; 1165 #mbox-cells = <2>; 1166 status = "disabled"; 1167 }; 1168 1169 gen2_i2c: i2c@c240000 { 1170 compatible = "nvidia,tegra186-i2c"; 1171 reg = <0x0 0x0c240000 0x0 0x10000>; 1172 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1176 clock-names = "div-clk"; 1177 resets = <&bpmp TEGRA186_RESET_I2C2>; 1178 reset-names = "i2c"; 1179 status = "disabled"; 1180 }; 1181 1182 gen8_i2c: i2c@c250000 { 1183 compatible = "nvidia,tegra186-i2c"; 1184 reg = <0x0 0x0c250000 0x0 0x10000>; 1185 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1189 clock-names = "div-clk"; 1190 resets = <&bpmp TEGRA186_RESET_I2C8>; 1191 reset-names = "i2c"; 1192 status = "disabled"; 1193 }; 1194 1195 uartc: serial@c280000 { 1196 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1197 reg = <0x0 0x0c280000 0x0 0x40>; 1198 reg-shift = <2>; 1199 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1201 clock-names = "serial"; 1202 resets = <&bpmp TEGRA186_RESET_UARTC>; 1203 reset-names = "serial"; 1204 status = "disabled"; 1205 }; 1206 1207 uartg: serial@c290000 { 1208 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1209 reg = <0x0 0x0c290000 0x0 0x40>; 1210 reg-shift = <2>; 1211 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1213 clock-names = "serial"; 1214 resets = <&bpmp TEGRA186_RESET_UARTG>; 1215 reset-names = "serial"; 1216 status = "disabled"; 1217 }; 1218 1219 rtc: rtc@c2a0000 { 1220 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1221 reg = <0 0x0c2a0000 0 0x10000>; 1222 interrupt-parent = <&pmc>; 1223 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1225 clock-names = "rtc"; 1226 status = "disabled"; 1227 }; 1228 1229 gpio_aon: gpio@c2f0000 { 1230 compatible = "nvidia,tegra186-gpio-aon"; 1231 reg-names = "security", "gpio"; 1232 reg = <0x0 0xc2f0000 0x0 0x1000>, 1233 <0x0 0xc2f1000 0x0 0x1000>; 1234 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1235 gpio-controller; 1236 #gpio-cells = <2>; 1237 interrupt-controller; 1238 #interrupt-cells = <2>; 1239 }; 1240 1241 pwm4: pwm@c340000 { 1242 compatible = "nvidia,tegra186-pwm"; 1243 reg = <0x0 0xc340000 0x0 0x10000>; 1244 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1245 clock-names = "pwm"; 1246 resets = <&bpmp TEGRA186_RESET_PWM4>; 1247 reset-names = "pwm"; 1248 status = "disabled"; 1249 #pwm-cells = <2>; 1250 }; 1251 1252 pmc: pmc@c360000 { 1253 compatible = "nvidia,tegra186-pmc"; 1254 reg = <0 0x0c360000 0 0x10000>, 1255 <0 0x0c370000 0 0x10000>, 1256 <0 0x0c380000 0 0x10000>, 1257 <0 0x0c390000 0 0x10000>; 1258 reg-names = "pmc", "wake", "aotag", "scratch"; 1259 1260 #interrupt-cells = <2>; 1261 interrupt-controller; 1262 1263 sdmmc1_3v3: sdmmc1-3v3 { 1264 pins = "sdmmc1-hv"; 1265 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1266 }; 1267 1268 sdmmc1_1v8: sdmmc1-1v8 { 1269 pins = "sdmmc1-hv"; 1270 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1271 }; 1272 1273 sdmmc2_3v3: sdmmc2-3v3 { 1274 pins = "sdmmc2-hv"; 1275 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1276 }; 1277 1278 sdmmc2_1v8: sdmmc2-1v8 { 1279 pins = "sdmmc2-hv"; 1280 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1281 }; 1282 1283 sdmmc3_3v3: sdmmc3-3v3 { 1284 pins = "sdmmc3-hv"; 1285 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1286 }; 1287 1288 sdmmc3_1v8: sdmmc3-1v8 { 1289 pins = "sdmmc3-hv"; 1290 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1291 }; 1292 }; 1293 1294 ccplex@e000000 { 1295 compatible = "nvidia,tegra186-ccplex-cluster"; 1296 reg = <0x0 0x0e000000 0x0 0x400000>; 1297 1298 nvidia,bpmp = <&bpmp>; 1299 }; 1300 1301 pcie@10003000 { 1302 compatible = "nvidia,tegra186-pcie"; 1303 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1304 device_type = "pci"; 1305 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1306 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1307 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1308 reg-names = "pads", "afi", "cs"; 1309 1310 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1311 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1312 interrupt-names = "intr", "msi"; 1313 1314 #interrupt-cells = <1>; 1315 interrupt-map-mask = <0 0 0 0>; 1316 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1317 1318 bus-range = <0x00 0xff>; 1319 #address-cells = <3>; 1320 #size-cells = <2>; 1321 1322 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1323 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1324 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1325 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1326 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1327 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1328 1329 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1330 <&bpmp TEGRA186_CLK_AFI>, 1331 <&bpmp TEGRA186_CLK_PLLE>; 1332 clock-names = "pex", "afi", "pll_e"; 1333 1334 resets = <&bpmp TEGRA186_RESET_PCIE>, 1335 <&bpmp TEGRA186_RESET_AFI>, 1336 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1337 reset-names = "pex", "afi", "pcie_x"; 1338 1339 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1340 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1341 interconnect-names = "dma-mem", "write"; 1342 1343 iommus = <&smmu TEGRA186_SID_AFI>; 1344 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1345 iommu-map-mask = <0x0>; 1346 1347 status = "disabled"; 1348 1349 pci@1,0 { 1350 device_type = "pci"; 1351 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1352 reg = <0x000800 0 0 0 0>; 1353 status = "disabled"; 1354 1355 #address-cells = <3>; 1356 #size-cells = <2>; 1357 ranges; 1358 1359 nvidia,num-lanes = <2>; 1360 }; 1361 1362 pci@2,0 { 1363 device_type = "pci"; 1364 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1365 reg = <0x001000 0 0 0 0>; 1366 status = "disabled"; 1367 1368 #address-cells = <3>; 1369 #size-cells = <2>; 1370 ranges; 1371 1372 nvidia,num-lanes = <1>; 1373 }; 1374 1375 pci@3,0 { 1376 device_type = "pci"; 1377 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1378 reg = <0x001800 0 0 0 0>; 1379 status = "disabled"; 1380 1381 #address-cells = <3>; 1382 #size-cells = <2>; 1383 ranges; 1384 1385 nvidia,num-lanes = <1>; 1386 }; 1387 }; 1388 1389 smmu: iommu@12000000 { 1390 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1391 reg = <0 0x12000000 0 0x800000>; 1392 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1457 stream-match-mask = <0x7f80>; 1458 #global-interrupts = <1>; 1459 #iommu-cells = <1>; 1460 1461 nvidia,memory-controller = <&mc>; 1462 }; 1463 1464 host1x@13e00000 { 1465 compatible = "nvidia,tegra186-host1x"; 1466 reg = <0x0 0x13e00000 0x0 0x10000>, 1467 <0x0 0x13e10000 0x0 0x10000>; 1468 reg-names = "hypervisor", "vm"; 1469 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1471 interrupt-names = "syncpt", "host1x"; 1472 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1473 clock-names = "host1x"; 1474 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1475 reset-names = "host1x"; 1476 1477 #address-cells = <1>; 1478 #size-cells = <1>; 1479 1480 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1481 1482 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1483 interconnect-names = "dma-mem"; 1484 1485 iommus = <&smmu TEGRA186_SID_HOST1X>; 1486 1487 /* Context isolation domains */ 1488 iommu-map = < 1489 0 &smmu TEGRA186_SID_HOST1X_CTX0 1 1490 1 &smmu TEGRA186_SID_HOST1X_CTX1 1 1491 2 &smmu TEGRA186_SID_HOST1X_CTX2 1 1492 3 &smmu TEGRA186_SID_HOST1X_CTX3 1 1493 4 &smmu TEGRA186_SID_HOST1X_CTX4 1 1494 5 &smmu TEGRA186_SID_HOST1X_CTX5 1 1495 6 &smmu TEGRA186_SID_HOST1X_CTX6 1 1496 7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1497 1498 dpaux1: dpaux@15040000 { 1499 compatible = "nvidia,tegra186-dpaux"; 1500 reg = <0x15040000 0x10000>; 1501 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1502 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1503 <&bpmp TEGRA186_CLK_PLLDP>; 1504 clock-names = "dpaux", "parent"; 1505 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1506 reset-names = "dpaux"; 1507 status = "disabled"; 1508 1509 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1510 1511 state_dpaux1_aux: pinmux-aux { 1512 groups = "dpaux-io"; 1513 function = "aux"; 1514 }; 1515 1516 state_dpaux1_i2c: pinmux-i2c { 1517 groups = "dpaux-io"; 1518 function = "i2c"; 1519 }; 1520 1521 state_dpaux1_off: pinmux-off { 1522 groups = "dpaux-io"; 1523 function = "off"; 1524 }; 1525 1526 i2c-bus { 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 }; 1530 }; 1531 1532 display-hub@15200000 { 1533 compatible = "nvidia,tegra186-display"; 1534 reg = <0x15200000 0x00040000>; 1535 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1536 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1537 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1538 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1539 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1540 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1541 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1542 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1543 "wgrp3", "wgrp4", "wgrp5"; 1544 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1545 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1546 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1547 clock-names = "disp", "dsc", "hub"; 1548 status = "disabled"; 1549 1550 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1551 1552 #address-cells = <1>; 1553 #size-cells = <1>; 1554 1555 ranges = <0x15200000 0x15200000 0x40000>; 1556 1557 display@15200000 { 1558 compatible = "nvidia,tegra186-dc"; 1559 reg = <0x15200000 0x10000>; 1560 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1561 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1562 clock-names = "dc"; 1563 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1564 reset-names = "dc"; 1565 1566 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1567 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1568 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1569 interconnect-names = "dma-mem", "read-1"; 1570 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1571 1572 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1573 nvidia,head = <0>; 1574 }; 1575 1576 display@15210000 { 1577 compatible = "nvidia,tegra186-dc"; 1578 reg = <0x15210000 0x10000>; 1579 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1580 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1581 clock-names = "dc"; 1582 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1583 reset-names = "dc"; 1584 1585 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1586 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1587 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1588 interconnect-names = "dma-mem", "read-1"; 1589 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1590 1591 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1592 nvidia,head = <1>; 1593 }; 1594 1595 display@15220000 { 1596 compatible = "nvidia,tegra186-dc"; 1597 reg = <0x15220000 0x10000>; 1598 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1599 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1600 clock-names = "dc"; 1601 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1602 reset-names = "dc"; 1603 1604 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1605 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1606 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1607 interconnect-names = "dma-mem", "read-1"; 1608 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1609 1610 nvidia,outputs = <&sor0 &sor1>; 1611 nvidia,head = <2>; 1612 }; 1613 }; 1614 1615 dsia: dsi@15300000 { 1616 compatible = "nvidia,tegra186-dsi"; 1617 reg = <0x15300000 0x10000>; 1618 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&bpmp TEGRA186_CLK_DSI>, 1620 <&bpmp TEGRA186_CLK_DSIA_LP>, 1621 <&bpmp TEGRA186_CLK_PLLD>; 1622 clock-names = "dsi", "lp", "parent"; 1623 resets = <&bpmp TEGRA186_RESET_DSI>; 1624 reset-names = "dsi"; 1625 status = "disabled"; 1626 1627 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1628 }; 1629 1630 vic@15340000 { 1631 compatible = "nvidia,tegra186-vic"; 1632 reg = <0x15340000 0x40000>; 1633 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1634 clocks = <&bpmp TEGRA186_CLK_VIC>; 1635 clock-names = "vic"; 1636 resets = <&bpmp TEGRA186_RESET_VIC>; 1637 reset-names = "vic"; 1638 1639 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1640 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1641 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1642 interconnect-names = "dma-mem", "write"; 1643 iommus = <&smmu TEGRA186_SID_VIC>; 1644 }; 1645 1646 nvjpg@15380000 { 1647 compatible = "nvidia,tegra186-nvjpg"; 1648 reg = <0x15380000 0x40000>; 1649 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1650 clock-names = "nvjpg"; 1651 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1652 reset-names = "nvjpg"; 1653 1654 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1655 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1656 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1657 interconnect-names = "dma-mem", "write"; 1658 iommus = <&smmu TEGRA186_SID_NVJPG>; 1659 }; 1660 1661 dsib: dsi@15400000 { 1662 compatible = "nvidia,tegra186-dsi"; 1663 reg = <0x15400000 0x10000>; 1664 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1666 <&bpmp TEGRA186_CLK_DSIB_LP>, 1667 <&bpmp TEGRA186_CLK_PLLD>; 1668 clock-names = "dsi", "lp", "parent"; 1669 resets = <&bpmp TEGRA186_RESET_DSIB>; 1670 reset-names = "dsi"; 1671 status = "disabled"; 1672 1673 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1674 }; 1675 1676 nvdec@15480000 { 1677 compatible = "nvidia,tegra186-nvdec"; 1678 reg = <0x15480000 0x40000>; 1679 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1680 clock-names = "nvdec"; 1681 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1682 reset-names = "nvdec"; 1683 1684 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1685 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1686 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1687 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1688 interconnect-names = "dma-mem", "read-1", "write"; 1689 iommus = <&smmu TEGRA186_SID_NVDEC>; 1690 }; 1691 1692 nvenc@154c0000 { 1693 compatible = "nvidia,tegra186-nvenc"; 1694 reg = <0x154c0000 0x40000>; 1695 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1696 clock-names = "nvenc"; 1697 resets = <&bpmp TEGRA186_RESET_NVENC>; 1698 reset-names = "nvenc"; 1699 1700 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1701 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1702 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1703 interconnect-names = "dma-mem", "write"; 1704 iommus = <&smmu TEGRA186_SID_NVENC>; 1705 }; 1706 1707 sor0: sor@15540000 { 1708 compatible = "nvidia,tegra186-sor"; 1709 reg = <0x15540000 0x10000>; 1710 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1711 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1712 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1713 <&bpmp TEGRA186_CLK_PLLD2>, 1714 <&bpmp TEGRA186_CLK_PLLDP>, 1715 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1716 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1717 clock-names = "sor", "out", "parent", "dp", "safe", 1718 "pad"; 1719 resets = <&bpmp TEGRA186_RESET_SOR0>; 1720 reset-names = "sor"; 1721 pinctrl-0 = <&state_dpaux_aux>; 1722 pinctrl-1 = <&state_dpaux_i2c>; 1723 pinctrl-2 = <&state_dpaux_off>; 1724 pinctrl-names = "aux", "i2c", "off"; 1725 status = "disabled"; 1726 1727 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1728 nvidia,interface = <0>; 1729 }; 1730 1731 sor1: sor@15580000 { 1732 compatible = "nvidia,tegra186-sor"; 1733 reg = <0x15580000 0x10000>; 1734 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1735 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1736 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1737 <&bpmp TEGRA186_CLK_PLLD3>, 1738 <&bpmp TEGRA186_CLK_PLLDP>, 1739 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1740 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1741 clock-names = "sor", "out", "parent", "dp", "safe", 1742 "pad"; 1743 resets = <&bpmp TEGRA186_RESET_SOR1>; 1744 reset-names = "sor"; 1745 pinctrl-0 = <&state_dpaux1_aux>; 1746 pinctrl-1 = <&state_dpaux1_i2c>; 1747 pinctrl-2 = <&state_dpaux1_off>; 1748 pinctrl-names = "aux", "i2c", "off"; 1749 status = "disabled"; 1750 1751 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1752 nvidia,interface = <1>; 1753 }; 1754 1755 dpaux: dpaux@155c0000 { 1756 compatible = "nvidia,tegra186-dpaux"; 1757 reg = <0x155c0000 0x10000>; 1758 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1759 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1760 <&bpmp TEGRA186_CLK_PLLDP>; 1761 clock-names = "dpaux", "parent"; 1762 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1763 reset-names = "dpaux"; 1764 status = "disabled"; 1765 1766 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1767 1768 state_dpaux_aux: pinmux-aux { 1769 groups = "dpaux-io"; 1770 function = "aux"; 1771 }; 1772 1773 state_dpaux_i2c: pinmux-i2c { 1774 groups = "dpaux-io"; 1775 function = "i2c"; 1776 }; 1777 1778 state_dpaux_off: pinmux-off { 1779 groups = "dpaux-io"; 1780 function = "off"; 1781 }; 1782 1783 i2c-bus { 1784 #address-cells = <1>; 1785 #size-cells = <0>; 1786 }; 1787 }; 1788 1789 padctl@15880000 { 1790 compatible = "nvidia,tegra186-dsi-padctl"; 1791 reg = <0x15880000 0x10000>; 1792 resets = <&bpmp TEGRA186_RESET_DSI>; 1793 reset-names = "dsi"; 1794 status = "disabled"; 1795 }; 1796 1797 dsic: dsi@15900000 { 1798 compatible = "nvidia,tegra186-dsi"; 1799 reg = <0x15900000 0x10000>; 1800 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1802 <&bpmp TEGRA186_CLK_DSIC_LP>, 1803 <&bpmp TEGRA186_CLK_PLLD>; 1804 clock-names = "dsi", "lp", "parent"; 1805 resets = <&bpmp TEGRA186_RESET_DSIC>; 1806 reset-names = "dsi"; 1807 status = "disabled"; 1808 1809 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1810 }; 1811 1812 dsid: dsi@15940000 { 1813 compatible = "nvidia,tegra186-dsi"; 1814 reg = <0x15940000 0x10000>; 1815 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1816 clocks = <&bpmp TEGRA186_CLK_DSID>, 1817 <&bpmp TEGRA186_CLK_DSID_LP>, 1818 <&bpmp TEGRA186_CLK_PLLD>; 1819 clock-names = "dsi", "lp", "parent"; 1820 resets = <&bpmp TEGRA186_RESET_DSID>; 1821 reset-names = "dsi"; 1822 status = "disabled"; 1823 1824 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1825 }; 1826 }; 1827 1828 gpu@17000000 { 1829 compatible = "nvidia,gp10b"; 1830 reg = <0x0 0x17000000 0x0 0x1000000>, 1831 <0x0 0x18000000 0x0 0x1000000>; 1832 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1834 interrupt-names = "stall", "nonstall"; 1835 1836 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1837 <&bpmp TEGRA186_CLK_GPU>; 1838 clock-names = "gpu", "pwr"; 1839 resets = <&bpmp TEGRA186_RESET_GPU>; 1840 reset-names = "gpu"; 1841 status = "disabled"; 1842 1843 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1844 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1845 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1846 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1847 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1848 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1849 }; 1850 1851 sram@30000000 { 1852 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1853 reg = <0x0 0x30000000 0x0 0x50000>; 1854 #address-cells = <1>; 1855 #size-cells = <1>; 1856 ranges = <0x0 0x0 0x30000000 0x50000>; 1857 no-memory-wc; 1858 1859 cpu_bpmp_tx: sram@4e000 { 1860 reg = <0x4e000 0x1000>; 1861 label = "cpu-bpmp-tx"; 1862 pool; 1863 }; 1864 1865 cpu_bpmp_rx: sram@4f000 { 1866 reg = <0x4f000 0x1000>; 1867 label = "cpu-bpmp-rx"; 1868 pool; 1869 }; 1870 }; 1871 1872 sata@3507000 { 1873 compatible = "nvidia,tegra186-ahci"; 1874 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1875 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1876 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1877 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1878 1879 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1880 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1881 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1882 interconnect-names = "dma-mem", "write"; 1883 iommus = <&smmu TEGRA186_SID_SATA>; 1884 1885 clocks = <&bpmp TEGRA186_CLK_SATA>, 1886 <&bpmp TEGRA186_CLK_SATA_OOB>; 1887 clock-names = "sata", "sata-oob"; 1888 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1889 <&bpmp TEGRA186_CLK_SATA_OOB>; 1890 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1891 <&bpmp TEGRA186_CLK_PLLP>; 1892 assigned-clock-rates = <102000000>, 1893 <204000000>; 1894 resets = <&bpmp TEGRA186_RESET_SATA>, 1895 <&bpmp TEGRA186_RESET_SATACOLD>; 1896 reset-names = "sata", "sata-cold"; 1897 status = "disabled"; 1898 }; 1899 1900 bpmp: bpmp { 1901 compatible = "nvidia,tegra186-bpmp"; 1902 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1903 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1904 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1905 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1906 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1907 iommus = <&smmu TEGRA186_SID_BPMP>; 1908 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1909 TEGRA_HSP_DB_MASTER_BPMP>; 1910 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1911 #clock-cells = <1>; 1912 #reset-cells = <1>; 1913 #power-domain-cells = <1>; 1914 1915 bpmp_i2c: i2c { 1916 compatible = "nvidia,tegra186-bpmp-i2c"; 1917 nvidia,bpmp-bus-id = <5>; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 status = "disabled"; 1921 }; 1922 1923 bpmp_thermal: thermal { 1924 compatible = "nvidia,tegra186-bpmp-thermal"; 1925 #thermal-sensor-cells = <1>; 1926 }; 1927 }; 1928 1929 cpus { 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 1933 denver_0: cpu@0 { 1934 compatible = "nvidia,tegra186-denver"; 1935 device_type = "cpu"; 1936 i-cache-size = <0x20000>; 1937 i-cache-line-size = <64>; 1938 i-cache-sets = <512>; 1939 d-cache-size = <0x10000>; 1940 d-cache-line-size = <64>; 1941 d-cache-sets = <256>; 1942 next-level-cache = <&L2_DENVER>; 1943 reg = <0x000>; 1944 }; 1945 1946 denver_1: cpu@1 { 1947 compatible = "nvidia,tegra186-denver"; 1948 device_type = "cpu"; 1949 i-cache-size = <0x20000>; 1950 i-cache-line-size = <64>; 1951 i-cache-sets = <512>; 1952 d-cache-size = <0x10000>; 1953 d-cache-line-size = <64>; 1954 d-cache-sets = <256>; 1955 next-level-cache = <&L2_DENVER>; 1956 reg = <0x001>; 1957 }; 1958 1959 ca57_0: cpu@2 { 1960 compatible = "arm,cortex-a57"; 1961 device_type = "cpu"; 1962 i-cache-size = <0xC000>; 1963 i-cache-line-size = <64>; 1964 i-cache-sets = <256>; 1965 d-cache-size = <0x8000>; 1966 d-cache-line-size = <64>; 1967 d-cache-sets = <256>; 1968 next-level-cache = <&L2_A57>; 1969 reg = <0x100>; 1970 }; 1971 1972 ca57_1: cpu@3 { 1973 compatible = "arm,cortex-a57"; 1974 device_type = "cpu"; 1975 i-cache-size = <0xC000>; 1976 i-cache-line-size = <64>; 1977 i-cache-sets = <256>; 1978 d-cache-size = <0x8000>; 1979 d-cache-line-size = <64>; 1980 d-cache-sets = <256>; 1981 next-level-cache = <&L2_A57>; 1982 reg = <0x101>; 1983 }; 1984 1985 ca57_2: cpu@4 { 1986 compatible = "arm,cortex-a57"; 1987 device_type = "cpu"; 1988 i-cache-size = <0xC000>; 1989 i-cache-line-size = <64>; 1990 i-cache-sets = <256>; 1991 d-cache-size = <0x8000>; 1992 d-cache-line-size = <64>; 1993 d-cache-sets = <256>; 1994 next-level-cache = <&L2_A57>; 1995 reg = <0x102>; 1996 }; 1997 1998 ca57_3: cpu@5 { 1999 compatible = "arm,cortex-a57"; 2000 device_type = "cpu"; 2001 i-cache-size = <0xC000>; 2002 i-cache-line-size = <64>; 2003 i-cache-sets = <256>; 2004 d-cache-size = <0x8000>; 2005 d-cache-line-size = <64>; 2006 d-cache-sets = <256>; 2007 next-level-cache = <&L2_A57>; 2008 reg = <0x103>; 2009 }; 2010 2011 L2_DENVER: l2-cache0 { 2012 compatible = "cache"; 2013 cache-unified; 2014 cache-level = <2>; 2015 cache-size = <0x200000>; 2016 cache-line-size = <64>; 2017 cache-sets = <2048>; 2018 }; 2019 2020 L2_A57: l2-cache1 { 2021 compatible = "cache"; 2022 cache-unified; 2023 cache-level = <2>; 2024 cache-size = <0x200000>; 2025 cache-line-size = <64>; 2026 cache-sets = <2048>; 2027 }; 2028 }; 2029 2030 pmu_denver { 2031 compatible = "nvidia,denver-pmu"; 2032 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2034 interrupt-affinity = <&denver_0 &denver_1>; 2035 }; 2036 2037 pmu_a57 { 2038 compatible = "arm,cortex-a57-pmu"; 2039 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2043 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2044 }; 2045 2046 sound { 2047 status = "disabled"; 2048 2049 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2050 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2051 clock-names = "pll_a", "plla_out0"; 2052 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2053 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2054 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2055 assigned-clock-parents = <0>, 2056 <&bpmp TEGRA186_CLK_PLLA>, 2057 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2058 /* 2059 * PLLA supports dynamic ramp. Below initial rate is chosen 2060 * for this to work and oscillate between base rates required 2061 * for 8x and 11.025x sample rate streams. 2062 */ 2063 assigned-clock-rates = <258000000>; 2064 2065 iommus = <&smmu TEGRA186_SID_APE>; 2066 }; 2067 2068 thermal-zones { 2069 /* Cortex-A57 cluster */ 2070 cpu-thermal { 2071 polling-delay = <0>; 2072 polling-delay-passive = <1000>; 2073 2074 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2075 2076 trips { 2077 critical { 2078 temperature = <101000>; 2079 hysteresis = <0>; 2080 type = "critical"; 2081 }; 2082 }; 2083 2084 cooling-maps { 2085 }; 2086 }; 2087 2088 /* Denver cluster */ 2089 aux-thermal { 2090 polling-delay = <0>; 2091 polling-delay-passive = <1000>; 2092 2093 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2094 2095 trips { 2096 critical { 2097 temperature = <101000>; 2098 hysteresis = <0>; 2099 type = "critical"; 2100 }; 2101 }; 2102 2103 cooling-maps { 2104 }; 2105 }; 2106 2107 gpu-thermal { 2108 polling-delay = <0>; 2109 polling-delay-passive = <1000>; 2110 2111 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2112 2113 trips { 2114 critical { 2115 temperature = <101000>; 2116 hysteresis = <0>; 2117 type = "critical"; 2118 }; 2119 }; 2120 2121 cooling-maps { 2122 }; 2123 }; 2124 2125 pll-thermal { 2126 polling-delay = <0>; 2127 polling-delay-passive = <1000>; 2128 2129 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2130 2131 trips { 2132 critical { 2133 temperature = <101000>; 2134 hysteresis = <0>; 2135 type = "critical"; 2136 }; 2137 }; 2138 2139 cooling-maps { 2140 }; 2141 }; 2142 2143 ao-thermal { 2144 polling-delay = <0>; 2145 polling-delay-passive = <1000>; 2146 2147 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2148 2149 trips { 2150 critical { 2151 temperature = <101000>; 2152 hysteresis = <0>; 2153 type = "critical"; 2154 }; 2155 }; 2156 2157 cooling-maps { 2158 }; 2159 }; 2160 }; 2161 2162 timer { 2163 compatible = "arm,armv8-timer"; 2164 interrupts = <GIC_PPI 13 2165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2166 <GIC_PPI 14 2167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2168 <GIC_PPI 11 2169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2170 <GIC_PPI 10 2171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2172 interrupt-parent = <&gic>; 2173 always-on; 2174 }; 2175}; 2176