1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * IPQ6018 SoC device tree source
4 *
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11#include <dt-bindings/clock/qcom,apss-ipq.h>
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&intc>;
17
18	clocks {
19		sleep_clk: sleep-clk {
20			compatible = "fixed-clock";
21			clock-frequency = <32000>;
22			#clock-cells = <0>;
23		};
24
25		xo: xo {
26			compatible = "fixed-clock";
27			clock-frequency = <24000000>;
28			#clock-cells = <0>;
29		};
30	};
31
32	cpus: cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35
36		CPU0: cpu@0 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a53";
39			reg = <0x0>;
40			enable-method = "psci";
41			next-level-cache = <&L2_0>;
42			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
43			clock-names = "cpu";
44			operating-points-v2 = <&cpu_opp_table>;
45			cpu-supply = <&ipq6018_s2>;
46		};
47
48		CPU1: cpu@1 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a53";
51			enable-method = "psci";
52			reg = <0x1>;
53			next-level-cache = <&L2_0>;
54			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
55			clock-names = "cpu";
56			operating-points-v2 = <&cpu_opp_table>;
57			cpu-supply = <&ipq6018_s2>;
58		};
59
60		CPU2: cpu@2 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53";
63			enable-method = "psci";
64			reg = <0x2>;
65			next-level-cache = <&L2_0>;
66			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
67			clock-names = "cpu";
68			operating-points-v2 = <&cpu_opp_table>;
69			cpu-supply = <&ipq6018_s2>;
70		};
71
72		CPU3: cpu@3 {
73			device_type = "cpu";
74			compatible = "arm,cortex-a53";
75			enable-method = "psci";
76			reg = <0x3>;
77			next-level-cache = <&L2_0>;
78			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
79			clock-names = "cpu";
80			operating-points-v2 = <&cpu_opp_table>;
81			cpu-supply = <&ipq6018_s2>;
82		};
83
84		L2_0: l2-cache {
85			compatible = "cache";
86			cache-level = <2>;
87			cache-unified;
88		};
89	};
90
91	firmware {
92		scm {
93			compatible = "qcom,scm-ipq6018", "qcom,scm";
94			qcom,dload-mode = <&tcsr 0x6100>;
95		};
96	};
97
98	cpu_opp_table: opp-table-cpu {
99		compatible = "operating-points-v2";
100		opp-shared;
101
102		opp-864000000 {
103			opp-hz = /bits/ 64 <864000000>;
104			opp-microvolt = <725000>;
105			clock-latency-ns = <200000>;
106		};
107
108		opp-1056000000 {
109			opp-hz = /bits/ 64 <1056000000>;
110			opp-microvolt = <787500>;
111			clock-latency-ns = <200000>;
112		};
113
114		opp-1320000000 {
115			opp-hz = /bits/ 64 <1320000000>;
116			opp-microvolt = <862500>;
117			clock-latency-ns = <200000>;
118		};
119
120		opp-1440000000 {
121			opp-hz = /bits/ 64 <1440000000>;
122			opp-microvolt = <925000>;
123			clock-latency-ns = <200000>;
124		};
125
126		opp-1608000000 {
127			opp-hz = /bits/ 64 <1608000000>;
128			opp-microvolt = <987500>;
129			clock-latency-ns = <200000>;
130		};
131
132		opp-1800000000 {
133			opp-hz = /bits/ 64 <1800000000>;
134			opp-microvolt = <1062500>;
135			clock-latency-ns = <200000>;
136		};
137	};
138
139	pmuv8: pmu {
140		compatible = "arm,cortex-a53-pmu";
141		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
142	};
143
144	psci: psci {
145		compatible = "arm,psci-1.0";
146		method = "smc";
147	};
148
149	reserved-memory {
150		#address-cells = <2>;
151		#size-cells = <2>;
152		ranges;
153
154		rpm_msg_ram: memory@60000 {
155			reg = <0x0 0x00060000 0x0 0x6000>;
156			no-map;
157		};
158
159		bootloader@4a100000 {
160			reg = <0x0 0x4a100000 0x0 0x400000>;
161			no-map;
162		};
163
164		sbl@4a500000 {
165			reg = <0x0 0x4a500000 0x0 0x100000>;
166			no-map;
167		};
168
169		tz: memory@4a600000 {
170			reg = <0x0 0x4a600000 0x0 0x400000>;
171			no-map;
172		};
173
174		smem_region: memory@4aa00000 {
175			reg = <0x0 0x4aa00000 0x0 0x100000>;
176			no-map;
177		};
178
179		q6_region: memory@4ab00000 {
180			reg = <0x0 0x4ab00000 0x0 0x5500000>;
181			no-map;
182		};
183	};
184
185	rpm-glink {
186		compatible = "qcom,glink-rpm";
187		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
188		qcom,rpm-msg-ram = <&rpm_msg_ram>;
189		mboxes = <&apcs_glb 0>;
190
191		rpm_requests: rpm-requests {
192			compatible = "qcom,rpm-ipq6018";
193			qcom,glink-channels = "rpm_requests";
194
195			regulators {
196				compatible = "qcom,rpm-mp5496-regulators";
197
198				ipq6018_s2: s2 {
199					regulator-min-microvolt = <725000>;
200					regulator-max-microvolt = <1062500>;
201					regulator-always-on;
202				};
203			};
204		};
205	};
206
207	smem {
208		compatible = "qcom,smem";
209		memory-region = <&smem_region>;
210		hwlocks = <&tcsr_mutex 0>;
211	};
212
213	soc: soc@0 {
214		#address-cells = <2>;
215		#size-cells = <2>;
216		ranges = <0 0 0 0 0x0 0xffffffff>;
217		dma-ranges;
218		compatible = "simple-bus";
219
220		qusb_phy_1: qusb@59000 {
221			compatible = "qcom,ipq6018-qusb2-phy";
222			reg = <0x0 0x00059000 0x0 0x180>;
223			#phy-cells = <0>;
224
225			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
226				 <&xo>;
227			clock-names = "cfg_ahb", "ref";
228
229			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
230			status = "disabled";
231		};
232
233		ssphy_0: ssphy@78000 {
234			compatible = "qcom,ipq6018-qmp-usb3-phy";
235			reg = <0x0 0x00078000 0x0 0x1c4>;
236			#address-cells = <2>;
237			#size-cells = <2>;
238			ranges;
239
240			clocks = <&gcc GCC_USB0_AUX_CLK>,
241				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
242			clock-names = "aux", "cfg_ahb", "ref";
243
244			resets = <&gcc GCC_USB0_PHY_BCR>,
245				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
246			reset-names = "phy","common";
247			status = "disabled";
248
249			usb0_ssphy: phy@78200 {
250				reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
251				      <0x0 0x00078400 0x0 0x200>, /* Rx */
252				      <0x0 0x00078800 0x0 0x1f8>, /* PCS */
253				      <0x0 0x00078600 0x0 0x044>; /* PCS misc */
254				#phy-cells = <0>;
255				#clock-cells = <0>;
256				clocks = <&gcc GCC_USB0_PIPE_CLK>;
257				clock-names = "pipe0";
258				clock-output-names = "gcc_usb0_pipe_clk_src";
259			};
260		};
261
262		qusb_phy_0: qusb@79000 {
263			compatible = "qcom,ipq6018-qusb2-phy";
264			reg = <0x0 0x00079000 0x0 0x180>;
265			#phy-cells = <0>;
266
267			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
268				<&xo>;
269			clock-names = "cfg_ahb", "ref";
270
271			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
272			status = "disabled";
273		};
274
275		pcie_phy: phy@84000 {
276			compatible = "qcom,ipq6018-qmp-pcie-phy";
277			reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
278			status = "disabled";
279			#address-cells = <2>;
280			#size-cells = <2>;
281			ranges;
282
283			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
284				<&gcc GCC_PCIE0_AHB_CLK>;
285			clock-names = "aux", "cfg_ahb";
286
287			resets = <&gcc GCC_PCIE0_PHY_BCR>,
288				<&gcc GCC_PCIE0PHY_PHY_BCR>;
289			reset-names = "phy",
290				      "common";
291
292			pcie_phy0: phy@84200 {
293				reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
294				      <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
295				      <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
296				      <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
297				#phy-cells = <0>;
298
299				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
300				clock-names = "pipe0";
301				clock-output-names = "gcc_pcie0_pipe_clk_src";
302				#clock-cells = <0>;
303			};
304		};
305
306		mdio: mdio@90000 {
307			#address-cells = <1>;
308			#size-cells = <0>;
309			compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
310			reg = <0x0 0x00090000 0x0 0x64>;
311			clocks = <&gcc GCC_MDIO_AHB_CLK>;
312			clock-names = "gcc_mdio_ahb_clk";
313			status = "disabled";
314		};
315
316		qfprom: efuse@a4000 {
317			compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
318			reg = <0x0 0x000a4000 0x0 0x2000>;
319			#address-cells = <1>;
320			#size-cells = <1>;
321		};
322
323		prng: qrng@e3000 {
324			compatible = "qcom,prng-ee";
325			reg = <0x0 0x000e3000 0x0 0x1000>;
326			clocks = <&gcc GCC_PRNG_AHB_CLK>;
327			clock-names = "core";
328		};
329
330		cryptobam: dma-controller@704000 {
331			compatible = "qcom,bam-v1.7.0";
332			reg = <0x0 0x00704000 0x0 0x20000>;
333			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
334			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
335			clock-names = "bam_clk";
336			#dma-cells = <1>;
337			qcom,ee = <1>;
338			qcom,controlled-remotely;
339		};
340
341		crypto: crypto@73a000 {
342			compatible = "qcom,crypto-v5.1";
343			reg = <0x0 0x0073a000 0x0 0x6000>;
344			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
345				 <&gcc GCC_CRYPTO_AXI_CLK>,
346				 <&gcc GCC_CRYPTO_CLK>;
347			clock-names = "iface", "bus", "core";
348			dmas = <&cryptobam 2>, <&cryptobam 3>;
349			dma-names = "rx", "tx";
350		};
351
352		tlmm: pinctrl@1000000 {
353			compatible = "qcom,ipq6018-pinctrl";
354			reg = <0x0 0x01000000 0x0 0x300000>;
355			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
356			gpio-controller;
357			#gpio-cells = <2>;
358			gpio-ranges = <&tlmm 0 0 80>;
359			interrupt-controller;
360			#interrupt-cells = <2>;
361
362			serial_3_pins: serial3-state {
363				pins = "gpio44", "gpio45";
364				function = "blsp2_uart";
365				drive-strength = <8>;
366				bias-pull-down;
367			};
368
369			qpic_pins: qpic-state {
370				pins = "gpio1", "gpio3", "gpio4",
371					"gpio5", "gpio6", "gpio7",
372					"gpio8", "gpio10", "gpio11",
373					"gpio12", "gpio13", "gpio14",
374					"gpio15", "gpio17";
375				function = "qpic_pad";
376				drive-strength = <8>;
377				bias-disable;
378			};
379		};
380
381		gcc: gcc@1800000 {
382			compatible = "qcom,gcc-ipq6018";
383			reg = <0x0 0x01800000 0x0 0x80000>;
384			clocks = <&xo>, <&sleep_clk>;
385			clock-names = "xo", "sleep_clk";
386			#clock-cells = <1>;
387			#reset-cells = <1>;
388		};
389
390		tcsr_mutex: hwlock@1905000 {
391			compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
392			reg = <0x0 0x01905000 0x0 0x1000>;
393			#hwlock-cells = <1>;
394		};
395
396		tcsr: syscon@1937000 {
397			compatible = "qcom,tcsr-ipq6018", "syscon";
398			reg = <0x0 0x01937000 0x0 0x21000>;
399		};
400
401		usb2: usb@70f8800 {
402			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
403			reg = <0x0 0x070f8800 0x0 0x400>;
404			#address-cells = <2>;
405			#size-cells = <2>;
406			ranges;
407			clocks = <&gcc GCC_USB1_MASTER_CLK>,
408				 <&gcc GCC_USB1_SLEEP_CLK>,
409				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
410			clock-names = "core",
411				      "sleep",
412				      "mock_utmi";
413
414			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
415					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
416			assigned-clock-rates = <133330000>,
417					       <24000000>;
418			resets = <&gcc GCC_USB1_BCR>;
419			status = "disabled";
420
421			dwc_1: usb@7000000 {
422				compatible = "snps,dwc3";
423				reg = <0x0 0x07000000 0x0 0xcd00>;
424				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
425				phys = <&qusb_phy_1>;
426				phy-names = "usb2-phy";
427				tx-fifo-resize;
428				snps,is-utmi-l1-suspend;
429				snps,hird-threshold = /bits/ 8 <0x0>;
430				snps,dis_u2_susphy_quirk;
431				snps,dis_u3_susphy_quirk;
432				dr_mode = "host";
433			};
434		};
435
436		blsp_dma: dma-controller@7884000 {
437			compatible = "qcom,bam-v1.7.0";
438			reg = <0x0 0x07884000 0x0 0x2b000>;
439			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
440			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
441			clock-names = "bam_clk";
442			#dma-cells = <1>;
443			qcom,ee = <0>;
444		};
445
446		blsp1_uart3: serial@78b1000 {
447			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
448			reg = <0x0 0x078b1000 0x0 0x200>;
449			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
450			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
451				 <&gcc GCC_BLSP1_AHB_CLK>;
452			clock-names = "core", "iface";
453			status = "disabled";
454		};
455
456		blsp1_spi1: spi@78b5000 {
457			compatible = "qcom,spi-qup-v2.2.1";
458			#address-cells = <1>;
459			#size-cells = <0>;
460			reg = <0x0 0x078b5000 0x0 0x600>;
461			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
462			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
463				 <&gcc GCC_BLSP1_AHB_CLK>;
464			clock-names = "core", "iface";
465			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
466			dma-names = "tx", "rx";
467			status = "disabled";
468		};
469
470		blsp1_spi2: spi@78b6000 {
471			compatible = "qcom,spi-qup-v2.2.1";
472			#address-cells = <1>;
473			#size-cells = <0>;
474			reg = <0x0 0x078b6000 0x0 0x600>;
475			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
476			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
477				 <&gcc GCC_BLSP1_AHB_CLK>;
478			clock-names = "core", "iface";
479			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
480			dma-names = "tx", "rx";
481			status = "disabled";
482		};
483
484		blsp1_i2c2: i2c@78b6000 {
485			compatible = "qcom,i2c-qup-v2.2.1";
486			#address-cells = <1>;
487			#size-cells = <0>;
488			reg = <0x0 0x078b6000 0x0 0x600>;
489			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
490			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
491				 <&gcc GCC_BLSP1_AHB_CLK>;
492			clock-names = "core", "iface";
493			clock-frequency = <400000>;
494			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
495			dma-names = "tx", "rx";
496			status = "disabled";
497		};
498
499		blsp1_i2c3: i2c@78b7000 {
500			compatible = "qcom,i2c-qup-v2.2.1";
501			#address-cells = <1>;
502			#size-cells = <0>;
503			reg = <0x0 0x078b7000 0x0 0x600>;
504			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
505			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
506				 <&gcc GCC_BLSP1_AHB_CLK>;
507			clock-names = "core", "iface";
508			clock-frequency = <400000>;
509			dmas = <&blsp_dma 16>, <&blsp_dma 17>;
510			dma-names = "tx", "rx";
511			status = "disabled";
512		};
513
514		qpic_bam: dma-controller@7984000 {
515			compatible = "qcom,bam-v1.7.0";
516			reg = <0x0 0x07984000 0x0 0x1a000>;
517			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
518			clocks = <&gcc GCC_QPIC_AHB_CLK>;
519			clock-names = "bam_clk";
520			#dma-cells = <1>;
521			qcom,ee = <0>;
522			status = "disabled";
523		};
524
525		qpic_nand: nand-controller@79b0000 {
526			compatible = "qcom,ipq6018-nand";
527			reg = <0x0 0x079b0000 0x0 0x10000>;
528			#address-cells = <1>;
529			#size-cells = <0>;
530			clocks = <&gcc GCC_QPIC_CLK>,
531				 <&gcc GCC_QPIC_AHB_CLK>;
532			clock-names = "core", "aon";
533
534			dmas = <&qpic_bam 0>,
535			       <&qpic_bam 1>,
536			       <&qpic_bam 2>;
537			dma-names = "tx", "rx", "cmd";
538			pinctrl-0 = <&qpic_pins>;
539			pinctrl-names = "default";
540			status = "disabled";
541		};
542
543		usb3: usb@8af8800 {
544			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
545			reg = <0x0 0x08af8800 0x0 0x400>;
546			#address-cells = <2>;
547			#size-cells = <2>;
548			ranges;
549
550			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
551				<&gcc GCC_USB0_MASTER_CLK>,
552				<&gcc GCC_USB0_SLEEP_CLK>,
553				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
554			clock-names = "cfg_noc",
555				"core",
556				"sleep",
557				"mock_utmi";
558
559			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
560					  <&gcc GCC_USB0_MASTER_CLK>,
561					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
562			assigned-clock-rates = <133330000>,
563					       <133330000>,
564					       <20000000>;
565
566			resets = <&gcc GCC_USB0_BCR>;
567			status = "disabled";
568
569			dwc_0: usb@8a00000 {
570				compatible = "snps,dwc3";
571				reg = <0x0 0x08a00000 0x0 0xcd00>;
572				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
573				phys = <&qusb_phy_0>, <&usb0_ssphy>;
574				phy-names = "usb2-phy", "usb3-phy";
575				clocks = <&xo>;
576				clock-names = "ref";
577				tx-fifo-resize;
578				snps,is-utmi-l1-suspend;
579				snps,hird-threshold = /bits/ 8 <0x0>;
580				snps,dis_u2_susphy_quirk;
581				snps,dis_u3_susphy_quirk;
582				dr_mode = "host";
583			};
584		};
585
586		intc: interrupt-controller@b000000 {
587			compatible = "qcom,msm-qgic2";
588			#address-cells = <2>;
589			#size-cells = <2>;
590			interrupt-controller;
591			#interrupt-cells = <3>;
592			reg = <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
593			      <0x0 0x0b002000 0x0 0x1000>,  /*GICC*/
594			      <0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
595			      <0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
596			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
597			ranges = <0 0 0 0xb00a000 0 0xffd>;
598
599			v2m@0 {
600				compatible = "arm,gic-v2m-frame";
601				msi-controller;
602				reg = <0x0 0x0 0x0 0xffd>;
603			};
604		};
605
606		watchdog@b017000 {
607			compatible = "qcom,kpss-wdt";
608			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
609			reg = <0x0 0x0b017000 0x0 0x40>;
610			clocks = <&sleep_clk>;
611			timeout-sec = <10>;
612		};
613
614		apcs_glb: mailbox@b111000 {
615			compatible = "qcom,ipq6018-apcs-apps-global";
616			reg = <0x0 0x0b111000 0x0 0x1000>;
617			#clock-cells = <1>;
618			clocks = <&a53pll>, <&xo>;
619			clock-names = "pll", "xo";
620			#mbox-cells = <1>;
621		};
622
623		a53pll: clock@b116000 {
624			compatible = "qcom,ipq6018-a53pll";
625			reg = <0x0 0x0b116000 0x0 0x40>;
626			#clock-cells = <0>;
627			clocks = <&xo>;
628			clock-names = "xo";
629		};
630
631		timer@b120000 {
632			#address-cells = <1>;
633			#size-cells = <1>;
634			ranges = <0 0 0 0x10000000>;
635			compatible = "arm,armv7-timer-mem";
636			reg = <0x0 0x0b120000 0x0 0x1000>;
637
638			frame@b120000 {
639				frame-number = <0>;
640				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
641					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
642				reg = <0x0b121000 0x1000>,
643				      <0x0b122000 0x1000>;
644			};
645
646			frame@b123000 {
647				frame-number = <1>;
648				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
649				reg = <0x0b123000 0x1000>;
650				status = "disabled";
651			};
652
653			frame@b124000 {
654				frame-number = <2>;
655				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
656				reg = <0x0b124000 0x1000>;
657				status = "disabled";
658			};
659
660			frame@b125000 {
661				frame-number = <3>;
662				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
663				reg = <0x0b125000 0x1000>;
664				status = "disabled";
665			};
666
667			frame@b126000 {
668				frame-number = <4>;
669				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
670				reg = <0x0b126000 0x1000>;
671				status = "disabled";
672			};
673
674			frame@b127000 {
675				frame-number = <5>;
676				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
677				reg = <0x0b127000 0x1000>;
678				status = "disabled";
679			};
680
681			frame@b128000 {
682				frame-number = <6>;
683				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
684				reg = <0x0b128000 0x1000>;
685				status = "disabled";
686			};
687		};
688
689		q6v5_wcss: remoteproc@cd00000 {
690			compatible = "qcom,ipq6018-wcss-pil";
691			reg = <0x0 0x0cd00000 0x0 0x4040>,
692			      <0x0 0x004ab000 0x0 0x20>;
693			reg-names = "qdsp6",
694				    "rmb";
695			interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
696					      <&wcss_smp2p_in 0 0>,
697					      <&wcss_smp2p_in 1 0>,
698					      <&wcss_smp2p_in 2 0>,
699					      <&wcss_smp2p_in 3 0>;
700			interrupt-names = "wdog",
701					  "fatal",
702					  "ready",
703					  "handover",
704					  "stop-ack";
705
706			resets = <&gcc GCC_WCSSAON_RESET>,
707				 <&gcc GCC_WCSS_BCR>,
708				 <&gcc GCC_WCSS_Q6_BCR>;
709
710			reset-names = "wcss_aon_reset",
711				      "wcss_reset",
712				      "wcss_q6_reset";
713
714			clocks = <&gcc GCC_PRNG_AHB_CLK>;
715			clock-names = "prng";
716
717			qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
718
719			qcom,smem-states = <&wcss_smp2p_out 0>,
720					   <&wcss_smp2p_out 1>;
721			qcom,smem-state-names = "shutdown",
722						"stop";
723
724			memory-region = <&q6_region>;
725
726			glink-edge {
727				interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
728				label = "rtr";
729				qcom,remote-pid = <1>;
730				mboxes = <&apcs_glb 8>;
731
732				qrtr_requests {
733					qcom,glink-channels = "IPCRTR";
734				};
735			};
736		};
737
738		pcie0: pci@20000000 {
739			compatible = "qcom,pcie-ipq6018";
740			reg = <0x0 0x20000000 0x0 0xf1d>,
741			      <0x0 0x20000f20 0x0 0xa8>,
742			      <0x0 0x20001000 0x0 0x1000>,
743			      <0x0 0x80000 0x0 0x4000>,
744			      <0x0 0x20100000 0x0 0x1000>;
745			reg-names = "dbi", "elbi", "atu", "parf", "config";
746
747			device_type = "pci";
748			linux,pci-domain = <0>;
749			bus-range = <0x00 0xff>;
750			num-lanes = <1>;
751			max-link-speed = <3>;
752			#address-cells = <3>;
753			#size-cells = <2>;
754
755			phys = <&pcie_phy0>;
756			phy-names = "pciephy";
757
758			ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
759				 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
760
761			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
762			interrupt-names = "msi";
763
764			#interrupt-cells = <1>;
765			interrupt-map-mask = <0 0 0 0x7>;
766			interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
767					<0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
768					<0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
769					<0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
770
771			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
772				 <&gcc GCC_PCIE0_AXI_M_CLK>,
773				 <&gcc GCC_PCIE0_AXI_S_CLK>,
774				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
775				 <&gcc PCIE0_RCHNG_CLK>;
776			clock-names = "iface",
777				      "axi_m",
778				      "axi_s",
779				      "axi_bridge",
780				      "rchng";
781
782			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
783				 <&gcc GCC_PCIE0_SLEEP_ARES>,
784				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
785				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
786				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
787				 <&gcc GCC_PCIE0_AHB_ARES>,
788				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
789				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
790			reset-names = "pipe",
791				      "sleep",
792				      "sticky",
793				      "axi_m",
794				      "axi_s",
795				      "ahb",
796				      "axi_m_sticky",
797				      "axi_s_sticky";
798
799			status = "disabled";
800		};
801	};
802
803	timer {
804		compatible = "arm,armv8-timer";
805		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
806			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
807			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
808			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
809	};
810
811	wcss: wcss-smp2p {
812		compatible = "qcom,smp2p";
813		qcom,smem = <435>, <428>;
814
815		interrupt-parent = <&intc>;
816		interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
817
818		mboxes = <&apcs_glb 9>;
819
820		qcom,local-pid = <0>;
821		qcom,remote-pid = <1>;
822
823		wcss_smp2p_out: master-kernel {
824			qcom,entry-name = "master-kernel";
825			#qcom,smem-state-cells = <1>;
826		};
827
828		wcss_smp2p_in: slave-kernel {
829			qcom,entry-name = "slave-kernel";
830			interrupt-controller;
831			#interrupt-cells = <2>;
832		};
833	};
834};
835