1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8994.h>
7#include <dt-bindings/power/qcom-rpmpd.h>
8
9/ {
10	interrupt-parent = <&intc>;
11
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	chosen { };
16
17	clocks {
18		xo_board: xo-board {
19			compatible = "fixed-clock";
20			#clock-cells = <0>;
21			clock-frequency = <19200000>;
22			clock-output-names = "xo_board";
23		};
24
25		sleep_clk: sleep-clk {
26			compatible = "fixed-clock";
27			#clock-cells = <0>;
28			clock-frequency = <32768>;
29			clock-output-names = "sleep_clk";
30		};
31	};
32
33	cpus {
34		#address-cells = <2>;
35		#size-cells = <0>;
36
37		CPU0: cpu@0 {
38			device_type = "cpu";
39			compatible = "arm,cortex-a53";
40			reg = <0x0 0x0>;
41			enable-method = "psci";
42			next-level-cache = <&L2_0>;
43			L2_0: l2-cache {
44				compatible = "cache";
45				cache-level = <2>;
46			};
47		};
48
49		CPU1: cpu@1 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53";
52			reg = <0x0 0x1>;
53			enable-method = "psci";
54			next-level-cache = <&L2_0>;
55		};
56
57		CPU2: cpu@2 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53";
60			reg = <0x0 0x2>;
61			enable-method = "psci";
62			next-level-cache = <&L2_0>;
63		};
64
65		CPU3: cpu@3 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53";
68			reg = <0x0 0x3>;
69			enable-method = "psci";
70			next-level-cache = <&L2_0>;
71		};
72
73		CPU4: cpu@100 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a57";
76			reg = <0x0 0x100>;
77			enable-method = "psci";
78			next-level-cache = <&L2_1>;
79			L2_1: l2-cache {
80				compatible = "cache";
81				cache-level = <2>;
82			};
83		};
84
85		CPU5: cpu@101 {
86			device_type = "cpu";
87			compatible = "arm,cortex-a57";
88			reg = <0x0 0x101>;
89			enable-method = "psci";
90			next-level-cache = <&L2_1>;
91		};
92
93		CPU6: cpu@102 {
94			device_type = "cpu";
95			compatible = "arm,cortex-a57";
96			reg = <0x0 0x101>;
97			enable-method = "psci";
98			next-level-cache = <&L2_1>;
99		};
100
101		CPU7: cpu@103 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a57";
104			reg = <0x0 0x101>;
105			enable-method = "psci";
106			next-level-cache = <&L2_1>;
107		};
108
109		cpu-map {
110			cluster0 {
111				core0 {
112					cpu = <&CPU0>;
113				};
114
115				core1 {
116					cpu = <&CPU1>;
117				};
118
119				core2 {
120					cpu = <&CPU2>;
121				};
122
123				core3 {
124					cpu = <&CPU3>;
125				};
126			};
127
128			cluster1 {
129				core0 {
130					cpu = <&CPU4>;
131				};
132
133				core1 {
134					cpu = <&CPU5>;
135				};
136
137				cpu6_map: core2 {
138					cpu = <&CPU6>;
139				};
140
141				cpu7_map: core3 {
142					cpu = <&CPU7>;
143				};
144			};
145		};
146	};
147
148	firmware {
149		scm {
150			compatible = "qcom,scm-msm8994", "qcom,scm";
151		};
152	};
153
154	memory@80000000 {
155		device_type = "memory";
156		/* We expect the bootloader to fill in the reg */
157		reg = <0 0x80000000 0 0>;
158	};
159
160	tcsr_mutex: hwlock {
161		compatible = "qcom,tcsr-mutex";
162		syscon = <&tcsr_mutex_regs 0 0x80>;
163		#hwlock-cells = <1>;
164	};
165
166	pmu {
167		compatible = "arm,cortex-a53-pmu";
168		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
169	};
170
171	psci {
172		compatible = "arm,psci-0.2";
173		method = "hvc";
174	};
175
176	reserved-memory {
177		#address-cells = <2>;
178		#size-cells = <2>;
179		ranges;
180
181		dfps_data_mem: dfps_data_mem@3400000 {
182			reg = <0 0x03400000 0 0x1000>;
183			no-map;
184		};
185
186		cont_splash_mem: memory@3800000 {
187			reg = <0 0x03800000 0 0x2400000>;
188			no-map;
189		};
190
191		smem_mem: smem_region@6a00000 {
192			reg = <0 0x06a00000 0 0x200000>;
193			no-map;
194		};
195
196		mpss_mem: memory@7000000 {
197			reg = <0 0x07000000 0 0x5a00000>;
198			no-map;
199		};
200
201		peripheral_region: memory@ca00000 {
202			reg = <0 0x0ca00000 0 0x1f00000>;
203			no-map;
204		};
205
206		rmtfs_mem: memory@c6400000 {
207			compatible = "qcom,rmtfs-mem";
208			reg = <0 0xc6400000 0 0x180000>;
209			no-map;
210
211			qcom,client-id = <1>;
212		};
213
214		mba_mem: memory@c6700000 {
215			reg = <0 0xc6700000 0 0x100000>;
216			no-map;
217		};
218
219		audio_mem: memory@c7000000 {
220			reg = <0 0xc7000000 0 0x800000>;
221			no-map;
222		};
223
224		adsp_mem: memory@c9400000 {
225			reg = <0 0xc9400000 0 0x3f00000>;
226			no-map;
227		};
228	};
229
230	smd {
231		compatible = "qcom,smd";
232		rpm {
233			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
234			qcom,ipc = <&apcs 8 0>;
235			qcom,smd-edge = <15>;
236			qcom,local-pid = <0>;
237			qcom,remote-pid = <6>;
238
239			rpm_requests: rpm-requests {
240				compatible = "qcom,rpm-msm8994";
241				qcom,smd-channels = "rpm_requests";
242
243				rpmcc: rpmcc {
244					compatible = "qcom,rpmcc-msm8994";
245					#clock-cells = <1>;
246				};
247
248				rpmpd: power-controller {
249					compatible = "qcom,msm8994-rpmpd";
250					#power-domain-cells = <1>;
251					operating-points-v2 = <&rpmpd_opp_table>;
252
253					rpmpd_opp_table: opp-table {
254						compatible = "operating-points-v2";
255
256						rpmpd_opp_ret: opp1 {
257							opp-level = <1>;
258						};
259						rpmpd_opp_svs_krait: opp2 {
260							opp-level = <2>;
261						};
262						rpmpd_opp_svs_soc: opp3 {
263							opp-level = <3>;
264						};
265						rpmpd_opp_nom: opp4 {
266							opp-level = <4>;
267						};
268						rpmpd_opp_turbo: opp5 {
269							opp-level = <5>;
270						};
271						rpmpd_opp_super_turbo: opp6 {
272							opp-level = <6>;
273						};
274					};
275				};
276			};
277		};
278	};
279
280	smem {
281		compatible = "qcom,smem";
282		memory-region = <&smem_mem>;
283		qcom,rpm-msg-ram = <&rpm_msg_ram>;
284		hwlocks = <&tcsr_mutex 3>;
285	};
286
287	smp2p-lpass {
288		compatible = "qcom,smp2p";
289		qcom,smem = <443>, <429>;
290
291		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
292
293		qcom,ipc = <&apcs 8 10>;
294
295		qcom,local-pid = <0>;
296		qcom,remote-pid = <2>;
297
298		adsp_smp2p_out: master-kernel {
299			qcom,entry-name = "master-kernel";
300			#qcom,smem-state-cells = <1>;
301		};
302
303		adsp_smp2p_in: slave-kernel {
304			qcom,entry-name = "slave-kernel";
305
306			interrupt-controller;
307			#interrupt-cells = <2>;
308		};
309	};
310
311	smp2p-modem {
312		compatible = "qcom,smp2p";
313		qcom,smem = <435>, <428>;
314
315		interrupt-parent = <&intc>;
316		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
317
318		qcom,ipc = <&apcs 8 14>;
319
320		qcom,local-pid = <0>;
321		qcom,remote-pid = <1>;
322
323		modem_smp2p_out: master-kernel {
324			qcom,entry-name = "master-kernel";
325			#qcom,smem-state-cells = <1>;
326		};
327
328		modem_smp2p_in: slave-kernel {
329			qcom,entry-name = "slave-kernel";
330
331			interrupt-controller;
332			#interrupt-cells = <2>;
333		};
334	};
335
336	soc: soc {
337
338		#address-cells = <1>;
339		#size-cells = <1>;
340		ranges = <0 0 0 0xffffffff>;
341		compatible = "simple-bus";
342
343		intc: interrupt-controller@f9000000 {
344			compatible = "qcom,msm-qgic2";
345			interrupt-controller;
346			#interrupt-cells = <3>;
347			reg = <0xf9000000 0x1000>,
348			      <0xf9002000 0x1000>;
349		};
350
351		apcs: mailbox@f900d000 {
352			compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
353			reg = <0xf900d000 0x2000>;
354			#mbox-cells = <1>;
355		};
356
357		timer@f9020000 {
358			#address-cells = <1>;
359			#size-cells = <1>;
360			ranges;
361			compatible = "arm,armv7-timer-mem";
362			reg = <0xf9020000 0x1000>;
363
364			frame@f9021000 {
365				frame-number = <0>;
366				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
367					     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
368				reg = <0xf9021000 0x1000>,
369				      <0xf9022000 0x1000>;
370			};
371
372			frame@f9023000 {
373				frame-number = <1>;
374				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
375				reg = <0xf9023000 0x1000>;
376				status = "disabled";
377			};
378
379			frame@f9024000 {
380				frame-number = <2>;
381				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
382				reg = <0xf9024000 0x1000>;
383				status = "disabled";
384			};
385
386			frame@f9025000 {
387				frame-number = <3>;
388				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
389				reg = <0xf9025000 0x1000>;
390				status = "disabled";
391			};
392
393			frame@f9026000 {
394				frame-number = <4>;
395				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
396				reg = <0xf9026000 0x1000>;
397				status = "disabled";
398			};
399
400			frame@f9027000 {
401				frame-number = <5>;
402				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
403				reg = <0xf9027000 0x1000>;
404				status = "disabled";
405			};
406
407			frame@f9028000 {
408				frame-number = <6>;
409				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
410				reg = <0xf9028000 0x1000>;
411				status = "disabled";
412			};
413		};
414
415		usb3: usb@f92f8800 {
416			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
417			reg = <0xf92f8800 0x400>;
418			#address-cells = <1>;
419			#size-cells = <1>;
420			ranges;
421
422			clocks = <&gcc GCC_USB30_MASTER_CLK>,
423				 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
424				 <&gcc GCC_USB30_SLEEP_CLK>,
425				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
426			clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
427
428			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
429					  <&gcc GCC_USB30_MASTER_CLK>;
430			assigned-clock-rates = <19200000>, <120000000>;
431
432			power-domains = <&gcc USB30_GDSC>;
433			qcom,select-utmi-as-pipe-clk;
434
435			usb@f9200000 {
436				compatible = "snps,dwc3";
437				reg = <0xf9200000 0xcc00>;
438				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
439				snps,dis_u2_susphy_quirk;
440				snps,dis_enblslpm_quirk;
441				maximum-speed = "high-speed";
442				dr_mode = "peripheral";
443			};
444		};
445
446		sdhc1: sdhci@f9824900 {
447			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
448			reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
449			reg-names = "hc_mem", "core_mem";
450
451			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
452				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
453			interrupt-names = "hc_irq", "pwr_irq";
454
455			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
456			         <&gcc GCC_SDCC1_AHB_CLK>,
457				 <&xo_board>;
458			clock-names = "core", "iface", "xo";
459
460			pinctrl-names = "default", "sleep";
461			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
462			pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
463
464			bus-width = <8>;
465			non-removable;
466			status = "disabled";
467		};
468
469		sdhc2: sdhci@f98a4900 {
470			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
471			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
472			reg-names = "hc_mem", "core_mem";
473
474			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
475				<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
476			interrupt-names = "hc_irq", "pwr_irq";
477
478			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
479				<&gcc GCC_SDCC2_AHB_CLK>,
480				<&xo_board>;
481			clock-names = "core", "iface", "xo";
482
483			pinctrl-names = "default", "sleep";
484			pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
485			pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
486
487			cd-gpios = <&tlmm 100 0>;
488			bus-width = <4>;
489			status = "disabled";
490		};
491
492		blsp1_dma: dma-controller@f9904000 {
493			compatible = "qcom,bam-v1.7.0";
494			reg = <0xf9904000 0x19000>;
495			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
496			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
497			clock-names = "bam_clk";
498			#dma-cells = <1>;
499			qcom,ee = <0>;
500			qcom,controlled-remotely;
501			num-channels = <18>;
502			qcom,num-ees = <4>;
503		};
504
505		blsp1_uart2: serial@f991e000 {
506			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
507			reg = <0xf991e000 0x1000>;
508			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
509			clock-names = "core", "iface";
510			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
511				 <&gcc GCC_BLSP1_AHB_CLK>;
512			pinctrl-names = "default", "sleep";
513			pinctrl-0 = <&blsp1_uart2_default>;
514			pinctrl-1 = <&blsp1_uart2_sleep>;
515			status = "disabled";
516		};
517
518		blsp1_i2c1: i2c@f9923000 {
519			compatible = "qcom,i2c-qup-v2.2.1";
520			reg = <0xf9923000 0x500>;
521			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
522			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
523						<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
524			clock-names = "iface", "core";
525			clock-frequency = <400000>;
526			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
527			dma-names = "tx", "rx";
528			pinctrl-names = "default", "sleep";
529			pinctrl-0 = <&i2c1_default>;
530			pinctrl-1 = <&i2c1_sleep>;
531			#address-cells = <1>;
532			#size-cells = <0>;
533			status = "disabled";
534		};
535
536		blsp1_spi1: spi@f9923000 {
537			compatible = "qcom,spi-qup-v2.2.1";
538			reg = <0xf9923000 0x500>;
539			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
540			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
541				 <&gcc GCC_BLSP1_AHB_CLK>;
542			clock-names = "core", "iface";
543			spi-max-frequency = <19200000>;
544			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
545			dma-names = "tx", "rx";
546			pinctrl-names = "default", "sleep";
547			pinctrl-0 = <&blsp1_spi1_default>;
548			pinctrl-1 = <&blsp1_spi1_sleep>;
549			#address-cells = <1>;
550			#size-cells = <0>;
551			status = "disabled";
552		};
553
554		blsp1_i2c2: i2c@f9924000 {
555			compatible = "qcom,i2c-qup-v2.2.1";
556			reg = <0xf9924000 0x500>;
557			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
558			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
559						<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
560			clock-names = "iface", "core";
561			clock-frequency = <400000>;
562			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
563			dma-names = "tx", "rx";
564			pinctrl-names = "default", "sleep";
565			pinctrl-0 = <&i2c2_default>;
566			pinctrl-1 = <&i2c2_sleep>;
567			#address-cells = <1>;
568			#size-cells = <0>;
569			status = "disabled";
570		};
571
572		/* I2C3 doesn't exist */
573
574		blsp1_i2c4: i2c@f9926000 {
575			compatible = "qcom,i2c-qup-v2.2.1";
576			reg = <0xf9926000 0x500>;
577			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
578			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
579						<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
580			clock-names = "iface", "core";
581			clock-frequency = <400000>;
582			dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
583			dma-names = "tx", "rx";
584			pinctrl-names = "default", "sleep";
585			pinctrl-0 = <&i2c4_default>;
586			pinctrl-1 = <&i2c4_sleep>;
587			#address-cells = <1>;
588			#size-cells = <0>;
589			status = "disabled";
590		};
591
592		blsp1_i2c5: i2c@f9927000 {
593			compatible = "qcom,i2c-qup-v2.2.1";
594			reg = <0xf9927000 0x500>;
595			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
596			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
597						<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
598			clock-names = "iface", "core";
599			clock-frequency = <400000>;
600			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
601			dma-names = "tx", "rx";
602			pinctrl-names = "default", "sleep";
603			pinctrl-0 = <&i2c5_default>;
604			pinctrl-1 = <&i2c5_sleep>;
605			#address-cells = <1>;
606			#size-cells = <0>;
607			status = "disabled";
608		};
609
610		blsp1_i2c6: i2c@f9928000 {
611			compatible = "qcom,i2c-qup-v2.2.1";
612			reg = <0xf9928000 0x500>;
613			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
614			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
615						<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
616			clock-names = "iface", "core";
617			clock-frequency = <400000>;
618			dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
619			dma-names = "tx", "rx";
620			pinctrl-names = "default", "sleep";
621			pinctrl-0 = <&i2c6_default>;
622			pinctrl-1 = <&i2c6_sleep>;
623			#address-cells = <1>;
624			#size-cells = <0>;
625			status = "disabled";
626		};
627
628		blsp2_dma: dma-controller@f9944000 {
629			compatible = "qcom,bam-v1.7.0";
630			reg = <0xf9944000 0x19000>;
631			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
632			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
633			clock-names = "bam_clk";
634			#dma-cells = <1>;
635			qcom,ee = <0>;
636			qcom,controlled-remotely;
637			num-channels = <18>;
638			qcom,num-ees = <4>;
639		};
640
641		blsp2_uart2: serial@f995e000 {
642			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
643			reg = <0xf995e000 0x1000>;
644			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
645			clock-names = "core", "iface";
646			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
647					<&gcc GCC_BLSP2_AHB_CLK>;
648			dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
649			dma-names = "tx", "rx";
650			pinctrl-names = "default", "sleep";
651			pinctrl-0 = <&blsp2_uart2_default>;
652			pinctrl-1 = <&blsp2_uart2_sleep>;
653			status = "disabled";
654		};
655
656		blsp2_i2c1: i2c@f9963000 {
657			compatible = "qcom,i2c-qup-v2.2.1";
658			reg = <0xf9963000 0x500>;
659			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
660			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
661					<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
662			clock-names = "iface", "core";
663			clock-frequency = <400000>;
664			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
665			dma-names = "tx", "rx";
666			pinctrl-names = "default", "sleep";
667			pinctrl-0 = <&i2c7_default>;
668			pinctrl-1 = <&i2c7_sleep>;
669			#address-cells = <1>;
670			#size-cells = <0>;
671			status = "disabled";
672		};
673
674		blsp2_spi4: spi@f9966000 {
675			compatible = "qcom,spi-qup-v2.2.1";
676			reg = <0xf9966000 0x500>;
677			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
678			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
679				 <&gcc GCC_BLSP2_AHB_CLK>;
680			clock-names = "core", "iface";
681			spi-max-frequency = <19200000>;
682			dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
683			dma-names = "tx", "rx";
684			pinctrl-names = "default", "sleep";
685			pinctrl-0 = <&blsp2_spi10_default>;
686			pinctrl-1 = <&blsp2_spi10_sleep>;
687			#address-cells = <1>;
688			#size-cells = <0>;
689			status = "disabled";
690		};
691
692		blsp2_i2c5: i2c@f9967000 {
693			compatible = "qcom,i2c-qup-v2.2.1";
694			reg = <0xf9967000 0x500>;
695			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
696			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
697						<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
698			clock-names = "iface", "core";
699			clock-frequency = <355000>;
700			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
701			dma-names = "tx", "rx";
702			pinctrl-names = "default", "sleep";
703			pinctrl-0 = <&i2c11_default>;
704			pinctrl-1 = <&i2c11_sleep>;
705			#address-cells = <1>;
706			#size-cells = <0>;
707			status = "disabled";
708		};
709
710		gcc: clock-controller@fc400000 {
711			compatible = "qcom,gcc-msm8994";
712			#clock-cells = <1>;
713			#reset-cells = <1>;
714			#power-domain-cells = <1>;
715			reg = <0xfc400000 0x2000>;
716
717			clock-names = "xo", "sleep_clk";
718			clocks = <&xo_board>, <&sleep_clk>;
719		};
720
721		rpm_msg_ram: sram@fc428000 {
722			compatible = "qcom,rpm-msg-ram";
723			reg = <0xfc428000 0x4000>;
724		};
725
726		restart@fc4ab000 {
727			compatible = "qcom,pshold";
728			reg = <0xfc4ab000 0x4>;
729		};
730
731		spmi_bus: spmi@fc4c0000 {
732			compatible = "qcom,spmi-pmic-arb";
733			reg = <0xfc4cf000 0x1000>,
734			      <0xfc4cb000 0x1000>,
735			      <0xfc4ca000 0x1000>;
736			reg-names = "core", "intr", "cnfg";
737			interrupt-names = "periph_irq";
738			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
739			qcom,ee = <0>;
740			qcom,channel = <0>;
741			#address-cells = <2>;
742			#size-cells = <0>;
743			interrupt-controller;
744			#interrupt-cells = <4>;
745		};
746
747		tcsr_mutex_regs: syscon@fd484000 {
748			compatible = "syscon";
749			reg = <0xfd484000 0x2000>;
750		};
751
752		tlmm: pinctrl@fd510000 {
753			compatible = "qcom,msm8994-pinctrl";
754			reg = <0xfd510000 0x4000>;
755			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
756			gpio-controller;
757			gpio-ranges = <&tlmm 0 0 146>;
758			#gpio-cells = <2>;
759			interrupt-controller;
760			#interrupt-cells = <2>;
761
762			blsp1_uart2_default: blsp1-uart2-default {
763				function = "blsp_uart2";
764				pins = "gpio4", "gpio5";
765				drive-strength = <16>;
766				bias-disable;
767			};
768
769			blsp1_uart2_sleep: blsp1-uart2-sleep {
770				function = "gpio";
771				pins = "gpio4", "gpio5";
772				drive-strength = <2>;
773				bias-pull-down;
774			};
775
776			blsp2_uart2_default: blsp2-uart2-default {
777				function = "blsp_uart8";
778				pins = "gpio45", "gpio46",
779						"gpio47", "gpio48";
780				drive-strength = <16>;
781				bias-disable;
782			};
783
784			blsp2_uart2_sleep: blsp2-uart2-sleep {
785				function = "gpio";
786				pins = "gpio45", "gpio46",
787						"gpio47", "gpio48";
788				drive-strength = <2>;
789				bias-disable;
790			};
791
792			i2c1_default: i2c1-default {
793				function = "blsp_i2c1";
794				pins = "gpio2", "gpio3";
795				drive-strength = <2>;
796				bias-disable;
797			};
798
799			i2c1_sleep: i2c1-sleep {
800				function = "gpio";
801				pins = "gpio2", "gpio3";
802				drive-strength = <2>;
803				bias-disable;
804			};
805
806			i2c2_default: i2c2-default {
807				function = "blsp_i2c2";
808				pins = "gpio6", "gpio7";
809				drive-strength = <2>;
810				bias-disable;
811			};
812
813			i2c2_sleep: i2c2-sleep {
814				function = "gpio";
815				pins = "gpio6", "gpio7";
816				drive-strength = <2>;
817				bias-disable;
818			};
819
820			i2c4_default: i2c4-default {
821				function = "blsp_i2c4";
822				pins = "gpio19", "gpio20";
823				drive-strength = <2>;
824				bias-disable;
825			};
826
827			i2c4_sleep: i2c4-sleep {
828				function = "gpio";
829				pins = "gpio19", "gpio20";
830				drive-strength = <2>;
831				bias-pull-down;
832				input-enable;
833			};
834
835			i2c5_default: i2c5-default {
836				function = "blsp_i2c5";
837				pins = "gpio23", "gpio24";
838				drive-strength = <2>;
839				bias-disable;
840			};
841
842			i2c5_sleep: i2c5-sleep {
843				function = "gpio";
844				pins = "gpio23", "gpio24";
845				drive-strength = <2>;
846				bias-disable;
847			};
848
849			i2c6_default: i2c6-default {
850				function = "blsp_i2c6";
851				pins = "gpio28", "gpio27";
852				drive-strength = <2>;
853				bias-disable;
854			};
855
856			i2c6_sleep: i2c6-sleep {
857				function = "gpio";
858				pins = "gpio28", "gpio27";
859				drive-strength = <2>;
860				bias-disable;
861			};
862
863			i2c7_default: i2c7-default {
864				function = "blsp_i2c7";
865				pins = "gpio44", "gpio43";
866				drive-strength = <2>;
867				bias-disable;
868			};
869
870			i2c7_sleep: i2c7-sleep {
871				function = "gpio";
872				pins = "gpio44", "gpio43";
873				drive-strength = <2>;
874				bias-disable;
875			};
876
877			blsp2_spi10_default: blsp2-spi10-default {
878				default {
879					function = "blsp_spi10";
880					pins = "gpio53", "gpio54", "gpio55";
881					drive-strength = <10>;
882					bias-pull-down;
883				};
884				cs {
885					function = "gpio";
886					pins = "gpio55";
887					drive-strength = <2>;
888					bias-disable;
889				};
890			};
891
892			blsp2_spi10_sleep: blsp2-spi10-sleep {
893				pins = "gpio53", "gpio54", "gpio55";
894				drive-strength = <2>;
895				bias-disable;
896			};
897
898			i2c11_default: i2c11-default {
899				function = "blsp_i2c11";
900				pins = "gpio83", "gpio84";
901				drive-strength = <2>;
902				bias-disable;
903			};
904
905			i2c11_sleep: i2c11-sleep {
906				function = "gpio";
907				pins = "gpio83", "gpio84";
908				drive-strength = <2>;
909				bias-disable;
910			};
911
912			blsp1_spi1_default: blsp1-spi1-default {
913				default {
914					function = "blsp_spi1";
915					pins = "gpio0", "gpio1", "gpio3";
916					drive-strength = <10>;
917					bias-pull-down;
918				};
919				cs {
920					function = "gpio";
921					pins = "gpio8";
922					drive-strength = <2>;
923					bias-disable;
924				};
925			};
926
927			blsp1_spi1_sleep: blsp1-spi1-sleep {
928				pins = "gpio0", "gpio1", "gpio3";
929				drive-strength = <2>;
930				bias-disable;
931			};
932
933			sdc1_clk_on: clk-on {
934				pins = "sdc1_clk";
935				bias-disable;
936				drive-strength = <16>;
937			};
938
939			sdc1_clk_off: clk-off {
940				pins = "sdc1_clk";
941				bias-disable;
942				drive-strength = <2>;
943			};
944
945			sdc1_cmd_on: cmd-on {
946				pins = "sdc1_cmd";
947				bias-pull-up;
948				drive-strength = <8>;
949			};
950
951			sdc1_cmd_off: cmd-off {
952				pins = "sdc1_cmd";
953				bias-pull-up;
954				drive-strength = <2>;
955			};
956
957			sdc1_data_on: data-on {
958				pins = "sdc1_data";
959				bias-pull-up;
960				drive-strength = <8>;
961			};
962
963			sdc1_data_off: data-off {
964				pins = "sdc1_data";
965				bias-pull-up;
966				drive-strength = <2>;
967			};
968
969			sdc1_rclk_on: rclk-on {
970				pins = "sdc1_rclk";
971				bias-pull-down;
972			};
973
974			sdc1_rclk_off: rclk-off {
975				pins = "sdc1_rclk";
976				bias-pull-down;
977			};
978
979			sdc2_clk_on: sdc2-clk-on {
980				pins = "sdc2_clk";
981				bias-disable;
982				drive-strength = <10>;
983			};
984
985			sdc2_clk_off: sdc2-clk-off {
986				pins = "sdc2_clk";
987				bias-disable;
988				drive-strength = <2>;
989			};
990
991			sdc2_cmd_on: sdc2-cmd-on {
992				pins = "sdc2_cmd";
993				bias-pull-up;
994				drive-strength = <10>;
995			};
996
997			sdc2_cmd_off: sdc2-cmd-off {
998				pins = "sdc2_cmd";
999				bias-pull-up;
1000				drive-strength = <2>;
1001			};
1002
1003			sdc2_data_on: sdc2-data-on {
1004				pins = "sdc2_data";
1005				bias-pull-up;
1006				drive-strength = <10>;
1007			};
1008
1009			sdc2_data_off: sdc2-data-off {
1010				pins = "sdc2_data";
1011				bias-pull-up;
1012				drive-strength = <2>;
1013			};
1014		};
1015	};
1016
1017	timer: timer {
1018		compatible = "arm,armv8-timer";
1019		interrupts = <GIC_PPI 2 0xff08>,
1020			     <GIC_PPI 3 0xff08>,
1021			     <GIC_PPI 4 0xff08>,
1022			     <GIC_PPI 1 0xff08>;
1023	};
1024
1025	vph_pwr: vph-pwr-regulator {
1026		compatible = "regulator-fixed";
1027		regulator-name = "vph_pwr";
1028
1029		regulator-min-microvolt = <3600000>;
1030		regulator-max-microvolt = <3600000>;
1031
1032		regulator-always-on;
1033	};
1034};
1035
1036