1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8998.h>
6#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	interrupt-parent = <&intc>;
14
15	qcom,msm-id = <292 0x0>;
16
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	chosen { };
21
22	memory@80000000 {
23		device_type = "memory";
24		/* We expect the bootloader to fill in the reg */
25		reg = <0x0 0x80000000 0x0 0x0>;
26	};
27
28	reserved-memory {
29		#address-cells = <2>;
30		#size-cells = <2>;
31		ranges;
32
33		hyp_mem: memory@85800000 {
34			reg = <0x0 0x85800000 0x0 0x600000>;
35			no-map;
36		};
37
38		xbl_mem: memory@85e00000 {
39			reg = <0x0 0x85e00000 0x0 0x100000>;
40			no-map;
41		};
42
43		smem_mem: smem-mem@86000000 {
44			reg = <0x0 0x86000000 0x0 0x200000>;
45			no-map;
46		};
47
48		tz_mem: memory@86200000 {
49			reg = <0x0 0x86200000 0x0 0x2d00000>;
50			no-map;
51		};
52
53		rmtfs_mem: memory@88f00000 {
54			compatible = "qcom,rmtfs-mem";
55			reg = <0x0 0x88f00000 0x0 0x200000>;
56			no-map;
57
58			qcom,client-id = <1>;
59			qcom,vmid = <15>;
60		};
61
62		spss_mem: memory@8ab00000 {
63			reg = <0x0 0x8ab00000 0x0 0x700000>;
64			no-map;
65		};
66
67		adsp_mem: memory@8b200000 {
68			reg = <0x0 0x8b200000 0x0 0x1a00000>;
69			no-map;
70		};
71
72		mpss_mem: memory@8cc00000 {
73			reg = <0x0 0x8cc00000 0x0 0x7000000>;
74			no-map;
75		};
76
77		venus_mem: memory@93c00000 {
78			reg = <0x0 0x93c00000 0x0 0x500000>;
79			no-map;
80		};
81
82		mba_mem: memory@94100000 {
83			reg = <0x0 0x94100000 0x0 0x200000>;
84			no-map;
85		};
86
87		slpi_mem: memory@94300000 {
88			reg = <0x0 0x94300000 0x0 0xf00000>;
89			no-map;
90		};
91
92		ipa_fw_mem: memory@95200000 {
93			reg = <0x0 0x95200000 0x0 0x10000>;
94			no-map;
95		};
96
97		ipa_gsi_mem: memory@95210000 {
98			reg = <0x0 0x95210000 0x0 0x5000>;
99			no-map;
100		};
101
102		gpu_mem: memory@95600000 {
103			reg = <0x0 0x95600000 0x0 0x100000>;
104			no-map;
105		};
106
107		wlan_msa_mem: memory@95700000 {
108			reg = <0x0 0x95700000 0x0 0x100000>;
109			no-map;
110		};
111
112		mdata_mem: mpss-metadata {
113			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
114			size = <0x0 0x4000>;
115			no-map;
116		};
117	};
118
119	clocks {
120		xo: xo-board {
121			compatible = "fixed-clock";
122			#clock-cells = <0>;
123			clock-frequency = <19200000>;
124			clock-output-names = "xo_board";
125		};
126
127		sleep_clk: sleep-clk {
128			compatible = "fixed-clock";
129			#clock-cells = <0>;
130			clock-frequency = <32764>;
131		};
132	};
133
134	cpus {
135		#address-cells = <2>;
136		#size-cells = <0>;
137
138		CPU0: cpu@0 {
139			device_type = "cpu";
140			compatible = "qcom,kryo280";
141			reg = <0x0 0x0>;
142			enable-method = "psci";
143			capacity-dmips-mhz = <1024>;
144			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
145			next-level-cache = <&L2_0>;
146			L2_0: l2-cache {
147				compatible = "cache";
148				cache-level = <2>;
149				cache-unified;
150			};
151		};
152
153		CPU1: cpu@1 {
154			device_type = "cpu";
155			compatible = "qcom,kryo280";
156			reg = <0x0 0x1>;
157			enable-method = "psci";
158			capacity-dmips-mhz = <1024>;
159			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
160			next-level-cache = <&L2_0>;
161		};
162
163		CPU2: cpu@2 {
164			device_type = "cpu";
165			compatible = "qcom,kryo280";
166			reg = <0x0 0x2>;
167			enable-method = "psci";
168			capacity-dmips-mhz = <1024>;
169			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
170			next-level-cache = <&L2_0>;
171		};
172
173		CPU3: cpu@3 {
174			device_type = "cpu";
175			compatible = "qcom,kryo280";
176			reg = <0x0 0x3>;
177			enable-method = "psci";
178			capacity-dmips-mhz = <1024>;
179			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
180			next-level-cache = <&L2_0>;
181		};
182
183		CPU4: cpu@100 {
184			device_type = "cpu";
185			compatible = "qcom,kryo280";
186			reg = <0x0 0x100>;
187			enable-method = "psci";
188			capacity-dmips-mhz = <1536>;
189			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
190			next-level-cache = <&L2_1>;
191			L2_1: l2-cache {
192				compatible = "cache";
193				cache-level = <2>;
194				cache-unified;
195			};
196		};
197
198		CPU5: cpu@101 {
199			device_type = "cpu";
200			compatible = "qcom,kryo280";
201			reg = <0x0 0x101>;
202			enable-method = "psci";
203			capacity-dmips-mhz = <1536>;
204			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
205			next-level-cache = <&L2_1>;
206		};
207
208		CPU6: cpu@102 {
209			device_type = "cpu";
210			compatible = "qcom,kryo280";
211			reg = <0x0 0x102>;
212			enable-method = "psci";
213			capacity-dmips-mhz = <1536>;
214			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
215			next-level-cache = <&L2_1>;
216		};
217
218		CPU7: cpu@103 {
219			device_type = "cpu";
220			compatible = "qcom,kryo280";
221			reg = <0x0 0x103>;
222			enable-method = "psci";
223			capacity-dmips-mhz = <1536>;
224			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
225			next-level-cache = <&L2_1>;
226		};
227
228		cpu-map {
229			cluster0 {
230				core0 {
231					cpu = <&CPU0>;
232				};
233
234				core1 {
235					cpu = <&CPU1>;
236				};
237
238				core2 {
239					cpu = <&CPU2>;
240				};
241
242				core3 {
243					cpu = <&CPU3>;
244				};
245			};
246
247			cluster1 {
248				core0 {
249					cpu = <&CPU4>;
250				};
251
252				core1 {
253					cpu = <&CPU5>;
254				};
255
256				core2 {
257					cpu = <&CPU6>;
258				};
259
260				core3 {
261					cpu = <&CPU7>;
262				};
263			};
264		};
265
266		idle-states {
267			entry-method = "psci";
268
269			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
270				compatible = "arm,idle-state";
271				idle-state-name = "little-retention";
272				/* CPU Retention (C2D), L2 Active */
273				arm,psci-suspend-param = <0x00000002>;
274				entry-latency-us = <81>;
275				exit-latency-us = <86>;
276				min-residency-us = <504>;
277			};
278
279			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
280				compatible = "arm,idle-state";
281				idle-state-name = "little-power-collapse";
282				/* CPU + L2 Power Collapse (C3, D4) */
283				arm,psci-suspend-param = <0x40000003>;
284				entry-latency-us = <814>;
285				exit-latency-us = <4562>;
286				min-residency-us = <9183>;
287				local-timer-stop;
288			};
289
290			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
291				compatible = "arm,idle-state";
292				idle-state-name = "big-retention";
293				/* CPU Retention (C2D), L2 Active */
294				arm,psci-suspend-param = <0x00000002>;
295				entry-latency-us = <79>;
296				exit-latency-us = <82>;
297				min-residency-us = <1302>;
298			};
299
300			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
301				compatible = "arm,idle-state";
302				idle-state-name = "big-power-collapse";
303				/* CPU + L2 Power Collapse (C3, D4) */
304				arm,psci-suspend-param = <0x40000003>;
305				entry-latency-us = <724>;
306				exit-latency-us = <2027>;
307				min-residency-us = <9419>;
308				local-timer-stop;
309			};
310		};
311	};
312
313	firmware {
314		scm {
315			compatible = "qcom,scm-msm8998", "qcom,scm";
316		};
317	};
318
319	psci {
320		compatible = "arm,psci-1.0";
321		method = "smc";
322	};
323
324	rpm-glink {
325		compatible = "qcom,glink-rpm";
326
327		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
328		qcom,rpm-msg-ram = <&rpm_msg_ram>;
329		mboxes = <&apcs_glb 0>;
330
331		rpm_requests: rpm-requests {
332			compatible = "qcom,rpm-msm8998";
333			qcom,glink-channels = "rpm_requests";
334
335			rpmcc: clock-controller {
336				compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
337				#clock-cells = <1>;
338			};
339
340			rpmpd: power-controller {
341				compatible = "qcom,msm8998-rpmpd";
342				#power-domain-cells = <1>;
343				operating-points-v2 = <&rpmpd_opp_table>;
344
345				rpmpd_opp_table: opp-table {
346					compatible = "operating-points-v2";
347
348					rpmpd_opp_ret: opp1 {
349						opp-level = <RPM_SMD_LEVEL_RETENTION>;
350					};
351
352					rpmpd_opp_ret_plus: opp2 {
353						opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
354					};
355
356					rpmpd_opp_min_svs: opp3 {
357						opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
358					};
359
360					rpmpd_opp_low_svs: opp4 {
361						opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
362					};
363
364					rpmpd_opp_svs: opp5 {
365						opp-level = <RPM_SMD_LEVEL_SVS>;
366					};
367
368					rpmpd_opp_svs_plus: opp6 {
369						opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
370					};
371
372					rpmpd_opp_nom: opp7 {
373						opp-level = <RPM_SMD_LEVEL_NOM>;
374					};
375
376					rpmpd_opp_nom_plus: opp8 {
377						opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
378					};
379
380					rpmpd_opp_turbo: opp9 {
381						opp-level = <RPM_SMD_LEVEL_TURBO>;
382					};
383
384					rpmpd_opp_turbo_plus: opp10 {
385						opp-level = <RPM_SMD_LEVEL_BINNING>;
386					};
387				};
388			};
389		};
390	};
391
392	smem {
393		compatible = "qcom,smem";
394		memory-region = <&smem_mem>;
395		hwlocks = <&tcsr_mutex 3>;
396	};
397
398	smp2p-lpass {
399		compatible = "qcom,smp2p";
400		qcom,smem = <443>, <429>;
401
402		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
403
404		mboxes = <&apcs_glb 10>;
405
406		qcom,local-pid = <0>;
407		qcom,remote-pid = <2>;
408
409		adsp_smp2p_out: master-kernel {
410			qcom,entry-name = "master-kernel";
411			#qcom,smem-state-cells = <1>;
412		};
413
414		adsp_smp2p_in: slave-kernel {
415			qcom,entry-name = "slave-kernel";
416
417			interrupt-controller;
418			#interrupt-cells = <2>;
419		};
420	};
421
422	smp2p-mpss {
423		compatible = "qcom,smp2p";
424		qcom,smem = <435>, <428>;
425		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
426		mboxes = <&apcs_glb 14>;
427		qcom,local-pid = <0>;
428		qcom,remote-pid = <1>;
429
430		modem_smp2p_out: master-kernel {
431			qcom,entry-name = "master-kernel";
432			#qcom,smem-state-cells = <1>;
433		};
434
435		modem_smp2p_in: slave-kernel {
436			qcom,entry-name = "slave-kernel";
437			interrupt-controller;
438			#interrupt-cells = <2>;
439		};
440	};
441
442	smp2p-slpi {
443		compatible = "qcom,smp2p";
444		qcom,smem = <481>, <430>;
445		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
446		mboxes = <&apcs_glb 26>;
447		qcom,local-pid = <0>;
448		qcom,remote-pid = <3>;
449
450		slpi_smp2p_out: master-kernel {
451			qcom,entry-name = "master-kernel";
452			#qcom,smem-state-cells = <1>;
453		};
454
455		slpi_smp2p_in: slave-kernel {
456			qcom,entry-name = "slave-kernel";
457			interrupt-controller;
458			#interrupt-cells = <2>;
459		};
460	};
461
462	thermal-zones {
463		cpu0-thermal {
464			polling-delay-passive = <250>;
465			polling-delay = <1000>;
466
467			thermal-sensors = <&tsens0 1>;
468
469			trips {
470				cpu0_alert0: trip-point0 {
471					temperature = <75000>;
472					hysteresis = <2000>;
473					type = "passive";
474				};
475
476				cpu0_crit: cpu-crit {
477					temperature = <110000>;
478					hysteresis = <2000>;
479					type = "critical";
480				};
481			};
482		};
483
484		cpu1-thermal {
485			polling-delay-passive = <250>;
486			polling-delay = <1000>;
487
488			thermal-sensors = <&tsens0 2>;
489
490			trips {
491				cpu1_alert0: trip-point0 {
492					temperature = <75000>;
493					hysteresis = <2000>;
494					type = "passive";
495				};
496
497				cpu1_crit: cpu-crit {
498					temperature = <110000>;
499					hysteresis = <2000>;
500					type = "critical";
501				};
502			};
503		};
504
505		cpu2-thermal {
506			polling-delay-passive = <250>;
507			polling-delay = <1000>;
508
509			thermal-sensors = <&tsens0 3>;
510
511			trips {
512				cpu2_alert0: trip-point0 {
513					temperature = <75000>;
514					hysteresis = <2000>;
515					type = "passive";
516				};
517
518				cpu2_crit: cpu-crit {
519					temperature = <110000>;
520					hysteresis = <2000>;
521					type = "critical";
522				};
523			};
524		};
525
526		cpu3-thermal {
527			polling-delay-passive = <250>;
528			polling-delay = <1000>;
529
530			thermal-sensors = <&tsens0 4>;
531
532			trips {
533				cpu3_alert0: trip-point0 {
534					temperature = <75000>;
535					hysteresis = <2000>;
536					type = "passive";
537				};
538
539				cpu3_crit: cpu-crit {
540					temperature = <110000>;
541					hysteresis = <2000>;
542					type = "critical";
543				};
544			};
545		};
546
547		cpu4-thermal {
548			polling-delay-passive = <250>;
549			polling-delay = <1000>;
550
551			thermal-sensors = <&tsens0 7>;
552
553			trips {
554				cpu4_alert0: trip-point0 {
555					temperature = <75000>;
556					hysteresis = <2000>;
557					type = "passive";
558				};
559
560				cpu4_crit: cpu-crit {
561					temperature = <110000>;
562					hysteresis = <2000>;
563					type = "critical";
564				};
565			};
566		};
567
568		cpu5-thermal {
569			polling-delay-passive = <250>;
570			polling-delay = <1000>;
571
572			thermal-sensors = <&tsens0 8>;
573
574			trips {
575				cpu5_alert0: trip-point0 {
576					temperature = <75000>;
577					hysteresis = <2000>;
578					type = "passive";
579				};
580
581				cpu5_crit: cpu-crit {
582					temperature = <110000>;
583					hysteresis = <2000>;
584					type = "critical";
585				};
586			};
587		};
588
589		cpu6-thermal {
590			polling-delay-passive = <250>;
591			polling-delay = <1000>;
592
593			thermal-sensors = <&tsens0 9>;
594
595			trips {
596				cpu6_alert0: trip-point0 {
597					temperature = <75000>;
598					hysteresis = <2000>;
599					type = "passive";
600				};
601
602				cpu6_crit: cpu-crit {
603					temperature = <110000>;
604					hysteresis = <2000>;
605					type = "critical";
606				};
607			};
608		};
609
610		cpu7-thermal {
611			polling-delay-passive = <250>;
612			polling-delay = <1000>;
613
614			thermal-sensors = <&tsens0 10>;
615
616			trips {
617				cpu7_alert0: trip-point0 {
618					temperature = <75000>;
619					hysteresis = <2000>;
620					type = "passive";
621				};
622
623				cpu7_crit: cpu-crit {
624					temperature = <110000>;
625					hysteresis = <2000>;
626					type = "critical";
627				};
628			};
629		};
630
631		gpu-bottom-thermal {
632			polling-delay-passive = <250>;
633			polling-delay = <1000>;
634
635			thermal-sensors = <&tsens0 12>;
636
637			trips {
638				gpu1_alert0: trip-point0 {
639					temperature = <90000>;
640					hysteresis = <2000>;
641					type = "hot";
642				};
643			};
644		};
645
646		gpu-top-thermal {
647			polling-delay-passive = <250>;
648			polling-delay = <1000>;
649
650			thermal-sensors = <&tsens0 13>;
651
652			trips {
653				gpu2_alert0: trip-point0 {
654					temperature = <90000>;
655					hysteresis = <2000>;
656					type = "hot";
657				};
658			};
659		};
660
661		clust0-mhm-thermal {
662			polling-delay-passive = <250>;
663			polling-delay = <1000>;
664
665			thermal-sensors = <&tsens0 5>;
666
667			trips {
668				cluster0_mhm_alert0: trip-point0 {
669					temperature = <90000>;
670					hysteresis = <2000>;
671					type = "hot";
672				};
673			};
674		};
675
676		clust1-mhm-thermal {
677			polling-delay-passive = <250>;
678			polling-delay = <1000>;
679
680			thermal-sensors = <&tsens0 6>;
681
682			trips {
683				cluster1_mhm_alert0: trip-point0 {
684					temperature = <90000>;
685					hysteresis = <2000>;
686					type = "hot";
687				};
688			};
689		};
690
691		cluster1-l2-thermal {
692			polling-delay-passive = <250>;
693			polling-delay = <1000>;
694
695			thermal-sensors = <&tsens0 11>;
696
697			trips {
698				cluster1_l2_alert0: trip-point0 {
699					temperature = <90000>;
700					hysteresis = <2000>;
701					type = "hot";
702				};
703			};
704		};
705
706		modem-thermal {
707			polling-delay-passive = <250>;
708			polling-delay = <1000>;
709
710			thermal-sensors = <&tsens1 1>;
711
712			trips {
713				modem_alert0: trip-point0 {
714					temperature = <90000>;
715					hysteresis = <2000>;
716					type = "hot";
717				};
718			};
719		};
720
721		mem-thermal {
722			polling-delay-passive = <250>;
723			polling-delay = <1000>;
724
725			thermal-sensors = <&tsens1 2>;
726
727			trips {
728				mem_alert0: trip-point0 {
729					temperature = <90000>;
730					hysteresis = <2000>;
731					type = "hot";
732				};
733			};
734		};
735
736		wlan-thermal {
737			polling-delay-passive = <250>;
738			polling-delay = <1000>;
739
740			thermal-sensors = <&tsens1 3>;
741
742			trips {
743				wlan_alert0: trip-point0 {
744					temperature = <90000>;
745					hysteresis = <2000>;
746					type = "hot";
747				};
748			};
749		};
750
751		q6-dsp-thermal {
752			polling-delay-passive = <250>;
753			polling-delay = <1000>;
754
755			thermal-sensors = <&tsens1 4>;
756
757			trips {
758				q6_dsp_alert0: trip-point0 {
759					temperature = <90000>;
760					hysteresis = <2000>;
761					type = "hot";
762				};
763			};
764		};
765
766		camera-thermal {
767			polling-delay-passive = <250>;
768			polling-delay = <1000>;
769
770			thermal-sensors = <&tsens1 5>;
771
772			trips {
773				camera_alert0: trip-point0 {
774					temperature = <90000>;
775					hysteresis = <2000>;
776					type = "hot";
777				};
778			};
779		};
780
781		multimedia-thermal {
782			polling-delay-passive = <250>;
783			polling-delay = <1000>;
784
785			thermal-sensors = <&tsens1 6>;
786
787			trips {
788				multimedia_alert0: trip-point0 {
789					temperature = <90000>;
790					hysteresis = <2000>;
791					type = "hot";
792				};
793			};
794		};
795	};
796
797	timer {
798		compatible = "arm,armv8-timer";
799		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
800			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
801			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
802			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
803	};
804
805	soc: soc@0 {
806		#address-cells = <1>;
807		#size-cells = <1>;
808		ranges = <0 0 0 0xffffffff>;
809		compatible = "simple-bus";
810
811		gcc: clock-controller@100000 {
812			compatible = "qcom,gcc-msm8998";
813			#clock-cells = <1>;
814			#reset-cells = <1>;
815			#power-domain-cells = <1>;
816			reg = <0x00100000 0xb0000>;
817
818			clock-names = "xo", "sleep_clk";
819			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
820
821			/*
822			 * The hypervisor typically configures the memory region where these clocks
823			 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
824			 * these clocks on a device with such configuration (e.g. because they are
825			 * enabled but unused during boot-up), the device will most likely decide
826			 * to reboot.
827			 * In light of that, we are conservative here and we list all such clocks
828			 * as protected. The board dts (or a user-supplied dts) can override the
829			 * list of protected clocks if it differs from the norm, and it is in fact
830			 * desired for the HLOS to manage these clocks
831			 */
832			protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
833					   <SSC_XO>,
834					   <SSC_CNOC_AHBS_CLK>;
835		};
836
837		rpm_msg_ram: sram@778000 {
838			compatible = "qcom,rpm-msg-ram";
839			reg = <0x00778000 0x7000>;
840		};
841
842		qfprom: qfprom@784000 {
843			compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
844			reg = <0x00784000 0x621c>;
845			#address-cells = <1>;
846			#size-cells = <1>;
847
848			qusb2_hstx_trim: hstx-trim@23a {
849				reg = <0x23a 0x1>;
850				bits = <0 4>;
851			};
852		};
853
854		tsens0: thermal@10ab000 {
855			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
856			reg = <0x010ab000 0x1000>, /* TM */
857			      <0x010aa000 0x1000>; /* SROT */
858			#qcom,sensors = <14>;
859			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
860				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
861			interrupt-names = "uplow", "critical";
862			#thermal-sensor-cells = <1>;
863		};
864
865		tsens1: thermal@10ae000 {
866			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
867			reg = <0x010ae000 0x1000>, /* TM */
868			      <0x010ad000 0x1000>; /* SROT */
869			#qcom,sensors = <8>;
870			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
871				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
872			interrupt-names = "uplow", "critical";
873			#thermal-sensor-cells = <1>;
874		};
875
876		anoc1_smmu: iommu@1680000 {
877			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
878			reg = <0x01680000 0x10000>;
879			#iommu-cells = <1>;
880
881			#global-interrupts = <0>;
882			interrupts =
883				<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
884				<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
885				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
886				<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
887				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
888				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
889		};
890
891		anoc2_smmu: iommu@16c0000 {
892			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
893			reg = <0x016c0000 0x40000>;
894			#iommu-cells = <1>;
895
896			#global-interrupts = <0>;
897			interrupts =
898				<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
899				<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
900				<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
901				<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
902				<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
903				<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
904				<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
905				<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
906				<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
907				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
908		};
909
910		pcie0: pci@1c00000 {
911			compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
912			reg =	<0x01c00000 0x2000>,
913				<0x1b000000 0xf1d>,
914				<0x1b000f20 0xa8>,
915				<0x1b100000 0x100000>;
916			reg-names = "parf", "dbi", "elbi", "config";
917			device_type = "pci";
918			linux,pci-domain = <0>;
919			bus-range = <0x00 0xff>;
920			#address-cells = <3>;
921			#size-cells = <2>;
922			num-lanes = <1>;
923			phys = <&pciephy>;
924			phy-names = "pciephy";
925			status = "disabled";
926
927			ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
928				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
929
930			#interrupt-cells = <1>;
931			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
932			interrupt-names = "msi";
933			interrupt-map-mask = <0 0 0 0x7>;
934			interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
935					<0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
936					<0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
937					<0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
938
939			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
940				 <&gcc GCC_PCIE_0_AUX_CLK>,
941				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
942				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
943				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
944			clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
945
946			power-domains = <&gcc PCIE_0_GDSC>;
947			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
948			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
949		};
950
951		pcie_phy: phy@1c06000 {
952			compatible = "qcom,msm8998-qmp-pcie-phy";
953			reg = <0x01c06000 0x18c>;
954			#address-cells = <1>;
955			#size-cells = <1>;
956			status = "disabled";
957			ranges;
958
959			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
960				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
961				 <&gcc GCC_PCIE_CLKREF_CLK>;
962			clock-names = "aux", "cfg_ahb", "ref";
963
964			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
965			reset-names = "phy", "common";
966
967			vdda-phy-supply = <&vreg_l1a_0p875>;
968			vdda-pll-supply = <&vreg_l2a_1p2>;
969
970			pciephy: phy@1c06800 {
971				reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
972				#phy-cells = <0>;
973
974				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
975				clock-names = "pipe0";
976				clock-output-names = "pcie_0_pipe_clk_src";
977				#clock-cells = <0>;
978			};
979		};
980
981		ufshc: ufshc@1da4000 {
982			compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
983			reg = <0x01da4000 0x2500>;
984			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
985			phys = <&ufsphy_lanes>;
986			phy-names = "ufsphy";
987			lanes-per-direction = <2>;
988			power-domains = <&gcc UFS_GDSC>;
989			status = "disabled";
990			#reset-cells = <1>;
991
992			clock-names =
993				"core_clk",
994				"bus_aggr_clk",
995				"iface_clk",
996				"core_clk_unipro",
997				"ref_clk",
998				"tx_lane0_sync_clk",
999				"rx_lane0_sync_clk",
1000				"rx_lane1_sync_clk";
1001			clocks =
1002				<&gcc GCC_UFS_AXI_CLK>,
1003				<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1004				<&gcc GCC_UFS_AHB_CLK>,
1005				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1006				<&rpmcc RPM_SMD_LN_BB_CLK1>,
1007				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1008				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1009				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1010			freq-table-hz =
1011				<50000000 200000000>,
1012				<0 0>,
1013				<0 0>,
1014				<37500000 150000000>,
1015				<0 0>,
1016				<0 0>,
1017				<0 0>,
1018				<0 0>;
1019
1020			resets = <&gcc GCC_UFS_BCR>;
1021			reset-names = "rst";
1022		};
1023
1024		ufsphy: phy@1da7000 {
1025			compatible = "qcom,msm8998-qmp-ufs-phy";
1026			reg = <0x01da7000 0x18c>;
1027			#address-cells = <1>;
1028			#size-cells = <1>;
1029			status = "disabled";
1030			ranges;
1031
1032			clock-names =
1033				"ref",
1034				"ref_aux";
1035			clocks =
1036				<&gcc GCC_UFS_CLKREF_CLK>,
1037				<&gcc GCC_UFS_PHY_AUX_CLK>;
1038
1039			reset-names = "ufsphy";
1040			resets = <&ufshc 0>;
1041
1042			ufsphy_lanes: phy@1da7400 {
1043				reg = <0x01da7400 0x128>,
1044				      <0x01da7600 0x1fc>,
1045				      <0x01da7c00 0x1dc>,
1046				      <0x01da7800 0x128>,
1047				      <0x01da7a00 0x1fc>;
1048				#phy-cells = <0>;
1049			};
1050		};
1051
1052		tcsr_mutex: hwlock@1f40000 {
1053			compatible = "qcom,tcsr-mutex";
1054			reg = <0x01f40000 0x20000>;
1055			#hwlock-cells = <1>;
1056		};
1057
1058		tcsr_regs_1: syscon@1f60000 {
1059			compatible = "qcom,msm8998-tcsr", "syscon";
1060			reg = <0x01f60000 0x20000>;
1061		};
1062
1063		tlmm: pinctrl@3400000 {
1064			compatible = "qcom,msm8998-pinctrl";
1065			reg = <0x03400000 0xc00000>;
1066			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1067			gpio-ranges = <&tlmm 0 0 150>;
1068			gpio-controller;
1069			#gpio-cells = <2>;
1070			interrupt-controller;
1071			#interrupt-cells = <2>;
1072
1073			sdc2_on: sdc2-on-state {
1074				clk-pins {
1075					pins = "sdc2_clk";
1076					drive-strength = <16>;
1077					bias-disable;
1078				};
1079
1080				cmd-pins {
1081					pins = "sdc2_cmd";
1082					drive-strength = <10>;
1083					bias-pull-up;
1084				};
1085
1086				data-pins {
1087					pins = "sdc2_data";
1088					drive-strength = <10>;
1089					bias-pull-up;
1090				};
1091			};
1092
1093			sdc2_off: sdc2-off-state {
1094				clk-pins {
1095					pins = "sdc2_clk";
1096					drive-strength = <2>;
1097					bias-disable;
1098				};
1099
1100				cmd-pins {
1101					pins = "sdc2_cmd";
1102					drive-strength = <2>;
1103					bias-pull-up;
1104				};
1105
1106				data-pins {
1107					pins = "sdc2_data";
1108					drive-strength = <2>;
1109					bias-pull-up;
1110				};
1111			};
1112
1113			sdc2_cd: sdc2-cd-state {
1114				pins = "gpio95";
1115				function = "gpio";
1116				bias-pull-up;
1117				drive-strength = <2>;
1118			};
1119
1120			blsp1_uart3_on: blsp1-uart3-on-state {
1121				tx-pins {
1122					pins = "gpio45";
1123					function = "blsp_uart3_a";
1124					drive-strength = <2>;
1125					bias-disable;
1126				};
1127
1128				rx-pins {
1129					pins = "gpio46";
1130					function = "blsp_uart3_a";
1131					drive-strength = <2>;
1132					bias-disable;
1133				};
1134
1135				cts-pins {
1136					pins = "gpio47";
1137					function = "blsp_uart3_a";
1138					drive-strength = <2>;
1139					bias-disable;
1140				};
1141
1142				rfr-pins {
1143					pins = "gpio48";
1144					function = "blsp_uart3_a";
1145					drive-strength = <2>;
1146					bias-disable;
1147				};
1148			};
1149
1150			blsp1_i2c1_default: blsp1-i2c1-default-state {
1151				pins = "gpio2", "gpio3";
1152				function = "blsp_i2c1";
1153				drive-strength = <2>;
1154				bias-disable;
1155			};
1156
1157			blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1158				pins = "gpio2", "gpio3";
1159				function = "blsp_i2c1";
1160				drive-strength = <2>;
1161				bias-pull-up;
1162			};
1163
1164			blsp1_i2c2_default: blsp1-i2c2-default-state {
1165				pins = "gpio32", "gpio33";
1166				function = "blsp_i2c2";
1167				drive-strength = <2>;
1168				bias-disable;
1169			};
1170
1171			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1172				pins = "gpio32", "gpio33";
1173				function = "blsp_i2c2";
1174				drive-strength = <2>;
1175				bias-pull-up;
1176			};
1177
1178			blsp1_i2c3_default: blsp1-i2c3-default-state {
1179				pins = "gpio47", "gpio48";
1180				function = "blsp_i2c3";
1181				drive-strength = <2>;
1182				bias-disable;
1183			};
1184
1185			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1186				pins = "gpio47", "gpio48";
1187				function = "blsp_i2c3";
1188				drive-strength = <2>;
1189				bias-pull-up;
1190			};
1191
1192			blsp1_i2c4_default: blsp1-i2c4-default-state {
1193				pins = "gpio10", "gpio11";
1194				function = "blsp_i2c4";
1195				drive-strength = <2>;
1196				bias-disable;
1197			};
1198
1199			blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1200				pins = "gpio10", "gpio11";
1201				function = "blsp_i2c4";
1202				drive-strength = <2>;
1203				bias-pull-up;
1204			};
1205
1206			blsp1_i2c5_default: blsp1-i2c5-default-state {
1207				pins = "gpio87", "gpio88";
1208				function = "blsp_i2c5";
1209				drive-strength = <2>;
1210				bias-disable;
1211			};
1212
1213			blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1214				pins = "gpio87", "gpio88";
1215				function = "blsp_i2c5";
1216				drive-strength = <2>;
1217				bias-pull-up;
1218			};
1219
1220			blsp1_i2c6_default: blsp1-i2c6-default-state {
1221				pins = "gpio43", "gpio44";
1222				function = "blsp_i2c6";
1223				drive-strength = <2>;
1224				bias-disable;
1225			};
1226
1227			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1228				pins = "gpio43", "gpio44";
1229				function = "blsp_i2c6";
1230				drive-strength = <2>;
1231				bias-pull-up;
1232			};
1233
1234			blsp1_spi_b_default: blsp1-spi-b-default-state {
1235				pins = "gpio23", "gpio28";
1236				function = "blsp1_spi_b";
1237				drive-strength = <6>;
1238				bias-disable;
1239			};
1240
1241			blsp1_spi1_default: blsp1-spi1-default-state {
1242				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1243				function = "blsp_spi1";
1244				drive-strength = <6>;
1245				bias-disable;
1246			};
1247
1248			blsp1_spi2_default: blsp1-spi2-default-state {
1249				pins = "gpio31", "gpio34", "gpio32", "gpio33";
1250				function = "blsp_spi2";
1251				drive-strength = <6>;
1252				bias-disable;
1253			};
1254
1255			blsp1_spi3_default: blsp1-spi3-default-state {
1256				pins = "gpio45", "gpio46", "gpio47", "gpio48";
1257				function = "blsp_spi2";
1258				drive-strength = <6>;
1259				bias-disable;
1260			};
1261
1262			blsp1_spi4_default: blsp1-spi4-default-state {
1263				pins = "gpio8", "gpio9", "gpio10", "gpio11";
1264				function = "blsp_spi4";
1265				drive-strength = <6>;
1266				bias-disable;
1267			};
1268
1269			blsp1_spi5_default: blsp1-spi5-default-state {
1270				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1271				function = "blsp_spi5";
1272				drive-strength = <6>;
1273				bias-disable;
1274			};
1275
1276			blsp1_spi6_default: blsp1-spi6-default-state {
1277				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1278				function = "blsp_spi6";
1279				drive-strength = <6>;
1280				bias-disable;
1281			};
1282
1283
1284			/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1285			blsp2_i2c1_default: blsp2-i2c1-default-state {
1286				pins = "gpio55", "gpio56";
1287				function = "blsp_i2c7";
1288				drive-strength = <2>;
1289				bias-disable;
1290			};
1291
1292			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1293				pins = "gpio55", "gpio56";
1294				function = "blsp_i2c7";
1295				drive-strength = <2>;
1296				bias-pull-up;
1297			};
1298
1299			blsp2_i2c2_default: blsp2-i2c2-default-state {
1300				pins = "gpio6", "gpio7";
1301				function = "blsp_i2c8";
1302				drive-strength = <2>;
1303				bias-disable;
1304			};
1305
1306			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1307				pins = "gpio6", "gpio7";
1308				function = "blsp_i2c8";
1309				drive-strength = <2>;
1310				bias-pull-up;
1311			};
1312
1313			blsp2_i2c3_default: blsp2-i2c3-default-state {
1314				pins = "gpio51", "gpio52";
1315				function = "blsp_i2c9";
1316				drive-strength = <2>;
1317				bias-disable;
1318			};
1319
1320			blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1321				pins = "gpio51", "gpio52";
1322				function = "blsp_i2c9";
1323				drive-strength = <2>;
1324				bias-pull-up;
1325			};
1326
1327			blsp2_i2c4_default: blsp2-i2c4-default-state {
1328				pins = "gpio67", "gpio68";
1329				function = "blsp_i2c10";
1330				drive-strength = <2>;
1331				bias-disable;
1332			};
1333
1334			blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1335				pins = "gpio67", "gpio68";
1336				function = "blsp_i2c10";
1337				drive-strength = <2>;
1338				bias-pull-up;
1339			};
1340
1341			blsp2_i2c5_default: blsp2-i2c5-default-state {
1342				pins = "gpio60", "gpio61";
1343				function = "blsp_i2c11";
1344				drive-strength = <2>;
1345				bias-disable;
1346			};
1347
1348			blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1349				pins = "gpio60", "gpio61";
1350				function = "blsp_i2c11";
1351				drive-strength = <2>;
1352				bias-pull-up;
1353			};
1354
1355			blsp2_i2c6_default: blsp2-i2c6-default-state {
1356				pins = "gpio83", "gpio84";
1357				function = "blsp_i2c12";
1358				drive-strength = <2>;
1359				bias-disable;
1360			};
1361
1362			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1363				pins = "gpio83", "gpio84";
1364				function = "blsp_i2c12";
1365				drive-strength = <2>;
1366				bias-pull-up;
1367			};
1368
1369			blsp2_spi1_default: blsp2-spi1-default-state {
1370				pins = "gpio53", "gpio54", "gpio55", "gpio56";
1371				function = "blsp_spi7";
1372				drive-strength = <6>;
1373				bias-disable;
1374			};
1375
1376			blsp2_spi2_default: blsp2-spi2-default-state {
1377				pins = "gpio4", "gpio5", "gpio6", "gpio7";
1378				function = "blsp_spi8";
1379				drive-strength = <6>;
1380				bias-disable;
1381			};
1382
1383			blsp2_spi3_default: blsp2-spi3-default-state {
1384				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1385				function = "blsp_spi9";
1386				drive-strength = <6>;
1387				bias-disable;
1388			};
1389
1390			blsp2_spi4_default: blsp2-spi4-default-state {
1391				pins = "gpio65", "gpio66", "gpio67", "gpio68";
1392				function = "blsp_spi10";
1393				drive-strength = <6>;
1394				bias-disable;
1395			};
1396
1397			blsp2_spi5_default: blsp2-spi5-default-state {
1398				pins = "gpio58", "gpio59", "gpio60", "gpio61";
1399				function = "blsp_spi11";
1400				drive-strength = <6>;
1401				bias-disable;
1402			};
1403
1404			blsp2_spi6_default: blsp2-spi6-default-state {
1405				pins = "gpio81", "gpio82", "gpio83", "gpio84";
1406				function = "blsp_spi12";
1407				drive-strength = <6>;
1408				bias-disable;
1409			};
1410		};
1411
1412		remoteproc_mss: remoteproc@4080000 {
1413			compatible = "qcom,msm8998-mss-pil";
1414			reg = <0x04080000 0x100>, <0x04180000 0x20>;
1415			reg-names = "qdsp6", "rmb";
1416
1417			interrupts-extended =
1418				<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1419				<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1420				<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1421				<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1422				<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1423				<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1424			interrupt-names = "wdog", "fatal", "ready",
1425					  "handover", "stop-ack",
1426					  "shutdown-ack";
1427
1428			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1429				 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1430				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1431				 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1432				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1433				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1434				 <&rpmcc RPM_SMD_QDSS_CLK>,
1435				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1436			clock-names = "iface", "bus", "mem", "gpll0_mss",
1437				      "snoc_axi", "mnoc_axi", "qdss", "xo";
1438
1439			qcom,smem-states = <&modem_smp2p_out 0>;
1440			qcom,smem-state-names = "stop";
1441
1442			resets = <&gcc GCC_MSS_RESTART>;
1443			reset-names = "mss_restart";
1444
1445			qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1446
1447			power-domains = <&rpmpd MSM8998_VDDCX>,
1448					<&rpmpd MSM8998_VDDMX>;
1449			power-domain-names = "cx", "mx";
1450
1451			status = "disabled";
1452
1453			mba {
1454				memory-region = <&mba_mem>;
1455			};
1456
1457			mpss {
1458				memory-region = <&mpss_mem>;
1459			};
1460
1461			metadata {
1462				memory-region = <&mdata_mem>;
1463			};
1464
1465			glink-edge {
1466				interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1467				label = "modem";
1468				qcom,remote-pid = <1>;
1469				mboxes = <&apcs_glb 15>;
1470			};
1471		};
1472
1473		adreno_gpu: gpu@5000000 {
1474			compatible = "qcom,adreno-540.1", "qcom,adreno";
1475			reg = <0x05000000 0x40000>;
1476			reg-names = "kgsl_3d0_reg_memory";
1477
1478			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1479				<&gpucc RBBMTIMER_CLK>,
1480				<&gcc GCC_BIMC_GFX_CLK>,
1481				<&gcc GCC_GPU_BIMC_GFX_CLK>,
1482				<&gpucc RBCPR_CLK>,
1483				<&gpucc GFX3D_CLK>;
1484			clock-names = "iface",
1485				"rbbmtimer",
1486				"mem",
1487				"mem_iface",
1488				"rbcpr",
1489				"core";
1490
1491			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1492			iommus = <&adreno_smmu 0>;
1493			operating-points-v2 = <&gpu_opp_table>;
1494			power-domains = <&rpmpd MSM8998_VDDMX>;
1495			status = "disabled";
1496
1497			gpu_opp_table: opp-table {
1498				compatible = "operating-points-v2";
1499				opp-710000097 {
1500					opp-hz = /bits/ 64 <710000097>;
1501					opp-level = <RPM_SMD_LEVEL_TURBO>;
1502					opp-supported-hw = <0xff>;
1503				};
1504
1505				opp-670000048 {
1506					opp-hz = /bits/ 64 <670000048>;
1507					opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1508					opp-supported-hw = <0xff>;
1509				};
1510
1511				opp-596000097 {
1512					opp-hz = /bits/ 64 <596000097>;
1513					opp-level = <RPM_SMD_LEVEL_NOM>;
1514					opp-supported-hw = <0xff>;
1515				};
1516
1517				opp-515000097 {
1518					opp-hz = /bits/ 64 <515000097>;
1519					opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1520					opp-supported-hw = <0xff>;
1521				};
1522
1523				opp-414000000 {
1524					opp-hz = /bits/ 64 <414000000>;
1525					opp-level = <RPM_SMD_LEVEL_SVS>;
1526					opp-supported-hw = <0xff>;
1527				};
1528
1529				opp-342000000 {
1530					opp-hz = /bits/ 64 <342000000>;
1531					opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1532					opp-supported-hw = <0xff>;
1533				};
1534
1535				opp-257000000 {
1536					opp-hz = /bits/ 64 <257000000>;
1537					opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1538					opp-supported-hw = <0xff>;
1539				};
1540			};
1541		};
1542
1543		adreno_smmu: iommu@5040000 {
1544			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1545			reg = <0x05040000 0x10000>;
1546			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1547				 <&gcc GCC_BIMC_GFX_CLK>,
1548				 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1549			clock-names = "iface", "mem", "mem_iface";
1550
1551			#global-interrupts = <0>;
1552			#iommu-cells = <1>;
1553			interrupts =
1554				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1555				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1556				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1557			/*
1558			 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1559			 * GPU-CX for SMMU but we need both of them up for Adreno.
1560			 * Contemporarily, we also need to manage the VDDMX rpmpd
1561			 * domain in the Adreno driver.
1562			 * Enable GPU CX/GX GDSCs here so that we can manage the
1563			 * SoC VDDMX RPM Power Domain in the Adreno driver.
1564			 */
1565			power-domains = <&gpucc GPU_GX_GDSC>;
1566			status = "disabled";
1567		};
1568
1569		gpucc: clock-controller@5065000 {
1570			compatible = "qcom,msm8998-gpucc";
1571			#clock-cells = <1>;
1572			#reset-cells = <1>;
1573			#power-domain-cells = <1>;
1574			reg = <0x05065000 0x9000>;
1575
1576			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1577				 <&gcc GPLL0_OUT_MAIN>;
1578			clock-names = "xo",
1579				      "gpll0";
1580		};
1581
1582		remoteproc_slpi: remoteproc@5800000 {
1583			compatible = "qcom,msm8998-slpi-pas";
1584			reg = <0x05800000 0x4040>;
1585
1586			interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1587					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1588					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1589					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1590					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1591			interrupt-names = "wdog", "fatal", "ready",
1592					  "handover", "stop-ack";
1593
1594			px-supply = <&vreg_lvs2a_1p8>;
1595
1596			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1597				 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1598			clock-names = "xo", "aggre2";
1599
1600			memory-region = <&slpi_mem>;
1601
1602			qcom,smem-states = <&slpi_smp2p_out 0>;
1603			qcom,smem-state-names = "stop";
1604
1605			power-domains = <&rpmpd MSM8998_SSCCX>;
1606			power-domain-names = "ssc_cx";
1607
1608			status = "disabled";
1609
1610			glink-edge {
1611				interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1612				label = "dsps";
1613				qcom,remote-pid = <3>;
1614				mboxes = <&apcs_glb 27>;
1615			};
1616		};
1617
1618		stm: stm@6002000 {
1619			compatible = "arm,coresight-stm", "arm,primecell";
1620			reg = <0x06002000 0x1000>,
1621			      <0x16280000 0x180000>;
1622			reg-names = "stm-base", "stm-stimulus-base";
1623			status = "disabled";
1624
1625			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1626			clock-names = "apb_pclk", "atclk";
1627
1628			out-ports {
1629				port {
1630					stm_out: endpoint {
1631						remote-endpoint = <&funnel0_in7>;
1632					};
1633				};
1634			};
1635		};
1636
1637		funnel1: funnel@6041000 {
1638			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1639			reg = <0x06041000 0x1000>;
1640			status = "disabled";
1641
1642			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1643			clock-names = "apb_pclk", "atclk";
1644
1645			out-ports {
1646				port {
1647					funnel0_out: endpoint {
1648						remote-endpoint =
1649						  <&merge_funnel_in0>;
1650					};
1651				};
1652			};
1653
1654			in-ports {
1655				#address-cells = <1>;
1656				#size-cells = <0>;
1657
1658				port@7 {
1659					reg = <7>;
1660					funnel0_in7: endpoint {
1661						remote-endpoint = <&stm_out>;
1662					};
1663				};
1664			};
1665		};
1666
1667		funnel2: funnel@6042000 {
1668			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1669			reg = <0x06042000 0x1000>;
1670			status = "disabled";
1671
1672			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1673			clock-names = "apb_pclk", "atclk";
1674
1675			out-ports {
1676				port {
1677					funnel1_out: endpoint {
1678						remote-endpoint =
1679						  <&merge_funnel_in1>;
1680					};
1681				};
1682			};
1683
1684			in-ports {
1685				#address-cells = <1>;
1686				#size-cells = <0>;
1687
1688				port@6 {
1689					reg = <6>;
1690					funnel1_in6: endpoint {
1691						remote-endpoint =
1692						  <&apss_merge_funnel_out>;
1693					};
1694				};
1695			};
1696		};
1697
1698		funnel3: funnel@6045000 {
1699			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1700			reg = <0x06045000 0x1000>;
1701			status = "disabled";
1702
1703			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1704			clock-names = "apb_pclk", "atclk";
1705
1706			out-ports {
1707				port {
1708					merge_funnel_out: endpoint {
1709						remote-endpoint =
1710						  <&etf_in>;
1711					};
1712				};
1713			};
1714
1715			in-ports {
1716				#address-cells = <1>;
1717				#size-cells = <0>;
1718
1719				port@0 {
1720					reg = <0>;
1721					merge_funnel_in0: endpoint {
1722						remote-endpoint =
1723						  <&funnel0_out>;
1724					};
1725				};
1726
1727				port@1 {
1728					reg = <1>;
1729					merge_funnel_in1: endpoint {
1730						remote-endpoint =
1731						  <&funnel1_out>;
1732					};
1733				};
1734			};
1735		};
1736
1737		replicator1: replicator@6046000 {
1738			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1739			reg = <0x06046000 0x1000>;
1740			status = "disabled";
1741
1742			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1743			clock-names = "apb_pclk", "atclk";
1744
1745			out-ports {
1746				port {
1747					replicator_out: endpoint {
1748						remote-endpoint = <&etr_in>;
1749					};
1750				};
1751			};
1752
1753			in-ports {
1754				port {
1755					replicator_in: endpoint {
1756						remote-endpoint = <&etf_out>;
1757					};
1758				};
1759			};
1760		};
1761
1762		etf: etf@6047000 {
1763			compatible = "arm,coresight-tmc", "arm,primecell";
1764			reg = <0x06047000 0x1000>;
1765			status = "disabled";
1766
1767			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1768			clock-names = "apb_pclk", "atclk";
1769
1770			out-ports {
1771				port {
1772					etf_out: endpoint {
1773						remote-endpoint =
1774						  <&replicator_in>;
1775					};
1776				};
1777			};
1778
1779			in-ports {
1780				port {
1781					etf_in: endpoint {
1782						remote-endpoint =
1783						  <&merge_funnel_out>;
1784					};
1785				};
1786			};
1787		};
1788
1789		etr: etr@6048000 {
1790			compatible = "arm,coresight-tmc", "arm,primecell";
1791			reg = <0x06048000 0x1000>;
1792			status = "disabled";
1793
1794			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1795			clock-names = "apb_pclk", "atclk";
1796			arm,scatter-gather;
1797
1798			in-ports {
1799				port {
1800					etr_in: endpoint {
1801						remote-endpoint =
1802						  <&replicator_out>;
1803					};
1804				};
1805			};
1806		};
1807
1808		etm1: etm@7840000 {
1809			compatible = "arm,coresight-etm4x", "arm,primecell";
1810			reg = <0x07840000 0x1000>;
1811			status = "disabled";
1812
1813			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1814			clock-names = "apb_pclk", "atclk";
1815
1816			cpu = <&CPU0>;
1817
1818			out-ports {
1819				port {
1820					etm0_out: endpoint {
1821						remote-endpoint =
1822						  <&apss_funnel_in0>;
1823					};
1824				};
1825			};
1826		};
1827
1828		etm2: etm@7940000 {
1829			compatible = "arm,coresight-etm4x", "arm,primecell";
1830			reg = <0x07940000 0x1000>;
1831			status = "disabled";
1832
1833			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1834			clock-names = "apb_pclk", "atclk";
1835
1836			cpu = <&CPU1>;
1837
1838			out-ports {
1839				port {
1840					etm1_out: endpoint {
1841						remote-endpoint =
1842						  <&apss_funnel_in1>;
1843					};
1844				};
1845			};
1846		};
1847
1848		etm3: etm@7a40000 {
1849			compatible = "arm,coresight-etm4x", "arm,primecell";
1850			reg = <0x07a40000 0x1000>;
1851			status = "disabled";
1852
1853			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1854			clock-names = "apb_pclk", "atclk";
1855
1856			cpu = <&CPU2>;
1857
1858			out-ports {
1859				port {
1860					etm2_out: endpoint {
1861						remote-endpoint =
1862						  <&apss_funnel_in2>;
1863					};
1864				};
1865			};
1866		};
1867
1868		etm4: etm@7b40000 {
1869			compatible = "arm,coresight-etm4x", "arm,primecell";
1870			reg = <0x07b40000 0x1000>;
1871			status = "disabled";
1872
1873			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1874			clock-names = "apb_pclk", "atclk";
1875
1876			cpu = <&CPU3>;
1877
1878			out-ports {
1879				port {
1880					etm3_out: endpoint {
1881						remote-endpoint =
1882						  <&apss_funnel_in3>;
1883					};
1884				};
1885			};
1886		};
1887
1888		funnel4: funnel@7b60000 { /* APSS Funnel */
1889			compatible = "arm,coresight-etm4x", "arm,primecell";
1890			reg = <0x07b60000 0x1000>;
1891			status = "disabled";
1892
1893			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1894			clock-names = "apb_pclk", "atclk";
1895
1896			out-ports {
1897				port {
1898					apss_funnel_out: endpoint {
1899						remote-endpoint =
1900						  <&apss_merge_funnel_in>;
1901					};
1902				};
1903			};
1904
1905			in-ports {
1906				#address-cells = <1>;
1907				#size-cells = <0>;
1908
1909				port@0 {
1910					reg = <0>;
1911					apss_funnel_in0: endpoint {
1912						remote-endpoint =
1913						  <&etm0_out>;
1914					};
1915				};
1916
1917				port@1 {
1918					reg = <1>;
1919					apss_funnel_in1: endpoint {
1920						remote-endpoint =
1921						  <&etm1_out>;
1922					};
1923				};
1924
1925				port@2 {
1926					reg = <2>;
1927					apss_funnel_in2: endpoint {
1928						remote-endpoint =
1929						  <&etm2_out>;
1930					};
1931				};
1932
1933				port@3 {
1934					reg = <3>;
1935					apss_funnel_in3: endpoint {
1936						remote-endpoint =
1937						  <&etm3_out>;
1938					};
1939				};
1940
1941				port@4 {
1942					reg = <4>;
1943					apss_funnel_in4: endpoint {
1944						remote-endpoint =
1945						  <&etm4_out>;
1946					};
1947				};
1948
1949				port@5 {
1950					reg = <5>;
1951					apss_funnel_in5: endpoint {
1952						remote-endpoint =
1953						  <&etm5_out>;
1954					};
1955				};
1956
1957				port@6 {
1958					reg = <6>;
1959					apss_funnel_in6: endpoint {
1960						remote-endpoint =
1961						  <&etm6_out>;
1962					};
1963				};
1964
1965				port@7 {
1966					reg = <7>;
1967					apss_funnel_in7: endpoint {
1968						remote-endpoint =
1969						  <&etm7_out>;
1970					};
1971				};
1972			};
1973		};
1974
1975		funnel5: funnel@7b70000 {
1976			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1977			reg = <0x07b70000 0x1000>;
1978			status = "disabled";
1979
1980			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1981			clock-names = "apb_pclk", "atclk";
1982
1983			out-ports {
1984				port {
1985					apss_merge_funnel_out: endpoint {
1986						remote-endpoint =
1987						  <&funnel1_in6>;
1988					};
1989				};
1990			};
1991
1992			in-ports {
1993				port {
1994					apss_merge_funnel_in: endpoint {
1995						remote-endpoint =
1996						  <&apss_funnel_out>;
1997					};
1998				};
1999			};
2000		};
2001
2002		etm5: etm@7c40000 {
2003			compatible = "arm,coresight-etm4x", "arm,primecell";
2004			reg = <0x07c40000 0x1000>;
2005			status = "disabled";
2006
2007			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2008			clock-names = "apb_pclk", "atclk";
2009
2010			cpu = <&CPU4>;
2011
2012			port {
2013				etm4_out: endpoint {
2014					remote-endpoint = <&apss_funnel_in4>;
2015				};
2016			};
2017		};
2018
2019		etm6: etm@7d40000 {
2020			compatible = "arm,coresight-etm4x", "arm,primecell";
2021			reg = <0x07d40000 0x1000>;
2022			status = "disabled";
2023
2024			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2025			clock-names = "apb_pclk", "atclk";
2026
2027			cpu = <&CPU5>;
2028
2029			port {
2030				etm5_out: endpoint {
2031					remote-endpoint = <&apss_funnel_in5>;
2032				};
2033			};
2034		};
2035
2036		etm7: etm@7e40000 {
2037			compatible = "arm,coresight-etm4x", "arm,primecell";
2038			reg = <0x07e40000 0x1000>;
2039			status = "disabled";
2040
2041			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2042			clock-names = "apb_pclk", "atclk";
2043
2044			cpu = <&CPU6>;
2045
2046			port {
2047				etm6_out: endpoint {
2048					remote-endpoint = <&apss_funnel_in6>;
2049				};
2050			};
2051		};
2052
2053		etm8: etm@7f40000 {
2054			compatible = "arm,coresight-etm4x", "arm,primecell";
2055			reg = <0x07f40000 0x1000>;
2056			status = "disabled";
2057
2058			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2059			clock-names = "apb_pclk", "atclk";
2060
2061			cpu = <&CPU7>;
2062
2063			port {
2064				etm7_out: endpoint {
2065					remote-endpoint = <&apss_funnel_in7>;
2066				};
2067			};
2068		};
2069
2070		sram@290000 {
2071			compatible = "qcom,rpm-stats";
2072			reg = <0x00290000 0x10000>;
2073		};
2074
2075		spmi_bus: spmi@800f000 {
2076			compatible = "qcom,spmi-pmic-arb";
2077			reg =	<0x0800f000 0x1000>,
2078				<0x08400000 0x1000000>,
2079				<0x09400000 0x1000000>,
2080				<0x0a400000 0x220000>,
2081				<0x0800a000 0x3000>;
2082			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2083			interrupt-names = "periph_irq";
2084			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2085			qcom,ee = <0>;
2086			qcom,channel = <0>;
2087			#address-cells = <2>;
2088			#size-cells = <0>;
2089			interrupt-controller;
2090			#interrupt-cells = <4>;
2091		};
2092
2093		usb3: usb@a8f8800 {
2094			compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2095			reg = <0x0a8f8800 0x400>;
2096			status = "disabled";
2097			#address-cells = <1>;
2098			#size-cells = <1>;
2099			ranges;
2100
2101			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2102				 <&gcc GCC_USB30_MASTER_CLK>,
2103				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2104				 <&gcc GCC_USB30_SLEEP_CLK>,
2105				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2106			clock-names = "cfg_noc",
2107				      "core",
2108				      "iface",
2109				      "sleep",
2110				      "mock_utmi";
2111
2112			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2113					  <&gcc GCC_USB30_MASTER_CLK>;
2114			assigned-clock-rates = <19200000>, <120000000>;
2115
2116			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2117				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2118			interrupt-names = "hs_phy_irq", "ss_phy_irq";
2119
2120			power-domains = <&gcc USB_30_GDSC>;
2121
2122			resets = <&gcc GCC_USB_30_BCR>;
2123
2124			usb3_dwc3: usb@a800000 {
2125				compatible = "snps,dwc3";
2126				reg = <0x0a800000 0xcd00>;
2127				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2128				snps,dis_u2_susphy_quirk;
2129				snps,dis_enblslpm_quirk;
2130				phys = <&qusb2phy>, <&usb1_ssphy>;
2131				phy-names = "usb2-phy", "usb3-phy";
2132				snps,has-lpm-erratum;
2133				snps,hird-threshold = /bits/ 8 <0x10>;
2134			};
2135		};
2136
2137		usb3phy: phy@c010000 {
2138			compatible = "qcom,msm8998-qmp-usb3-phy";
2139			reg = <0x0c010000 0x18c>;
2140			status = "disabled";
2141			#address-cells = <1>;
2142			#size-cells = <1>;
2143			ranges;
2144
2145			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2146				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2147				 <&gcc GCC_USB3_CLKREF_CLK>;
2148			clock-names = "aux", "cfg_ahb", "ref";
2149
2150			resets = <&gcc GCC_USB3_PHY_BCR>,
2151				 <&gcc GCC_USB3PHY_PHY_BCR>;
2152			reset-names = "phy", "common";
2153
2154			usb1_ssphy: phy@c010200 {
2155				reg = <0xc010200 0x128>,
2156				      <0xc010400 0x200>,
2157				      <0xc010c00 0x20c>,
2158				      <0xc010600 0x128>,
2159				      <0xc010800 0x200>;
2160				#phy-cells = <0>;
2161				#clock-cells = <0>;
2162				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2163				clock-names = "pipe0";
2164				clock-output-names = "usb3_phy_pipe_clk_src";
2165			};
2166		};
2167
2168		qusb2phy: phy@c012000 {
2169			compatible = "qcom,msm8998-qusb2-phy";
2170			reg = <0x0c012000 0x2a8>;
2171			status = "disabled";
2172			#phy-cells = <0>;
2173
2174			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2175				 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2176			clock-names = "cfg_ahb", "ref";
2177
2178			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2179
2180			nvmem-cells = <&qusb2_hstx_trim>;
2181		};
2182
2183		sdhc2: mmc@c0a4900 {
2184			compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2185			reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2186			reg-names = "hc", "core";
2187
2188			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2189				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2190			interrupt-names = "hc_irq", "pwr_irq";
2191
2192			clock-names = "iface", "core", "xo";
2193			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2194				 <&gcc GCC_SDCC2_APPS_CLK>,
2195				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2196			bus-width = <4>;
2197			status = "disabled";
2198		};
2199
2200		blsp1_dma: dma-controller@c144000 {
2201			compatible = "qcom,bam-v1.7.0";
2202			reg = <0x0c144000 0x25000>;
2203			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2204			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2205			clock-names = "bam_clk";
2206			#dma-cells = <1>;
2207			qcom,ee = <0>;
2208			qcom,controlled-remotely;
2209			num-channels = <18>;
2210			qcom,num-ees = <4>;
2211		};
2212
2213		blsp1_uart3: serial@c171000 {
2214			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2215			reg = <0x0c171000 0x1000>;
2216			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2217			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2218				 <&gcc GCC_BLSP1_AHB_CLK>;
2219			clock-names = "core", "iface";
2220			dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2221			dma-names = "tx", "rx";
2222			pinctrl-names = "default";
2223			pinctrl-0 = <&blsp1_uart3_on>;
2224			status = "disabled";
2225		};
2226
2227		blsp1_i2c1: i2c@c175000 {
2228			compatible = "qcom,i2c-qup-v2.2.1";
2229			reg = <0x0c175000 0x600>;
2230			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2231
2232			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2233				 <&gcc GCC_BLSP1_AHB_CLK>;
2234			clock-names = "core", "iface";
2235			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2236			dma-names = "tx", "rx";
2237			pinctrl-names = "default", "sleep";
2238			pinctrl-0 = <&blsp1_i2c1_default>;
2239			pinctrl-1 = <&blsp1_i2c1_sleep>;
2240			clock-frequency = <400000>;
2241
2242			status = "disabled";
2243			#address-cells = <1>;
2244			#size-cells = <0>;
2245		};
2246
2247		blsp1_i2c2: i2c@c176000 {
2248			compatible = "qcom,i2c-qup-v2.2.1";
2249			reg = <0x0c176000 0x600>;
2250			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2251
2252			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2253				 <&gcc GCC_BLSP1_AHB_CLK>;
2254			clock-names = "core", "iface";
2255			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2256			dma-names = "tx", "rx";
2257			pinctrl-names = "default", "sleep";
2258			pinctrl-0 = <&blsp1_i2c2_default>;
2259			pinctrl-1 = <&blsp1_i2c2_sleep>;
2260			clock-frequency = <400000>;
2261
2262			status = "disabled";
2263			#address-cells = <1>;
2264			#size-cells = <0>;
2265		};
2266
2267		blsp1_i2c3: i2c@c177000 {
2268			compatible = "qcom,i2c-qup-v2.2.1";
2269			reg = <0x0c177000 0x600>;
2270			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2271
2272			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2273				 <&gcc GCC_BLSP1_AHB_CLK>;
2274			clock-names = "core", "iface";
2275			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2276			dma-names = "tx", "rx";
2277			pinctrl-names = "default", "sleep";
2278			pinctrl-0 = <&blsp1_i2c3_default>;
2279			pinctrl-1 = <&blsp1_i2c3_sleep>;
2280			clock-frequency = <400000>;
2281
2282			status = "disabled";
2283			#address-cells = <1>;
2284			#size-cells = <0>;
2285		};
2286
2287		blsp1_i2c4: i2c@c178000 {
2288			compatible = "qcom,i2c-qup-v2.2.1";
2289			reg = <0x0c178000 0x600>;
2290			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2291
2292			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2293				 <&gcc GCC_BLSP1_AHB_CLK>;
2294			clock-names = "core", "iface";
2295			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2296			dma-names = "tx", "rx";
2297			pinctrl-names = "default", "sleep";
2298			pinctrl-0 = <&blsp1_i2c4_default>;
2299			pinctrl-1 = <&blsp1_i2c4_sleep>;
2300			clock-frequency = <400000>;
2301
2302			status = "disabled";
2303			#address-cells = <1>;
2304			#size-cells = <0>;
2305		};
2306
2307		blsp1_i2c5: i2c@c179000 {
2308			compatible = "qcom,i2c-qup-v2.2.1";
2309			reg = <0x0c179000 0x600>;
2310			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2311
2312			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2313				 <&gcc GCC_BLSP1_AHB_CLK>;
2314			clock-names = "core", "iface";
2315			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2316			dma-names = "tx", "rx";
2317			pinctrl-names = "default", "sleep";
2318			pinctrl-0 = <&blsp1_i2c5_default>;
2319			pinctrl-1 = <&blsp1_i2c5_sleep>;
2320			clock-frequency = <400000>;
2321
2322			status = "disabled";
2323			#address-cells = <1>;
2324			#size-cells = <0>;
2325		};
2326
2327		blsp1_i2c6: i2c@c17a000 {
2328			compatible = "qcom,i2c-qup-v2.2.1";
2329			reg = <0x0c17a000 0x600>;
2330			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2331
2332			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2333				 <&gcc GCC_BLSP1_AHB_CLK>;
2334			clock-names = "core", "iface";
2335			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2336			dma-names = "tx", "rx";
2337			pinctrl-names = "default", "sleep";
2338			pinctrl-0 = <&blsp1_i2c6_default>;
2339			pinctrl-1 = <&blsp1_i2c6_sleep>;
2340			clock-frequency = <400000>;
2341
2342			status = "disabled";
2343			#address-cells = <1>;
2344			#size-cells = <0>;
2345		};
2346
2347		blsp1_spi1: spi@c175000 {
2348			compatible = "qcom,spi-qup-v2.2.1";
2349			reg = <0x0c175000 0x600>;
2350			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2351
2352			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2353				 <&gcc GCC_BLSP1_AHB_CLK>;
2354			clock-names = "core", "iface";
2355			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2356			dma-names = "tx", "rx";
2357			pinctrl-names = "default";
2358			pinctrl-0 = <&blsp1_spi1_default>;
2359
2360			status = "disabled";
2361			#address-cells = <1>;
2362			#size-cells = <0>;
2363		};
2364
2365		blsp1_spi2: spi@c176000 {
2366			compatible = "qcom,spi-qup-v2.2.1";
2367			reg = <0x0c176000 0x600>;
2368			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2369
2370			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2371				 <&gcc GCC_BLSP1_AHB_CLK>;
2372			clock-names = "core", "iface";
2373			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2374			dma-names = "tx", "rx";
2375			pinctrl-names = "default";
2376			pinctrl-0 = <&blsp1_spi2_default>;
2377
2378			status = "disabled";
2379			#address-cells = <1>;
2380			#size-cells = <0>;
2381		};
2382
2383		blsp1_spi3: spi@c177000 {
2384			compatible = "qcom,spi-qup-v2.2.1";
2385			reg = <0x0c177000 0x600>;
2386			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2387
2388			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2389				 <&gcc GCC_BLSP1_AHB_CLK>;
2390			clock-names = "core", "iface";
2391			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2392			dma-names = "tx", "rx";
2393			pinctrl-names = "default";
2394			pinctrl-0 = <&blsp1_spi3_default>;
2395
2396			status = "disabled";
2397			#address-cells = <1>;
2398			#size-cells = <0>;
2399		};
2400
2401		blsp1_spi4: spi@c178000 {
2402			compatible = "qcom,spi-qup-v2.2.1";
2403			reg = <0x0c178000 0x600>;
2404			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2405
2406			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2407				 <&gcc GCC_BLSP1_AHB_CLK>;
2408			clock-names = "core", "iface";
2409			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2410			dma-names = "tx", "rx";
2411			pinctrl-names = "default";
2412			pinctrl-0 = <&blsp1_spi4_default>;
2413
2414			status = "disabled";
2415			#address-cells = <1>;
2416			#size-cells = <0>;
2417		};
2418
2419		blsp1_spi5: spi@c179000 {
2420			compatible = "qcom,spi-qup-v2.2.1";
2421			reg = <0x0c179000 0x600>;
2422			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2423
2424			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2425				 <&gcc GCC_BLSP1_AHB_CLK>;
2426			clock-names = "core", "iface";
2427			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2428			dma-names = "tx", "rx";
2429			pinctrl-names = "default";
2430			pinctrl-0 = <&blsp1_spi5_default>;
2431
2432			status = "disabled";
2433			#address-cells = <1>;
2434			#size-cells = <0>;
2435		};
2436
2437		blsp1_spi6: spi@c17a000 {
2438			compatible = "qcom,spi-qup-v2.2.1";
2439			reg = <0x0c17a000 0x600>;
2440			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2441
2442			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2443				 <&gcc GCC_BLSP1_AHB_CLK>;
2444			clock-names = "core", "iface";
2445			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2446			dma-names = "tx", "rx";
2447			pinctrl-names = "default";
2448			pinctrl-0 = <&blsp1_spi6_default>;
2449
2450			status = "disabled";
2451			#address-cells = <1>;
2452			#size-cells = <0>;
2453		};
2454
2455		blsp2_dma: dma-controller@c184000 {
2456			compatible = "qcom,bam-v1.7.0";
2457			reg = <0x0c184000 0x25000>;
2458			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2459			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2460			clock-names = "bam_clk";
2461			#dma-cells = <1>;
2462			qcom,ee = <0>;
2463			qcom,controlled-remotely;
2464			num-channels = <18>;
2465			qcom,num-ees = <4>;
2466		};
2467
2468		blsp2_uart1: serial@c1b0000 {
2469			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2470			reg = <0x0c1b0000 0x1000>;
2471			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2472			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2473				 <&gcc GCC_BLSP2_AHB_CLK>;
2474			clock-names = "core", "iface";
2475			status = "disabled";
2476		};
2477
2478		blsp2_i2c1: i2c@c1b5000 {
2479			compatible = "qcom,i2c-qup-v2.2.1";
2480			reg = <0x0c1b5000 0x600>;
2481			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2482
2483			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2484				 <&gcc GCC_BLSP2_AHB_CLK>;
2485			clock-names = "core", "iface";
2486			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2487			dma-names = "tx", "rx";
2488			pinctrl-names = "default", "sleep";
2489			pinctrl-0 = <&blsp2_i2c1_default>;
2490			pinctrl-1 = <&blsp2_i2c1_sleep>;
2491			clock-frequency = <400000>;
2492
2493			status = "disabled";
2494			#address-cells = <1>;
2495			#size-cells = <0>;
2496		};
2497
2498		blsp2_i2c2: i2c@c1b6000 {
2499			compatible = "qcom,i2c-qup-v2.2.1";
2500			reg = <0x0c1b6000 0x600>;
2501			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2502
2503			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2504				 <&gcc GCC_BLSP2_AHB_CLK>;
2505			clock-names = "core", "iface";
2506			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2507			dma-names = "tx", "rx";
2508			pinctrl-names = "default", "sleep";
2509			pinctrl-0 = <&blsp2_i2c2_default>;
2510			pinctrl-1 = <&blsp2_i2c2_sleep>;
2511			clock-frequency = <400000>;
2512
2513			status = "disabled";
2514			#address-cells = <1>;
2515			#size-cells = <0>;
2516		};
2517
2518		blsp2_i2c3: i2c@c1b7000 {
2519			compatible = "qcom,i2c-qup-v2.2.1";
2520			reg = <0x0c1b7000 0x600>;
2521			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2522
2523			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2524				 <&gcc GCC_BLSP2_AHB_CLK>;
2525			clock-names = "core", "iface";
2526			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2527			dma-names = "tx", "rx";
2528			pinctrl-names = "default", "sleep";
2529			pinctrl-0 = <&blsp2_i2c3_default>;
2530			pinctrl-1 = <&blsp2_i2c3_sleep>;
2531			clock-frequency = <400000>;
2532
2533			status = "disabled";
2534			#address-cells = <1>;
2535			#size-cells = <0>;
2536		};
2537
2538		blsp2_i2c4: i2c@c1b8000 {
2539			compatible = "qcom,i2c-qup-v2.2.1";
2540			reg = <0x0c1b8000 0x600>;
2541			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2542
2543			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2544				 <&gcc GCC_BLSP2_AHB_CLK>;
2545			clock-names = "core", "iface";
2546			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2547			dma-names = "tx", "rx";
2548			pinctrl-names = "default", "sleep";
2549			pinctrl-0 = <&blsp2_i2c4_default>;
2550			pinctrl-1 = <&blsp2_i2c4_sleep>;
2551			clock-frequency = <400000>;
2552
2553			status = "disabled";
2554			#address-cells = <1>;
2555			#size-cells = <0>;
2556		};
2557
2558		blsp2_i2c5: i2c@c1b9000 {
2559			compatible = "qcom,i2c-qup-v2.2.1";
2560			reg = <0x0c1b9000 0x600>;
2561			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2562
2563			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2564				 <&gcc GCC_BLSP2_AHB_CLK>;
2565			clock-names = "core", "iface";
2566			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2567			dma-names = "tx", "rx";
2568			pinctrl-names = "default", "sleep";
2569			pinctrl-0 = <&blsp2_i2c5_default>;
2570			pinctrl-1 = <&blsp2_i2c5_sleep>;
2571			clock-frequency = <400000>;
2572
2573			status = "disabled";
2574			#address-cells = <1>;
2575			#size-cells = <0>;
2576		};
2577
2578		blsp2_i2c6: i2c@c1ba000 {
2579			compatible = "qcom,i2c-qup-v2.2.1";
2580			reg = <0x0c1ba000 0x600>;
2581			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2582
2583			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2584				 <&gcc GCC_BLSP2_AHB_CLK>;
2585			clock-names = "core", "iface";
2586			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2587			dma-names = "tx", "rx";
2588			pinctrl-names = "default", "sleep";
2589			pinctrl-0 = <&blsp2_i2c6_default>;
2590			pinctrl-1 = <&blsp2_i2c6_sleep>;
2591			clock-frequency = <400000>;
2592
2593			status = "disabled";
2594			#address-cells = <1>;
2595			#size-cells = <0>;
2596		};
2597
2598		blsp2_spi1: spi@c1b5000 {
2599			compatible = "qcom,spi-qup-v2.2.1";
2600			reg = <0x0c1b5000 0x600>;
2601			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2602
2603			clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2604				 <&gcc GCC_BLSP2_AHB_CLK>;
2605			clock-names = "core", "iface";
2606			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2607			dma-names = "tx", "rx";
2608			pinctrl-names = "default";
2609			pinctrl-0 = <&blsp2_spi1_default>;
2610
2611			status = "disabled";
2612			#address-cells = <1>;
2613			#size-cells = <0>;
2614		};
2615
2616		blsp2_spi2: spi@c1b6000 {
2617			compatible = "qcom,spi-qup-v2.2.1";
2618			reg = <0x0c1b6000 0x600>;
2619			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2620
2621			clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2622				 <&gcc GCC_BLSP2_AHB_CLK>;
2623			clock-names = "core", "iface";
2624			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2625			dma-names = "tx", "rx";
2626			pinctrl-names = "default";
2627			pinctrl-0 = <&blsp2_spi2_default>;
2628
2629			status = "disabled";
2630			#address-cells = <1>;
2631			#size-cells = <0>;
2632		};
2633
2634		blsp2_spi3: spi@c1b7000 {
2635			compatible = "qcom,spi-qup-v2.2.1";
2636			reg = <0x0c1b7000 0x600>;
2637			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2638
2639			clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2640				 <&gcc GCC_BLSP2_AHB_CLK>;
2641			clock-names = "core", "iface";
2642			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2643			dma-names = "tx", "rx";
2644			pinctrl-names = "default";
2645			pinctrl-0 = <&blsp2_spi3_default>;
2646
2647			status = "disabled";
2648			#address-cells = <1>;
2649			#size-cells = <0>;
2650		};
2651
2652		blsp2_spi4: spi@c1b8000 {
2653			compatible = "qcom,spi-qup-v2.2.1";
2654			reg = <0x0c1b8000 0x600>;
2655			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2656
2657			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2658				 <&gcc GCC_BLSP2_AHB_CLK>;
2659			clock-names = "core", "iface";
2660			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2661			dma-names = "tx", "rx";
2662			pinctrl-names = "default";
2663			pinctrl-0 = <&blsp2_spi4_default>;
2664
2665			status = "disabled";
2666			#address-cells = <1>;
2667			#size-cells = <0>;
2668		};
2669
2670		blsp2_spi5: spi@c1b9000 {
2671			compatible = "qcom,spi-qup-v2.2.1";
2672			reg = <0x0c1b9000 0x600>;
2673			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2674
2675			clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2676				 <&gcc GCC_BLSP2_AHB_CLK>;
2677			clock-names = "core", "iface";
2678			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2679			dma-names = "tx", "rx";
2680			pinctrl-names = "default";
2681			pinctrl-0 = <&blsp2_spi5_default>;
2682
2683			status = "disabled";
2684			#address-cells = <1>;
2685			#size-cells = <0>;
2686		};
2687
2688		blsp2_spi6: spi@c1ba000 {
2689			compatible = "qcom,spi-qup-v2.2.1";
2690			reg = <0x0c1ba000 0x600>;
2691			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2692
2693			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2694				 <&gcc GCC_BLSP2_AHB_CLK>;
2695			clock-names = "core", "iface";
2696			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2697			dma-names = "tx", "rx";
2698			pinctrl-names = "default";
2699			pinctrl-0 = <&blsp2_spi6_default>;
2700
2701			status = "disabled";
2702			#address-cells = <1>;
2703			#size-cells = <0>;
2704		};
2705
2706		mmcc: clock-controller@c8c0000 {
2707			compatible = "qcom,mmcc-msm8998";
2708			#clock-cells = <1>;
2709			#reset-cells = <1>;
2710			#power-domain-cells = <1>;
2711			reg = <0xc8c0000 0x40000>;
2712
2713			clock-names = "xo",
2714				      "gpll0",
2715				      "dsi0dsi",
2716				      "dsi0byte",
2717				      "dsi1dsi",
2718				      "dsi1byte",
2719				      "hdmipll",
2720				      "dplink",
2721				      "dpvco";
2722			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2723				 <&gcc GCC_MMSS_GPLL0_CLK>,
2724				 <0>,
2725				 <0>,
2726				 <0>,
2727				 <0>,
2728				 <0>,
2729				 <0>,
2730				 <0>;
2731		};
2732
2733		mmss_smmu: iommu@cd00000 {
2734			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
2735			reg = <0x0cd00000 0x40000>;
2736			#iommu-cells = <1>;
2737
2738			clocks = <&mmcc MNOC_AHB_CLK>,
2739				 <&mmcc BIMC_SMMU_AHB_CLK>,
2740				 <&rpmcc RPM_SMD_MMAXI_CLK>,
2741				 <&mmcc BIMC_SMMU_AXI_CLK>;
2742			clock-names = "iface-mm", "iface-smmu",
2743				      "bus-mm", "bus-smmu";
2744
2745			#global-interrupts = <0>;
2746			interrupts =
2747				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2748				<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2749				<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2750				<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2751				<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2752				<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2753				<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2754				<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2755				<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2756				<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2757				<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2758				<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2759				<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2760				<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2761				<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2762				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2763				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2764				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2765				<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2766				<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2767		};
2768
2769		remoteproc_adsp: remoteproc@17300000 {
2770			compatible = "qcom,msm8998-adsp-pas";
2771			reg = <0x17300000 0x4040>;
2772
2773			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2774					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2775					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2776					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2777					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2778			interrupt-names = "wdog", "fatal", "ready",
2779					  "handover", "stop-ack";
2780
2781			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2782			clock-names = "xo";
2783
2784			memory-region = <&adsp_mem>;
2785
2786			qcom,smem-states = <&adsp_smp2p_out 0>;
2787			qcom,smem-state-names = "stop";
2788
2789			power-domains = <&rpmpd MSM8998_VDDCX>;
2790			power-domain-names = "cx";
2791
2792			status = "disabled";
2793
2794			glink-edge {
2795				interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2796				label = "lpass";
2797				qcom,remote-pid = <2>;
2798				mboxes = <&apcs_glb 9>;
2799			};
2800		};
2801
2802		apcs_glb: mailbox@17911000 {
2803			compatible = "qcom,msm8998-apcs-hmss-global",
2804				     "qcom,msm8994-apcs-kpss-global";
2805			reg = <0x17911000 0x1000>;
2806
2807			#mbox-cells = <1>;
2808		};
2809
2810		timer@17920000 {
2811			#address-cells = <1>;
2812			#size-cells = <1>;
2813			ranges;
2814			compatible = "arm,armv7-timer-mem";
2815			reg = <0x17920000 0x1000>;
2816
2817			frame@17921000 {
2818				frame-number = <0>;
2819				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2820					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2821				reg = <0x17921000 0x1000>,
2822				      <0x17922000 0x1000>;
2823			};
2824
2825			frame@17923000 {
2826				frame-number = <1>;
2827				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2828				reg = <0x17923000 0x1000>;
2829				status = "disabled";
2830			};
2831
2832			frame@17924000 {
2833				frame-number = <2>;
2834				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2835				reg = <0x17924000 0x1000>;
2836				status = "disabled";
2837			};
2838
2839			frame@17925000 {
2840				frame-number = <3>;
2841				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2842				reg = <0x17925000 0x1000>;
2843				status = "disabled";
2844			};
2845
2846			frame@17926000 {
2847				frame-number = <4>;
2848				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2849				reg = <0x17926000 0x1000>;
2850				status = "disabled";
2851			};
2852
2853			frame@17927000 {
2854				frame-number = <5>;
2855				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2856				reg = <0x17927000 0x1000>;
2857				status = "disabled";
2858			};
2859
2860			frame@17928000 {
2861				frame-number = <6>;
2862				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2863				reg = <0x17928000 0x1000>;
2864				status = "disabled";
2865			};
2866		};
2867
2868		intc: interrupt-controller@17a00000 {
2869			compatible = "arm,gic-v3";
2870			reg = <0x17a00000 0x10000>,       /* GICD */
2871			      <0x17b00000 0x100000>;      /* GICR * 8 */
2872			#interrupt-cells = <3>;
2873			#address-cells = <1>;
2874			#size-cells = <1>;
2875			ranges;
2876			interrupt-controller;
2877			#redistributor-regions = <1>;
2878			redistributor-stride = <0x0 0x20000>;
2879			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2880		};
2881
2882		wifi: wifi@18800000 {
2883			compatible = "qcom,wcn3990-wifi";
2884			status = "disabled";
2885			reg = <0x18800000 0x800000>;
2886			reg-names = "membase";
2887			memory-region = <&wlan_msa_mem>;
2888			clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
2889			clock-names = "cxo_ref_clk_pin";
2890			interrupts =
2891				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2892				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2893				<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2894				<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2895				<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2896				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2897				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2898				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2899				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2900				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2901				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2902				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2903			iommus = <&anoc2_smmu 0x1900>,
2904				 <&anoc2_smmu 0x1901>;
2905			qcom,snoc-host-cap-8bit-quirk;
2906		};
2907	};
2908};
2909