1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sc7280 fragment for devices with Chrome bootloader
4 *
5 * This file mainly tries to abstract out the memory protections put into
6 * place by the Chrome bootloader which are different than what's put into
7 * place by Qualcomm's typical bootloader. It also has a smattering of other
8 * things that will hold true for any conceivable Chrome design
9 *
10 * Copyright 2022 Google LLC.
11 */
12
13/*
14 * Reserved memory changes
15 *
16 * Delete all unused memory nodes and define the peripheral memory regions
17 * required by the setup for Chrome boards.
18 */
19
20/delete-node/ &hyp_mem;
21/delete-node/ &xbl_mem;
22/delete-node/ &reserved_xbl_uefi_log;
23/delete-node/ &sec_apps_mem;
24
25/ {
26	reserved-memory {
27		adsp_mem: memory@86700000 {
28			reg = <0x0 0x86700000 0x0 0x2800000>;
29			no-map;
30		};
31
32		camera_mem: memory@8ad00000 {
33			reg = <0x0 0x8ad00000 0x0 0x500000>;
34			no-map;
35		};
36
37		venus_mem: memory@8b200000 {
38			reg = <0x0 0x8b200000 0x0 0x500000>;
39			no-map;
40		};
41
42		wpss_mem: memory@9ae00000 {
43			reg = <0x0 0x9ae00000 0x0 0x1900000>;
44			no-map;
45		};
46	};
47};
48
49/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
50&pmk8350_pon {
51	status = "disabled";
52};
53
54/*
55 * Chrome designs always boot from SPI flash hooked up to the qspi.
56 *
57 * It's expected that all boards will support "dual SPI" at 37.5 MHz.
58 * If some boards need a different speed or have a package that allows
59 * Quad SPI together with WP then those boards can easily override.
60 */
61&qspi {
62	status = "okay";
63	pinctrl-names = "default", "sleep";
64	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
65	pinctrl-1 = <&qspi_sleep>;
66
67	spi_flash: flash@0 {
68		compatible = "jedec,spi-nor";
69		reg = <0>;
70
71		spi-max-frequency = <37500000>;
72		spi-tx-bus-width = <2>;
73		spi-rx-bus-width = <2>;
74	};
75};
76
77&remoteproc_wpss {
78	status = "okay";
79	firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
80};
81
82&scm {
83	/* TF-A firmware maps memory cached so mark dma-coherent to match. */
84	dma-coherent;
85};
86
87&wifi {
88	status = "okay";
89
90	wifi-firmware {
91		iommus = <&apps_smmu 0x1c02 0x1>;
92	};
93};
94
95/* PINCTRL - chrome-common pinctrl */
96
97&tlmm {
98	qspi_sleep: qspi-sleep-state {
99		pins = "gpio12", "gpio13", "gpio14", "gpio15";
100
101		/*
102		 * When we're not actively transferring we want pins as GPIOs
103		 * with output disabled so that the quad SPI IP block stops
104		 * driving them. We rely on the normal pulls configured in
105		 * the active state and don't redefine them here. Also note
106		 * that we don't need the reverse (output-enable) in the
107		 * normal mode since the "output-enable" only matters for
108		 * GPIO function.
109		 */
110		function = "gpio";
111		output-disable;
112	};
113};
114