1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sc7280 CRD 3+ board device tree source
4 *
5 * Copyright 2022 Google LLC.
6 */
7
8/dts-v1/;
9
10#include "sc7280-herobrine.dtsi"
11#include "sc7280-herobrine-audio-wcd9385.dtsi"
12#include "sc7280-herobrine-lte-sku.dtsi"
13
14/ {
15	model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
16	compatible = "google,zoglin", "google,hoglin", "qcom,sc7280";
17
18	/* FIXED REGULATORS */
19
20	/*
21	 * On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL.
22	 * However, on CRD there's an extra regulator in the way. Since this
23	 * is expected to be uncommon, we'll leave the "vreg_edp_bl" label
24	 * in the baseboard herobrine.dtsi point at "ppvar_sys" and then
25	 * make a "_crd" specific version here.
26	 */
27	vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
28		compatible = "regulator-fixed";
29		regulator-name = "vreg_edp_bl_crd";
30
31		gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>;
32		enable-active-high;
33		pinctrl-names = "default";
34		pinctrl-0 = <&edp_bl_reg_en>;
35
36		vin-supply = <&ppvar_sys>;
37	};
38};
39
40/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
41
42&apps_rsc {
43	regulators-2 {
44		compatible = "qcom,pmg1110-rpmh-regulators";
45		qcom,pmic-id = "k";
46
47		vreg_s1k_1p0: smps1 {
48			regulator-min-microvolt = <1010000>;
49			regulator-max-microvolt = <1170000>;
50		};
51	};
52};
53
54ap_tp_i2c: &i2c0 {
55	status = "okay";
56	clock-frequency = <400000>;
57
58	trackpad: trackpad@15 {
59		compatible = "hid-over-i2c";
60		reg = <0x15>;
61		pinctrl-names = "default";
62		pinctrl-0 = <&tp_int_odl>;
63
64		interrupt-parent = <&tlmm>;
65		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
66
67		post-power-on-delay-ms = <20>;
68		hid-descr-addr = <0x0001>;
69		vdd-supply = <&pp3300_z1>;
70
71		wakeup-source;
72	};
73};
74
75&ap_sar_sensor_i2c {
76	status = "okay";
77};
78
79&ap_sar_sensor0 {
80	status = "okay";
81};
82
83&ap_sar_sensor1 {
84	status = "okay";
85};
86
87ap_ts_pen_1v8: &i2c13 {
88	status = "okay";
89	clock-frequency = <400000>;
90
91	ap_ts: touchscreen@5c {
92		compatible = "hid-over-i2c";
93		reg = <0x5c>;
94		pinctrl-names = "default";
95		pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
96
97		interrupt-parent = <&tlmm>;
98		interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
99
100		post-power-on-delay-ms = <500>;
101		hid-descr-addr = <0x0000>;
102
103		vdd-supply = <&pp3300_left_in_mlb>;
104	};
105};
106
107&mdss_edp {
108	status = "okay";
109};
110
111&mdss_edp_phy {
112	status = "okay";
113};
114
115/* For nvme */
116&pcie1 {
117	status = "okay";
118};
119
120/* For nvme */
121&pcie1_phy {
122	status = "okay";
123};
124
125&pm8350c_pwm_backlight {
126	power-supply = <&vreg_edp_bl_crd>;
127};
128
129/* For eMMC */
130&sdhc_1 {
131	status = "okay";
132};
133
134/* For SD Card */
135&sdhc_2 {
136	status = "okay";
137};
138
139/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
140
141/*
142 * This pin goes to the display panel but then doesn't actually do anything
143 * on the panel itself (it doesn't connect to the touchscreen controller).
144 * We'll set a pullup here just to park the line.
145 */
146&ts_rst_conn {
147	bias-pull-up;
148};
149
150/* PINCTRL - BOARD-SPECIFIC */
151
152/*
153 * Methodology for gpio-line-names:
154 * - If a pin goes to CRD board and is named it gets that name.
155 * - If a pin goes to CRD board and is not named, it gets no name.
156 * - If a pin is totally internal to Qcard then it gets Qcard name.
157 * - If a pin is not hooked up on Qcard, it gets no name.
158 */
159
160&pm8350c_gpios {
161	gpio-line-names = "FLASH_STROBE_1",		/* 1 */
162			  "AP_SUSPEND",
163			  "PM8008_1_RST_N",
164			  "",
165			  "",
166			  "EDP_BL_REG_EN",
167			  "PMIC_EDP_BL_EN",
168			  "PMIC_EDP_BL_PWM",
169			  "";
170
171	edp_bl_reg_en: edp-bl-reg-en-state {
172		pins = "gpio6";
173		function = "normal";
174		bias-disable;
175		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
176	};
177};
178
179&tlmm {
180	gpio-line-names = "AP_TP_I2C_SDA",		/* 0 */
181			  "AP_TP_I2C_SCL",
182			  "PCIE1_RESET_N",
183			  "PCIE1_WAKE_N",
184			  "APPS_I2C_SDA",
185			  "APPS_I2C_SCL",
186			  "",
187			  "TPAD_INT_N",
188			  "",
189			  "",
190
191			  "GNSS_L1_EN",			/* 10 */
192			  "GNSS_L5_EN",
193			  "QSPI_DATA_0",
194			  "QSPI_DATA_1",
195			  "QSPI_CLK",
196			  "QSPI_CS_N_1",
197			  /*
198			   * AP_FLASH_WP is crossystem ABI. Schematics call it
199			   * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the
200			   * signal is active high).
201			   */
202			  "AP_FLASH_WP",
203			  "",
204			  "AP_EC_INT_N",
205			  "",
206
207			  "CAM0_RST_N",			/* 20 */
208			  "CAM1_RST_N",
209			  "SM_DBG_UART_TX",
210			  "SM_DBG_UART_RX",
211			  "",
212			  "PM8008_IRQ_1",
213			  "HOST2WLAN_SOL",
214			  "WLAN2HOST_SOL",
215			  "MOS_BT_UART_CTS",
216			  "MOS_BT_UART_RFR",
217
218			  "MOS_BT_UART_TX",		/* 30 */
219			  "MOS_BT_UART_RX",
220			  "",
221			  "HUB_RST",
222			  "",
223			  "",
224			  "",
225			  "",
226			  "",
227			  "",
228
229			  "EC_SPI_MISO_GPIO40",		/* 40 */
230			  "EC_SPI_MOSI_GPIO41",
231			  "EC_SPI_CLK_GPIO42",
232			  "EC_SPI_CS_GPIO43",
233			  "",
234			  "EARLY_EUD_EN",
235			  "",
236			  "DP_HOT_PLUG_DETECT",
237			  "AP_BRD_ID_0",
238			  "AP_BRD_ID_1",
239
240			  "AP_BRD_ID_2",		/* 50 */
241			  "NVME_PWR_REG_EN",
242			  "TS_I2C_SDA_CONN",
243			  "TS_I2C_CLK_CONN",
244			  "TS_RST_CONN",
245			  "TS_INT_CONN",
246			  "AP_I2C_TPM_SDA",
247			  "AP_I2C_TPM_SCL",
248			  "",
249			  "",
250
251			  "EDP_HOT_PLUG_DET_N",		/* 60 */
252			  "",
253			  "",
254			  "AMP_EN",
255			  "CAM0_MCLK_GPIO_64",
256			  "CAM1_MCLK_GPIO_65",
257			  "",
258			  "",
259			  "",
260			  "CCI_I2C_SDA0",
261
262			  "CCI_I2C_SCL0",		/* 70 */
263			  "",
264			  "",
265			  "",
266			  "",
267			  "",
268			  "",
269			  "",
270			  "",
271			  "PCIE1_CLK_REQ_N",
272
273			  "EN_PP3300_DX_EDP",		/* 80 */
274			  "US_EURO_HS_SEL",
275			  "FORCED_USB_BOOT",
276			  "WCD_RESET_N",
277			  "MOS_WLAN_EN",
278			  "MOS_BT_EN",
279			  "MOS_SW_CTRL",
280			  "MOS_PCIE0_RST",
281			  "MOS_PCIE0_CLKREQ_N",
282			  "MOS_PCIE0_WAKE_N",
283
284			  "MOS_LAA_AS_EN",		/* 90 */
285			  "SD_CARD_DET_CONN",
286			  "",
287			  "",
288			  "MOS_BT_WLAN_SLIMBUS_CLK",
289			  "MOS_BT_WLAN_SLIMBUS_DAT0",
290			  "",
291			  "",
292			  "",
293			  "",
294
295			  "",				/* 100 */
296			  "",
297			  "",
298			  "",
299			  "H1_AP_INT_N",
300			  "",
301			  "AMP_BCLK",
302			  "AMP_DIN",
303			  "AMP_LRCLK",
304			  "UIM1_DATA_GPIO_109",
305
306			  "UIM1_CLK_GPIO_110",		/* 110 */
307			  "UIM1_RESET_GPIO_111",
308			  "",
309			  "UIM1_DATA",
310			  "UIM1_CLK",
311			  "UIM1_RESET",
312			  "UIM1_PRESENT",
313			  "SDM_RFFE0_CLK",
314			  "SDM_RFFE0_DATA",
315			  "",
316
317			  "SDM_RFFE1_DATA",		/* 120 */
318			  "SC_GPIO_121",
319			  "FASTBOOT_SEL_1",
320			  "SC_GPIO_123",
321			  "FASTBOOT_SEL_2",
322			  "SM_RFFE4_CLK_GRFC_8",
323			  "SM_RFFE4_DATA_GRFC_9",
324			  "WLAN_COEX_UART1_RX",
325			  "WLAN_COEX_UART1_TX",
326			  "",
327
328			  "",				/* 130 */
329			  "",
330			  "",
331			  "SDR_QLINK_REQ",
332			  "SDR_QLINK_EN",
333			  "QLINK0_WMSS_RESET_N",
334			  "SMR526_QLINK1_REQ",
335			  "SMR526_QLINK1_EN",
336			  "SMR526_QLINK1_WMSS_RESET_N",
337			  "",
338
339			  "SAR1_INT_N",			/* 140 */
340			  "SAR0_INT_N",
341			  "",
342			  "",
343			  "WCD_SWR_TX_CLK",
344			  "WCD_SWR_TX_DATA0",
345			  "WCD_SWR_TX_DATA1",
346			  "WCD_SWR_RX_CLK",
347			  "WCD_SWR_RX_DATA0",
348			  "WCD_SWR_RX_DATA1",
349
350			  "DMIC01_CLK",			/* 150 */
351			  "DMIC01_DATA",
352			  "DMIC23_CLK",
353			  "DMIC23_DATA",
354			  "",
355			  "",
356			  "EC_IN_RW_N",
357			  "EN_PP3300_HUB",
358			  "WCD_SWR_TX_DATA2",
359			  "",
360
361			  "",				/* 160 */
362			  "",
363			  "",
364			  "",
365			  "",
366			  "",
367			  "",
368			  "",
369			  "",
370			  "",
371
372			  "",				/* 170 */
373			  "MOS_BLE_UART_TX",
374			  "MOS_BLE_UART_RX",
375			  "",
376			  "";
377};
378