1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sc8280xp.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6afe.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 clocks { 30 xo_board_clk: xo-board-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a78c"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <602>; 53 next-level-cache = <&L2_0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 59 #cooling-cells = <2>; 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a78c"; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 78 enable-method = "psci"; 79 capacity-dmips-mhz = <602>; 80 next-level-cache = <&L2_100>; 81 power-domains = <&CPU_PD1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 86 #cooling-cells = <2>; 87 L2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&L3_0>; 92 }; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a78c"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <602>; 102 next-level-cache = <&L2_200>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 108 #cooling-cells = <2>; 109 L2_200: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a78c"; 120 reg = <0x0 0x300>; 121 clocks = <&cpufreq_hw 0>; 122 enable-method = "psci"; 123 capacity-dmips-mhz = <602>; 124 next-level-cache = <&L2_300>; 125 power-domains = <&CPU_PD3>; 126 power-domain-names = "psci"; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 operating-points-v2 = <&cpu0_opp_table>; 129 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 130 #cooling-cells = <2>; 131 L2_300: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU4: cpu@400 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-x1c"; 142 reg = <0x0 0x400>; 143 clocks = <&cpufreq_hw 1>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 next-level-cache = <&L2_400>; 147 power-domains = <&CPU_PD4>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 operating-points-v2 = <&cpu4_opp_table>; 151 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 152 #cooling-cells = <2>; 153 L2_400: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU5: cpu@500 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-x1c"; 164 reg = <0x0 0x500>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <1024>; 168 next-level-cache = <&L2_500>; 169 power-domains = <&CPU_PD5>; 170 power-domain-names = "psci"; 171 qcom,freq-domain = <&cpufreq_hw 1>; 172 operating-points-v2 = <&cpu4_opp_table>; 173 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 174 #cooling-cells = <2>; 175 L2_500: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 next-level-cache = <&L3_0>; 180 }; 181 }; 182 183 CPU6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-x1c"; 186 reg = <0x0 0x600>; 187 clocks = <&cpufreq_hw 1>; 188 enable-method = "psci"; 189 capacity-dmips-mhz = <1024>; 190 next-level-cache = <&L2_600>; 191 power-domains = <&CPU_PD6>; 192 power-domain-names = "psci"; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 operating-points-v2 = <&cpu4_opp_table>; 195 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 196 #cooling-cells = <2>; 197 L2_600: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU7: cpu@700 { 206 device_type = "cpu"; 207 compatible = "arm,cortex-x1c"; 208 reg = <0x0 0x700>; 209 clocks = <&cpufreq_hw 1>; 210 enable-method = "psci"; 211 capacity-dmips-mhz = <1024>; 212 next-level-cache = <&L2_700>; 213 power-domains = <&CPU_PD7>; 214 power-domain-names = "psci"; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu4_opp_table>; 217 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 218 #cooling-cells = <2>; 219 L2_700: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 cpu-map { 228 cluster0 { 229 core0 { 230 cpu = <&CPU0>; 231 }; 232 233 core1 { 234 cpu = <&CPU1>; 235 }; 236 237 core2 { 238 cpu = <&CPU2>; 239 }; 240 241 core3 { 242 cpu = <&CPU3>; 243 }; 244 245 core4 { 246 cpu = <&CPU4>; 247 }; 248 249 core5 { 250 cpu = <&CPU5>; 251 }; 252 253 core6 { 254 cpu = <&CPU6>; 255 }; 256 257 core7 { 258 cpu = <&CPU7>; 259 }; 260 }; 261 }; 262 263 idle-states { 264 entry-method = "psci"; 265 266 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 267 compatible = "arm,idle-state"; 268 idle-state-name = "little-rail-power-collapse"; 269 arm,psci-suspend-param = <0x40000004>; 270 entry-latency-us = <355>; 271 exit-latency-us = <909>; 272 min-residency-us = <3934>; 273 local-timer-stop; 274 }; 275 276 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "big-rail-power-collapse"; 279 arm,psci-suspend-param = <0x40000004>; 280 entry-latency-us = <241>; 281 exit-latency-us = <1461>; 282 min-residency-us = <4488>; 283 local-timer-stop; 284 }; 285 }; 286 287 domain-idle-states { 288 CLUSTER_SLEEP_0: cluster-sleep-0 { 289 compatible = "domain-idle-state"; 290 arm,psci-suspend-param = <0x4100c344>; 291 entry-latency-us = <3263>; 292 exit-latency-us = <6562>; 293 min-residency-us = <9987>; 294 }; 295 }; 296 }; 297 298 firmware { 299 scm: scm { 300 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 301 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 302 }; 303 }; 304 305 aggre1_noc: interconnect-aggre1-noc { 306 compatible = "qcom,sc8280xp-aggre1-noc"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 aggre2_noc: interconnect-aggre2-noc { 312 compatible = "qcom,sc8280xp-aggre2-noc"; 313 #interconnect-cells = <2>; 314 qcom,bcm-voters = <&apps_bcm_voter>; 315 }; 316 317 clk_virt: interconnect-clk-virt { 318 compatible = "qcom,sc8280xp-clk-virt"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 config_noc: interconnect-config-noc { 324 compatible = "qcom,sc8280xp-config-noc"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 dc_noc: interconnect-dc-noc { 330 compatible = "qcom,sc8280xp-dc-noc"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 gem_noc: interconnect-gem-noc { 336 compatible = "qcom,sc8280xp-gem-noc"; 337 #interconnect-cells = <2>; 338 qcom,bcm-voters = <&apps_bcm_voter>; 339 }; 340 341 lpass_noc: interconnect-lpass-ag-noc { 342 compatible = "qcom,sc8280xp-lpass-ag-noc"; 343 #interconnect-cells = <2>; 344 qcom,bcm-voters = <&apps_bcm_voter>; 345 }; 346 347 mc_virt: interconnect-mc-virt { 348 compatible = "qcom,sc8280xp-mc-virt"; 349 #interconnect-cells = <2>; 350 qcom,bcm-voters = <&apps_bcm_voter>; 351 }; 352 353 mmss_noc: interconnect-mmss-noc { 354 compatible = "qcom,sc8280xp-mmss-noc"; 355 #interconnect-cells = <2>; 356 qcom,bcm-voters = <&apps_bcm_voter>; 357 }; 358 359 nspa_noc: interconnect-nspa-noc { 360 compatible = "qcom,sc8280xp-nspa-noc"; 361 #interconnect-cells = <2>; 362 qcom,bcm-voters = <&apps_bcm_voter>; 363 }; 364 365 nspb_noc: interconnect-nspb-noc { 366 compatible = "qcom,sc8280xp-nspb-noc"; 367 #interconnect-cells = <2>; 368 qcom,bcm-voters = <&apps_bcm_voter>; 369 }; 370 371 system_noc: interconnect-system-noc { 372 compatible = "qcom,sc8280xp-system-noc"; 373 #interconnect-cells = <2>; 374 qcom,bcm-voters = <&apps_bcm_voter>; 375 }; 376 377 memory@80000000 { 378 device_type = "memory"; 379 /* We expect the bootloader to fill in the size */ 380 reg = <0x0 0x80000000 0x0 0x0>; 381 }; 382 383 cpu0_opp_table: opp-table-cpu0 { 384 compatible = "operating-points-v2"; 385 opp-shared; 386 387 opp-300000000 { 388 opp-hz = /bits/ 64 <300000000>; 389 opp-peak-kBps = <(300000 * 32)>; 390 }; 391 opp-403200000 { 392 opp-hz = /bits/ 64 <403200000>; 393 opp-peak-kBps = <(384000 * 32)>; 394 }; 395 opp-499200000 { 396 opp-hz = /bits/ 64 <499200000>; 397 opp-peak-kBps = <(480000 * 32)>; 398 }; 399 opp-595200000 { 400 opp-hz = /bits/ 64 <595200000>; 401 opp-peak-kBps = <(576000 * 32)>; 402 }; 403 opp-691200000 { 404 opp-hz = /bits/ 64 <691200000>; 405 opp-peak-kBps = <(672000 * 32)>; 406 }; 407 opp-806400000 { 408 opp-hz = /bits/ 64 <806400000>; 409 opp-peak-kBps = <(768000 * 32)>; 410 }; 411 opp-902400000 { 412 opp-hz = /bits/ 64 <902400000>; 413 opp-peak-kBps = <(864000 * 32)>; 414 }; 415 opp-1017600000 { 416 opp-hz = /bits/ 64 <1017600000>; 417 opp-peak-kBps = <(960000 * 32)>; 418 }; 419 opp-1113600000 { 420 opp-hz = /bits/ 64 <1113600000>; 421 opp-peak-kBps = <(1075200 * 32)>; 422 }; 423 opp-1209600000 { 424 opp-hz = /bits/ 64 <1209600000>; 425 opp-peak-kBps = <(1171200 * 32)>; 426 }; 427 opp-1324800000 { 428 opp-hz = /bits/ 64 <1324800000>; 429 opp-peak-kBps = <(1267200 * 32)>; 430 }; 431 opp-1440000000 { 432 opp-hz = /bits/ 64 <1440000000>; 433 opp-peak-kBps = <(1363200 * 32)>; 434 }; 435 opp-1555200000 { 436 opp-hz = /bits/ 64 <1555200000>; 437 opp-peak-kBps = <(1536000 * 32)>; 438 }; 439 opp-1670400000 { 440 opp-hz = /bits/ 64 <1670400000>; 441 opp-peak-kBps = <(1612800 * 32)>; 442 }; 443 opp-1785600000 { 444 opp-hz = /bits/ 64 <1785600000>; 445 opp-peak-kBps = <(1689600 * 32)>; 446 }; 447 opp-1881600000 { 448 opp-hz = /bits/ 64 <1881600000>; 449 opp-peak-kBps = <(1689600 * 32)>; 450 }; 451 opp-1996800000 { 452 opp-hz = /bits/ 64 <1996800000>; 453 opp-peak-kBps = <(1689600 * 32)>; 454 }; 455 opp-2112000000 { 456 opp-hz = /bits/ 64 <2112000000>; 457 opp-peak-kBps = <(1689600 * 32)>; 458 }; 459 opp-2227200000 { 460 opp-hz = /bits/ 64 <2227200000>; 461 opp-peak-kBps = <(1689600 * 32)>; 462 }; 463 opp-2342400000 { 464 opp-hz = /bits/ 64 <2342400000>; 465 opp-peak-kBps = <(1689600 * 32)>; 466 }; 467 opp-2438400000 { 468 opp-hz = /bits/ 64 <2438400000>; 469 opp-peak-kBps = <(1689600 * 32)>; 470 }; 471 }; 472 473 cpu4_opp_table: opp-table-cpu4 { 474 compatible = "operating-points-v2"; 475 opp-shared; 476 477 opp-825600000 { 478 opp-hz = /bits/ 64 <825600000>; 479 opp-peak-kBps = <(768000 * 32)>; 480 }; 481 opp-940800000 { 482 opp-hz = /bits/ 64 <940800000>; 483 opp-peak-kBps = <(864000 * 32)>; 484 }; 485 opp-1056000000 { 486 opp-hz = /bits/ 64 <1056000000>; 487 opp-peak-kBps = <(960000 * 32)>; 488 }; 489 opp-1171200000 { 490 opp-hz = /bits/ 64 <1171200000>; 491 opp-peak-kBps = <(1171200 * 32)>; 492 }; 493 opp-1286400000 { 494 opp-hz = /bits/ 64 <1286400000>; 495 opp-peak-kBps = <(1267200 * 32)>; 496 }; 497 opp-1401600000 { 498 opp-hz = /bits/ 64 <1401600000>; 499 opp-peak-kBps = <(1363200 * 32)>; 500 }; 501 opp-1516800000 { 502 opp-hz = /bits/ 64 <1516800000>; 503 opp-peak-kBps = <(1459200 * 32)>; 504 }; 505 opp-1632000000 { 506 opp-hz = /bits/ 64 <1632000000>; 507 opp-peak-kBps = <(1612800 * 32)>; 508 }; 509 opp-1747200000 { 510 opp-hz = /bits/ 64 <1747200000>; 511 opp-peak-kBps = <(1689600 * 32)>; 512 }; 513 opp-1862400000 { 514 opp-hz = /bits/ 64 <1862400000>; 515 opp-peak-kBps = <(1689600 * 32)>; 516 }; 517 opp-1977600000 { 518 opp-hz = /bits/ 64 <1977600000>; 519 opp-peak-kBps = <(1689600 * 32)>; 520 }; 521 opp-2073600000 { 522 opp-hz = /bits/ 64 <2073600000>; 523 opp-peak-kBps = <(1689600 * 32)>; 524 }; 525 opp-2169600000 { 526 opp-hz = /bits/ 64 <2169600000>; 527 opp-peak-kBps = <(1689600 * 32)>; 528 }; 529 opp-2284800000 { 530 opp-hz = /bits/ 64 <2284800000>; 531 opp-peak-kBps = <(1689600 * 32)>; 532 }; 533 opp-2400000000 { 534 opp-hz = /bits/ 64 <2400000000>; 535 opp-peak-kBps = <(1689600 * 32)>; 536 }; 537 opp-2496000000 { 538 opp-hz = /bits/ 64 <2496000000>; 539 opp-peak-kBps = <(1689600 * 32)>; 540 }; 541 opp-2592000000 { 542 opp-hz = /bits/ 64 <2592000000>; 543 opp-peak-kBps = <(1689600 * 32)>; 544 }; 545 opp-2688000000 { 546 opp-hz = /bits/ 64 <2688000000>; 547 opp-peak-kBps = <(1689600 * 32)>; 548 }; 549 opp-2803200000 { 550 opp-hz = /bits/ 64 <2803200000>; 551 opp-peak-kBps = <(1689600 * 32)>; 552 }; 553 opp-2899200000 { 554 opp-hz = /bits/ 64 <2899200000>; 555 opp-peak-kBps = <(1689600 * 32)>; 556 }; 557 opp-2995200000 { 558 opp-hz = /bits/ 64 <2995200000>; 559 opp-peak-kBps = <(1689600 * 32)>; 560 }; 561 }; 562 563 qup_opp_table_100mhz: opp-table-qup100mhz { 564 compatible = "operating-points-v2"; 565 566 opp-75000000 { 567 opp-hz = /bits/ 64 <75000000>; 568 required-opps = <&rpmhpd_opp_low_svs>; 569 }; 570 571 opp-100000000 { 572 opp-hz = /bits/ 64 <100000000>; 573 required-opps = <&rpmhpd_opp_svs>; 574 }; 575 }; 576 577 pmu { 578 compatible = "arm,armv8-pmuv3"; 579 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 580 }; 581 582 psci { 583 compatible = "arm,psci-1.0"; 584 method = "smc"; 585 586 CPU_PD0: power-domain-cpu0 { 587 #power-domain-cells = <0>; 588 power-domains = <&CLUSTER_PD>; 589 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 590 }; 591 592 CPU_PD1: power-domain-cpu1 { 593 #power-domain-cells = <0>; 594 power-domains = <&CLUSTER_PD>; 595 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 596 }; 597 598 CPU_PD2: power-domain-cpu2 { 599 #power-domain-cells = <0>; 600 power-domains = <&CLUSTER_PD>; 601 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 602 }; 603 604 CPU_PD3: power-domain-cpu3 { 605 #power-domain-cells = <0>; 606 power-domains = <&CLUSTER_PD>; 607 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 608 }; 609 610 CPU_PD4: power-domain-cpu4 { 611 #power-domain-cells = <0>; 612 power-domains = <&CLUSTER_PD>; 613 domain-idle-states = <&BIG_CPU_SLEEP_0>; 614 }; 615 616 CPU_PD5: power-domain-cpu5 { 617 #power-domain-cells = <0>; 618 power-domains = <&CLUSTER_PD>; 619 domain-idle-states = <&BIG_CPU_SLEEP_0>; 620 }; 621 622 CPU_PD6: power-domain-cpu6 { 623 #power-domain-cells = <0>; 624 power-domains = <&CLUSTER_PD>; 625 domain-idle-states = <&BIG_CPU_SLEEP_0>; 626 }; 627 628 CPU_PD7: power-domain-cpu7 { 629 #power-domain-cells = <0>; 630 power-domains = <&CLUSTER_PD>; 631 domain-idle-states = <&BIG_CPU_SLEEP_0>; 632 }; 633 634 CLUSTER_PD: power-domain-cpu-cluster0 { 635 #power-domain-cells = <0>; 636 domain-idle-states = <&CLUSTER_SLEEP_0>; 637 }; 638 }; 639 640 reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 reserved-region@80000000 { 646 reg = <0 0x80000000 0 0x860000>; 647 no-map; 648 }; 649 650 cmd_db: cmd-db-region@80860000 { 651 compatible = "qcom,cmd-db"; 652 reg = <0 0x80860000 0 0x20000>; 653 no-map; 654 }; 655 656 reserved-region@80880000 { 657 reg = <0 0x80880000 0 0x80000>; 658 no-map; 659 }; 660 661 smem_mem: smem-region@80900000 { 662 compatible = "qcom,smem"; 663 reg = <0 0x80900000 0 0x200000>; 664 no-map; 665 hwlocks = <&tcsr_mutex 3>; 666 }; 667 668 reserved-region@80b00000 { 669 reg = <0 0x80b00000 0 0x100000>; 670 no-map; 671 }; 672 673 reserved-region@83b00000 { 674 reg = <0 0x83b00000 0 0x1700000>; 675 no-map; 676 }; 677 678 reserved-region@85b00000 { 679 reg = <0 0x85b00000 0 0xc00000>; 680 no-map; 681 }; 682 683 pil_adsp_mem: adsp-region@86c00000 { 684 reg = <0 0x86c00000 0 0x2000000>; 685 no-map; 686 }; 687 688 pil_nsp0_mem: cdsp0-region@8a100000 { 689 reg = <0 0x8a100000 0 0x1e00000>; 690 no-map; 691 }; 692 693 pil_nsp1_mem: cdsp1-region@8c600000 { 694 reg = <0 0x8c600000 0 0x1e00000>; 695 no-map; 696 }; 697 698 reserved-region@aeb00000 { 699 reg = <0 0xaeb00000 0 0x16600000>; 700 no-map; 701 }; 702 }; 703 704 smp2p-adsp { 705 compatible = "qcom,smp2p"; 706 qcom,smem = <443>, <429>; 707 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 708 IPCC_MPROC_SIGNAL_SMP2P 709 IRQ_TYPE_EDGE_RISING>; 710 mboxes = <&ipcc IPCC_CLIENT_LPASS 711 IPCC_MPROC_SIGNAL_SMP2P>; 712 713 qcom,local-pid = <0>; 714 qcom,remote-pid = <2>; 715 716 smp2p_adsp_out: master-kernel { 717 qcom,entry-name = "master-kernel"; 718 #qcom,smem-state-cells = <1>; 719 }; 720 721 smp2p_adsp_in: slave-kernel { 722 qcom,entry-name = "slave-kernel"; 723 interrupt-controller; 724 #interrupt-cells = <2>; 725 }; 726 }; 727 728 smp2p-nsp0 { 729 compatible = "qcom,smp2p"; 730 qcom,smem = <94>, <432>; 731 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 732 IPCC_MPROC_SIGNAL_SMP2P 733 IRQ_TYPE_EDGE_RISING>; 734 mboxes = <&ipcc IPCC_CLIENT_CDSP 735 IPCC_MPROC_SIGNAL_SMP2P>; 736 737 qcom,local-pid = <0>; 738 qcom,remote-pid = <5>; 739 740 smp2p_nsp0_out: master-kernel { 741 qcom,entry-name = "master-kernel"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 smp2p_nsp0_in: slave-kernel { 746 qcom,entry-name = "slave-kernel"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 }; 751 752 smp2p-nsp1 { 753 compatible = "qcom,smp2p"; 754 qcom,smem = <617>, <616>; 755 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 756 IPCC_MPROC_SIGNAL_SMP2P 757 IRQ_TYPE_EDGE_RISING>; 758 mboxes = <&ipcc IPCC_CLIENT_NSP1 759 IPCC_MPROC_SIGNAL_SMP2P>; 760 761 qcom,local-pid = <0>; 762 qcom,remote-pid = <12>; 763 764 smp2p_nsp1_out: master-kernel { 765 qcom,entry-name = "master-kernel"; 766 #qcom,smem-state-cells = <1>; 767 }; 768 769 smp2p_nsp1_in: slave-kernel { 770 qcom,entry-name = "slave-kernel"; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 }; 774 }; 775 776 soc: soc@0 { 777 compatible = "simple-bus"; 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges = <0 0 0 0 0x10 0>; 781 dma-ranges = <0 0 0 0 0x10 0>; 782 783 ethernet0: ethernet@20000 { 784 compatible = "qcom,sc8280xp-ethqos"; 785 reg = <0x0 0x00020000 0x0 0x10000>, 786 <0x0 0x00036000 0x0 0x100>; 787 reg-names = "stmmaceth", "rgmii"; 788 789 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 790 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 791 <&gcc GCC_EMAC0_PTP_CLK>, 792 <&gcc GCC_EMAC0_RGMII_CLK>; 793 clock-names = "stmmaceth", 794 "pclk", 795 "ptp_ref", 796 "rgmii"; 797 798 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 800 interrupt-names = "macirq", "eth_lpi"; 801 802 iommus = <&apps_smmu 0x4c0 0xf>; 803 power-domains = <&gcc EMAC_0_GDSC>; 804 805 snps,tso; 806 snps,pbl = <32>; 807 rx-fifo-depth = <4096>; 808 tx-fifo-depth = <4096>; 809 810 status = "disabled"; 811 }; 812 813 gcc: clock-controller@100000 { 814 compatible = "qcom,gcc-sc8280xp"; 815 reg = <0x0 0x00100000 0x0 0x1f0000>; 816 #clock-cells = <1>; 817 #reset-cells = <1>; 818 #power-domain-cells = <1>; 819 clocks = <&rpmhcc RPMH_CXO_CLK>, 820 <&sleep_clk>, 821 <0>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 828 <0>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 836 <0>, 837 <0>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, 842 <0>, 843 <0>, 844 <0>, 845 <&pcie2a_phy>, 846 <&pcie2b_phy>, 847 <&pcie3a_phy>, 848 <&pcie3b_phy>, 849 <&pcie4_phy>, 850 <0>, 851 <0>; 852 power-domains = <&rpmhpd SC8280XP_CX>; 853 }; 854 855 ipcc: mailbox@408000 { 856 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 857 reg = <0 0x00408000 0 0x1000>; 858 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-controller; 860 #interrupt-cells = <3>; 861 #mbox-cells = <2>; 862 }; 863 864 qup2: geniqup@8c0000 { 865 compatible = "qcom,geni-se-qup"; 866 reg = <0 0x008c0000 0 0x2000>; 867 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 868 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 869 clock-names = "m-ahb", "s-ahb"; 870 iommus = <&apps_smmu 0xa3 0>; 871 872 #address-cells = <2>; 873 #size-cells = <2>; 874 ranges; 875 876 status = "disabled"; 877 878 i2c16: i2c@880000 { 879 compatible = "qcom,geni-i2c"; 880 reg = <0 0x00880000 0 0x4000>; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 884 clock-names = "se"; 885 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 886 power-domains = <&rpmhpd SC8280XP_CX>; 887 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 889 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 890 interconnect-names = "qup-core", "qup-config", "qup-memory"; 891 status = "disabled"; 892 }; 893 894 spi16: spi@880000 { 895 compatible = "qcom,geni-spi"; 896 reg = <0 0x00880000 0 0x4000>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 900 clock-names = "se"; 901 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 902 power-domains = <&rpmhpd SC8280XP_CX>; 903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 905 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 906 interconnect-names = "qup-core", "qup-config", "qup-memory"; 907 status = "disabled"; 908 }; 909 910 i2c17: i2c@884000 { 911 compatible = "qcom,geni-i2c"; 912 reg = <0 0x00884000 0 0x4000>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 916 clock-names = "se"; 917 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 918 power-domains = <&rpmhpd SC8280XP_CX>; 919 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 921 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 922 interconnect-names = "qup-core", "qup-config", "qup-memory"; 923 status = "disabled"; 924 }; 925 926 spi17: spi@884000 { 927 compatible = "qcom,geni-spi"; 928 reg = <0 0x00884000 0 0x4000>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 932 clock-names = "se"; 933 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 934 power-domains = <&rpmhpd SC8280XP_CX>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 937 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 status = "disabled"; 940 }; 941 942 uart17: serial@884000 { 943 compatible = "qcom,geni-uart"; 944 reg = <0 0x00884000 0 0x4000>; 945 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 946 clock-names = "se"; 947 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 948 operating-points-v2 = <&qup_opp_table_100mhz>; 949 power-domains = <&rpmhpd SC8280XP_CX>; 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 952 interconnect-names = "qup-core", "qup-config"; 953 status = "disabled"; 954 }; 955 956 i2c18: i2c@888000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0 0x00888000 0 0x4000>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 962 clock-names = "se"; 963 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 964 power-domains = <&rpmhpd SC8280XP_CX>; 965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 967 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 968 interconnect-names = "qup-core", "qup-config", "qup-memory"; 969 status = "disabled"; 970 }; 971 972 spi18: spi@888000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x00888000 0 0x4000>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 978 clock-names = "se"; 979 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 980 power-domains = <&rpmhpd SC8280XP_CX>; 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 982 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 983 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 984 interconnect-names = "qup-core", "qup-config", "qup-memory"; 985 status = "disabled"; 986 }; 987 988 i2c19: i2c@88c000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x0088c000 0 0x4000>; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 994 clock-names = "se"; 995 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 996 power-domains = <&rpmhpd SC8280XP_CX>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 999 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1000 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1001 status = "disabled"; 1002 }; 1003 1004 spi19: spi@88c000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0 0x0088c000 0 0x4000>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1010 clock-names = "se"; 1011 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1012 power-domains = <&rpmhpd SC8280XP_CX>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1015 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c20: i2c@890000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0 0x00890000 0 0x4000>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1026 clock-names = "se"; 1027 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1028 power-domains = <&rpmhpd SC8280XP_CX>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1031 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1032 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1033 status = "disabled"; 1034 }; 1035 1036 spi20: spi@890000 { 1037 compatible = "qcom,geni-spi"; 1038 reg = <0 0x00890000 0 0x4000>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1042 clock-names = "se"; 1043 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SC8280XP_CX>; 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1047 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1048 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1049 status = "disabled"; 1050 }; 1051 1052 i2c21: i2c@894000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0 0x00894000 0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1057 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 power-domains = <&rpmhpd SC8280XP_CX>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1063 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1064 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1065 status = "disabled"; 1066 }; 1067 1068 spi21: spi@894000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x00894000 0 0x4000>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1074 clock-names = "se"; 1075 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1076 power-domains = <&rpmhpd SC8280XP_CX>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1079 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1080 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1081 status = "disabled"; 1082 }; 1083 1084 i2c22: i2c@898000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00898000 0 0x4000>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 clock-names = "se"; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1091 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1092 power-domains = <&rpmhpd SC8280XP_CX>; 1093 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1095 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1096 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1097 status = "disabled"; 1098 }; 1099 1100 spi22: spi@898000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00898000 0 0x4000>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1106 clock-names = "se"; 1107 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1108 power-domains = <&rpmhpd SC8280XP_CX>; 1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1111 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1112 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1113 status = "disabled"; 1114 }; 1115 1116 i2c23: i2c@89c000 { 1117 compatible = "qcom,geni-i2c"; 1118 reg = <0 0x0089c000 0 0x4000>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 clock-names = "se"; 1122 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1123 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1124 power-domains = <&rpmhpd SC8280XP_CX>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1126 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1128 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1129 status = "disabled"; 1130 }; 1131 1132 spi23: spi@89c000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x0089c000 0 0x4000>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1138 clock-names = "se"; 1139 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1140 power-domains = <&rpmhpd SC8280XP_CX>; 1141 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1143 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1144 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1145 status = "disabled"; 1146 }; 1147 }; 1148 1149 qup0: geniqup@9c0000 { 1150 compatible = "qcom,geni-se-qup"; 1151 reg = <0 0x009c0000 0 0x6000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1153 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1154 clock-names = "m-ahb", "s-ahb"; 1155 iommus = <&apps_smmu 0x563 0>; 1156 1157 #address-cells = <2>; 1158 #size-cells = <2>; 1159 ranges; 1160 1161 status = "disabled"; 1162 1163 i2c0: i2c@980000 { 1164 compatible = "qcom,geni-i2c"; 1165 reg = <0 0x00980000 0 0x4000>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1170 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1171 power-domains = <&rpmhpd SC8280XP_CX>; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1173 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1174 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1175 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1176 status = "disabled"; 1177 }; 1178 1179 spi0: spi@980000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0 0x00980000 0 0x4000>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1185 clock-names = "se"; 1186 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1187 power-domains = <&rpmhpd SC8280XP_CX>; 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1189 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1190 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1191 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1192 status = "disabled"; 1193 }; 1194 1195 i2c1: i2c@984000 { 1196 compatible = "qcom,geni-i2c"; 1197 reg = <0 0x00984000 0 0x4000>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1203 power-domains = <&rpmhpd SC8280XP_CX>; 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1205 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1206 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1207 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1208 status = "disabled"; 1209 }; 1210 1211 spi1: spi@984000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0 0x00984000 0 0x4000>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1217 clock-names = "se"; 1218 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1219 power-domains = <&rpmhpd SC8280XP_CX>; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1222 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1223 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1224 status = "disabled"; 1225 }; 1226 1227 i2c2: i2c@988000 { 1228 compatible = "qcom,geni-i2c"; 1229 reg = <0 0x00988000 0 0x4000>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 clock-names = "se"; 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1234 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1235 power-domains = <&rpmhpd SC8280XP_CX>; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1238 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1239 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1240 status = "disabled"; 1241 }; 1242 1243 spi2: spi@988000 { 1244 compatible = "qcom,geni-spi"; 1245 reg = <0 0x00988000 0 0x4000>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1249 clock-names = "se"; 1250 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1251 power-domains = <&rpmhpd SC8280XP_CX>; 1252 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1254 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1255 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1256 status = "disabled"; 1257 }; 1258 1259 uart2: serial@988000 { 1260 compatible = "qcom,geni-uart"; 1261 reg = <0 0x00988000 0 0x4000>; 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1263 clock-names = "se"; 1264 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1265 operating-points-v2 = <&qup_opp_table_100mhz>; 1266 power-domains = <&rpmhpd SC8280XP_CX>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 status = "disabled"; 1271 }; 1272 1273 i2c3: i2c@98c000 { 1274 compatible = "qcom,geni-i2c"; 1275 reg = <0 0x0098c000 0 0x4000>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1280 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1281 power-domains = <&rpmhpd SC8280XP_CX>; 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1284 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1285 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1286 status = "disabled"; 1287 }; 1288 1289 spi3: spi@98c000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x0098c000 0 0x4000>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1295 clock-names = "se"; 1296 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1297 power-domains = <&rpmhpd SC8280XP_CX>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1299 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1300 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1301 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1302 status = "disabled"; 1303 }; 1304 1305 i2c4: i2c@990000 { 1306 compatible = "qcom,geni-i2c"; 1307 reg = <0 0x00990000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1310 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 power-domains = <&rpmhpd SC8280XP_CX>; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1315 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1316 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1317 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1318 status = "disabled"; 1319 }; 1320 1321 spi4: spi@990000 { 1322 compatible = "qcom,geni-spi"; 1323 reg = <0 0x00990000 0 0x4000>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1327 clock-names = "se"; 1328 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1329 power-domains = <&rpmhpd SC8280XP_CX>; 1330 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1332 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1333 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1334 status = "disabled"; 1335 }; 1336 1337 i2c5: i2c@994000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0 0x00994000 0 0x4000>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd SC8280XP_CX>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1348 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 status = "disabled"; 1351 }; 1352 1353 spi5: spi@994000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00994000 0 0x4000>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1359 clock-names = "se"; 1360 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1361 power-domains = <&rpmhpd SC8280XP_CX>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1364 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1366 status = "disabled"; 1367 }; 1368 1369 i2c6: i2c@998000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0 0x00998000 0 0x4000>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 clock-names = "se"; 1375 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1376 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1377 power-domains = <&rpmhpd SC8280XP_CX>; 1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1380 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1381 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1382 status = "disabled"; 1383 }; 1384 1385 spi6: spi@998000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00998000 0 0x4000>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1391 clock-names = "se"; 1392 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1393 power-domains = <&rpmhpd SC8280XP_CX>; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1395 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1396 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1397 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1398 status = "disabled"; 1399 }; 1400 1401 i2c7: i2c@99c000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x0099c000 0 0x4000>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 clock-names = "se"; 1407 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1408 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd SC8280XP_CX>; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1412 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1413 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1414 status = "disabled"; 1415 }; 1416 1417 spi7: spi@99c000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x0099c000 0 0x4000>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1423 clock-names = "se"; 1424 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1425 power-domains = <&rpmhpd SC8280XP_CX>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1428 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1429 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1430 status = "disabled"; 1431 }; 1432 }; 1433 1434 qup1: geniqup@ac0000 { 1435 compatible = "qcom,geni-se-qup"; 1436 reg = <0 0x00ac0000 0 0x6000>; 1437 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1438 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1439 clock-names = "m-ahb", "s-ahb"; 1440 iommus = <&apps_smmu 0x83 0>; 1441 1442 #address-cells = <2>; 1443 #size-cells = <2>; 1444 ranges; 1445 1446 status = "disabled"; 1447 1448 i2c8: i2c@a80000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x00a80000 0 0x4000>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1454 clock-names = "se"; 1455 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1456 power-domains = <&rpmhpd SC8280XP_CX>; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1459 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1460 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1461 status = "disabled"; 1462 }; 1463 1464 spi8: spi@a80000 { 1465 compatible = "qcom,geni-spi"; 1466 reg = <0 0x00a80000 0 0x4000>; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1470 clock-names = "se"; 1471 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1472 power-domains = <&rpmhpd SC8280XP_CX>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1477 status = "disabled"; 1478 }; 1479 1480 i2c9: i2c@a84000 { 1481 compatible = "qcom,geni-i2c"; 1482 reg = <0 0x00a84000 0 0x4000>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1486 clock-names = "se"; 1487 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1488 power-domains = <&rpmhpd SC8280XP_CX>; 1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1491 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1492 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1493 status = "disabled"; 1494 }; 1495 1496 spi9: spi@a84000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00a84000 0 0x4000>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1502 clock-names = "se"; 1503 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1504 power-domains = <&rpmhpd SC8280XP_CX>; 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1506 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1507 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1508 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1509 status = "disabled"; 1510 }; 1511 1512 i2c10: i2c@a88000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0 0x00a88000 0 0x4000>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1518 clock-names = "se"; 1519 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1520 power-domains = <&rpmhpd SC8280XP_CX>; 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1522 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1523 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1524 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1525 status = "disabled"; 1526 }; 1527 1528 spi10: spi@a88000 { 1529 compatible = "qcom,geni-spi"; 1530 reg = <0 0x00a88000 0 0x4000>; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1534 clock-names = "se"; 1535 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1536 power-domains = <&rpmhpd SC8280XP_CX>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1538 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1539 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1540 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1541 status = "disabled"; 1542 }; 1543 1544 i2c11: i2c@a8c000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0 0x00a8c000 0 0x4000>; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1550 clock-names = "se"; 1551 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1552 power-domains = <&rpmhpd SC8280XP_CX>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1556 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1557 status = "disabled"; 1558 }; 1559 1560 spi11: spi@a8c000 { 1561 compatible = "qcom,geni-spi"; 1562 reg = <0 0x00a8c000 0 0x4000>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1566 clock-names = "se"; 1567 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1568 power-domains = <&rpmhpd SC8280XP_CX>; 1569 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1570 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1571 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1572 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1573 status = "disabled"; 1574 }; 1575 1576 i2c12: i2c@a90000 { 1577 compatible = "qcom,geni-i2c"; 1578 reg = <0 0x00a90000 0 0x4000>; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1582 clock-names = "se"; 1583 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1584 power-domains = <&rpmhpd SC8280XP_CX>; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1587 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1588 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1589 status = "disabled"; 1590 }; 1591 1592 spi12: spi@a90000 { 1593 compatible = "qcom,geni-spi"; 1594 reg = <0 0x00a90000 0 0x4000>; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1598 clock-names = "se"; 1599 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1600 power-domains = <&rpmhpd SC8280XP_CX>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1603 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1604 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1605 status = "disabled"; 1606 }; 1607 1608 i2c13: i2c@a94000 { 1609 compatible = "qcom,geni-i2c"; 1610 reg = <0 0x00a94000 0 0x4000>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1614 clock-names = "se"; 1615 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1616 power-domains = <&rpmhpd SC8280XP_CX>; 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1618 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1619 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1620 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1621 status = "disabled"; 1622 }; 1623 1624 spi13: spi@a94000 { 1625 compatible = "qcom,geni-spi"; 1626 reg = <0 0x00a94000 0 0x4000>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1630 clock-names = "se"; 1631 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1632 power-domains = <&rpmhpd SC8280XP_CX>; 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1634 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1635 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1636 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1637 status = "disabled"; 1638 }; 1639 1640 i2c14: i2c@a98000 { 1641 compatible = "qcom,geni-i2c"; 1642 reg = <0 0x00a98000 0 0x4000>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1646 clock-names = "se"; 1647 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1648 power-domains = <&rpmhpd SC8280XP_CX>; 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1650 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1651 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1652 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1653 status = "disabled"; 1654 }; 1655 1656 spi14: spi@a98000 { 1657 compatible = "qcom,geni-spi"; 1658 reg = <0 0x00a98000 0 0x4000>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1662 clock-names = "se"; 1663 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1664 power-domains = <&rpmhpd SC8280XP_CX>; 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1667 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1668 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1669 status = "disabled"; 1670 }; 1671 1672 i2c15: i2c@a9c000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a9c000 0 0x4000>; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1678 clock-names = "se"; 1679 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1680 power-domains = <&rpmhpd SC8280XP_CX>; 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1682 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1683 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1684 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1685 status = "disabled"; 1686 }; 1687 1688 spi15: spi@a9c000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0 0x00a9c000 0 0x4000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1694 clock-names = "se"; 1695 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1696 power-domains = <&rpmhpd SC8280XP_CX>; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1698 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1699 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1700 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1701 status = "disabled"; 1702 }; 1703 }; 1704 1705 rng: rng@10d3000 { 1706 compatible = "qcom,prng-ee"; 1707 reg = <0 0x010d3000 0 0x1000>; 1708 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1709 clock-names = "core"; 1710 }; 1711 1712 pcie4: pcie@1c00000 { 1713 device_type = "pci"; 1714 compatible = "qcom,pcie-sc8280xp"; 1715 reg = <0x0 0x01c00000 0x0 0x3000>, 1716 <0x0 0x30000000 0x0 0xf1d>, 1717 <0x0 0x30000f20 0x0 0xa8>, 1718 <0x0 0x30001000 0x0 0x1000>, 1719 <0x0 0x30100000 0x0 0x100000>, 1720 <0x0 0x01c03000 0x0 0x1000>; 1721 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1722 #address-cells = <3>; 1723 #size-cells = <2>; 1724 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1725 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1726 bus-range = <0x00 0xff>; 1727 1728 dma-coherent; 1729 1730 linux,pci-domain = <6>; 1731 num-lanes = <1>; 1732 1733 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1737 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1738 1739 #interrupt-cells = <1>; 1740 interrupt-map-mask = <0 0 0 0x7>; 1741 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1742 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1743 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1744 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1745 1746 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1747 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1748 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1749 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1750 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1751 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1752 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1753 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1754 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1755 clock-names = "aux", 1756 "cfg", 1757 "bus_master", 1758 "bus_slave", 1759 "slave_q2a", 1760 "ddrss_sf_tbu", 1761 "noc_aggr_4", 1762 "noc_aggr_south_sf", 1763 "cnoc_qx"; 1764 1765 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1766 assigned-clock-rates = <19200000>; 1767 1768 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1769 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1770 interconnect-names = "pcie-mem", "cpu-pcie"; 1771 1772 resets = <&gcc GCC_PCIE_4_BCR>; 1773 reset-names = "pci"; 1774 1775 power-domains = <&gcc PCIE_4_GDSC>; 1776 1777 phys = <&pcie4_phy>; 1778 phy-names = "pciephy"; 1779 1780 status = "disabled"; 1781 }; 1782 1783 pcie4_phy: phy@1c06000 { 1784 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1785 reg = <0x0 0x01c06000 0x0 0x2000>; 1786 1787 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1788 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1789 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1790 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1791 <&gcc GCC_PCIE_4_PIPE_CLK>, 1792 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1793 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1794 "pipe", "pipediv2"; 1795 1796 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1797 assigned-clock-rates = <100000000>; 1798 1799 power-domains = <&gcc PCIE_4_GDSC>; 1800 1801 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1802 reset-names = "phy"; 1803 1804 #clock-cells = <0>; 1805 clock-output-names = "pcie_4_pipe_clk"; 1806 1807 #phy-cells = <0>; 1808 1809 status = "disabled"; 1810 }; 1811 1812 pcie3b: pcie@1c08000 { 1813 device_type = "pci"; 1814 compatible = "qcom,pcie-sc8280xp"; 1815 reg = <0x0 0x01c08000 0x0 0x3000>, 1816 <0x0 0x32000000 0x0 0xf1d>, 1817 <0x0 0x32000f20 0x0 0xa8>, 1818 <0x0 0x32001000 0x0 0x1000>, 1819 <0x0 0x32100000 0x0 0x100000>, 1820 <0x0 0x01c0b000 0x0 0x1000>; 1821 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1822 #address-cells = <3>; 1823 #size-cells = <2>; 1824 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1825 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1826 bus-range = <0x00 0xff>; 1827 1828 dma-coherent; 1829 1830 linux,pci-domain = <5>; 1831 num-lanes = <2>; 1832 1833 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1837 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1838 1839 #interrupt-cells = <1>; 1840 interrupt-map-mask = <0 0 0 0x7>; 1841 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1842 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1843 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1844 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1845 1846 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1847 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1848 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1849 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1850 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1851 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1852 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1853 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1854 clock-names = "aux", 1855 "cfg", 1856 "bus_master", 1857 "bus_slave", 1858 "slave_q2a", 1859 "ddrss_sf_tbu", 1860 "noc_aggr_4", 1861 "noc_aggr_south_sf"; 1862 1863 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1864 assigned-clock-rates = <19200000>; 1865 1866 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1867 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1868 interconnect-names = "pcie-mem", "cpu-pcie"; 1869 1870 resets = <&gcc GCC_PCIE_3B_BCR>; 1871 reset-names = "pci"; 1872 1873 power-domains = <&gcc PCIE_3B_GDSC>; 1874 1875 phys = <&pcie3b_phy>; 1876 phy-names = "pciephy"; 1877 1878 status = "disabled"; 1879 }; 1880 1881 pcie3b_phy: phy@1c0e000 { 1882 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1883 reg = <0x0 0x01c0e000 0x0 0x2000>; 1884 1885 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1886 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1887 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1888 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1889 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1890 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1891 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1892 "pipe", "pipediv2"; 1893 1894 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1895 assigned-clock-rates = <100000000>; 1896 1897 power-domains = <&gcc PCIE_3B_GDSC>; 1898 1899 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1900 reset-names = "phy"; 1901 1902 #clock-cells = <0>; 1903 clock-output-names = "pcie_3b_pipe_clk"; 1904 1905 #phy-cells = <0>; 1906 1907 status = "disabled"; 1908 }; 1909 1910 pcie3a: pcie@1c10000 { 1911 device_type = "pci"; 1912 compatible = "qcom,pcie-sc8280xp"; 1913 reg = <0x0 0x01c10000 0x0 0x3000>, 1914 <0x0 0x34000000 0x0 0xf1d>, 1915 <0x0 0x34000f20 0x0 0xa8>, 1916 <0x0 0x34001000 0x0 0x1000>, 1917 <0x0 0x34100000 0x0 0x100000>, 1918 <0x0 0x01c13000 0x0 0x1000>; 1919 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1920 #address-cells = <3>; 1921 #size-cells = <2>; 1922 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1923 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1924 bus-range = <0x00 0xff>; 1925 1926 dma-coherent; 1927 1928 linux,pci-domain = <4>; 1929 num-lanes = <4>; 1930 1931 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1935 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1936 1937 #interrupt-cells = <1>; 1938 interrupt-map-mask = <0 0 0 0x7>; 1939 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1940 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1941 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1942 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1943 1944 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1945 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1946 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1947 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1948 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1949 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1950 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1951 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1952 clock-names = "aux", 1953 "cfg", 1954 "bus_master", 1955 "bus_slave", 1956 "slave_q2a", 1957 "ddrss_sf_tbu", 1958 "noc_aggr_4", 1959 "noc_aggr_south_sf"; 1960 1961 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1962 assigned-clock-rates = <19200000>; 1963 1964 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1965 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1966 interconnect-names = "pcie-mem", "cpu-pcie"; 1967 1968 resets = <&gcc GCC_PCIE_3A_BCR>; 1969 reset-names = "pci"; 1970 1971 power-domains = <&gcc PCIE_3A_GDSC>; 1972 1973 phys = <&pcie3a_phy>; 1974 phy-names = "pciephy"; 1975 1976 status = "disabled"; 1977 }; 1978 1979 pcie3a_phy: phy@1c14000 { 1980 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1981 reg = <0x0 0x01c14000 0x0 0x2000>, 1982 <0x0 0x01c16000 0x0 0x2000>; 1983 1984 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1985 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1986 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1987 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1988 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1989 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1990 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1991 "pipe", "pipediv2"; 1992 1993 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1994 assigned-clock-rates = <100000000>; 1995 1996 power-domains = <&gcc PCIE_3A_GDSC>; 1997 1998 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 1999 reset-names = "phy"; 2000 2001 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2002 2003 #clock-cells = <0>; 2004 clock-output-names = "pcie_3a_pipe_clk"; 2005 2006 #phy-cells = <0>; 2007 2008 status = "disabled"; 2009 }; 2010 2011 pcie2b: pcie@1c18000 { 2012 device_type = "pci"; 2013 compatible = "qcom,pcie-sc8280xp"; 2014 reg = <0x0 0x01c18000 0x0 0x3000>, 2015 <0x0 0x38000000 0x0 0xf1d>, 2016 <0x0 0x38000f20 0x0 0xa8>, 2017 <0x0 0x38001000 0x0 0x1000>, 2018 <0x0 0x38100000 0x0 0x100000>, 2019 <0x0 0x01c1b000 0x0 0x1000>; 2020 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2021 #address-cells = <3>; 2022 #size-cells = <2>; 2023 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2024 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2025 bus-range = <0x00 0xff>; 2026 2027 dma-coherent; 2028 2029 linux,pci-domain = <3>; 2030 num-lanes = <2>; 2031 2032 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2036 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2037 2038 #interrupt-cells = <1>; 2039 interrupt-map-mask = <0 0 0 0x7>; 2040 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2041 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2042 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2043 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2044 2045 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2046 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2047 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2048 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2049 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2050 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2051 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2052 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2053 clock-names = "aux", 2054 "cfg", 2055 "bus_master", 2056 "bus_slave", 2057 "slave_q2a", 2058 "ddrss_sf_tbu", 2059 "noc_aggr_4", 2060 "noc_aggr_south_sf"; 2061 2062 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2063 assigned-clock-rates = <19200000>; 2064 2065 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2066 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2067 interconnect-names = "pcie-mem", "cpu-pcie"; 2068 2069 resets = <&gcc GCC_PCIE_2B_BCR>; 2070 reset-names = "pci"; 2071 2072 power-domains = <&gcc PCIE_2B_GDSC>; 2073 2074 phys = <&pcie2b_phy>; 2075 phy-names = "pciephy"; 2076 2077 status = "disabled"; 2078 }; 2079 2080 pcie2b_phy: phy@1c1e000 { 2081 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2082 reg = <0x0 0x01c1e000 0x0 0x2000>; 2083 2084 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2085 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2086 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2087 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2088 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2089 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2090 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2091 "pipe", "pipediv2"; 2092 2093 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2094 assigned-clock-rates = <100000000>; 2095 2096 power-domains = <&gcc PCIE_2B_GDSC>; 2097 2098 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2099 reset-names = "phy"; 2100 2101 #clock-cells = <0>; 2102 clock-output-names = "pcie_2b_pipe_clk"; 2103 2104 #phy-cells = <0>; 2105 2106 status = "disabled"; 2107 }; 2108 2109 pcie2a: pcie@1c20000 { 2110 device_type = "pci"; 2111 compatible = "qcom,pcie-sc8280xp"; 2112 reg = <0x0 0x01c20000 0x0 0x3000>, 2113 <0x0 0x3c000000 0x0 0xf1d>, 2114 <0x0 0x3c000f20 0x0 0xa8>, 2115 <0x0 0x3c001000 0x0 0x1000>, 2116 <0x0 0x3c100000 0x0 0x100000>, 2117 <0x0 0x01c23000 0x0 0x1000>; 2118 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2119 #address-cells = <3>; 2120 #size-cells = <2>; 2121 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2122 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2123 bus-range = <0x00 0xff>; 2124 2125 dma-coherent; 2126 2127 linux,pci-domain = <2>; 2128 num-lanes = <4>; 2129 2130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2134 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2135 2136 #interrupt-cells = <1>; 2137 interrupt-map-mask = <0 0 0 0x7>; 2138 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2139 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2140 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2141 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2142 2143 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2144 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2145 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2146 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2147 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2148 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2149 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2150 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2151 clock-names = "aux", 2152 "cfg", 2153 "bus_master", 2154 "bus_slave", 2155 "slave_q2a", 2156 "ddrss_sf_tbu", 2157 "noc_aggr_4", 2158 "noc_aggr_south_sf"; 2159 2160 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2161 assigned-clock-rates = <19200000>; 2162 2163 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2165 interconnect-names = "pcie-mem", "cpu-pcie"; 2166 2167 resets = <&gcc GCC_PCIE_2A_BCR>; 2168 reset-names = "pci"; 2169 2170 power-domains = <&gcc PCIE_2A_GDSC>; 2171 2172 phys = <&pcie2a_phy>; 2173 phy-names = "pciephy"; 2174 2175 status = "disabled"; 2176 }; 2177 2178 pcie2a_phy: phy@1c24000 { 2179 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2180 reg = <0x0 0x01c24000 0x0 0x2000>, 2181 <0x0 0x01c26000 0x0 0x2000>; 2182 2183 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2184 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2185 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2186 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2187 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2188 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2189 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2190 "pipe", "pipediv2"; 2191 2192 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2193 assigned-clock-rates = <100000000>; 2194 2195 power-domains = <&gcc PCIE_2A_GDSC>; 2196 2197 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2198 reset-names = "phy"; 2199 2200 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2201 2202 #clock-cells = <0>; 2203 clock-output-names = "pcie_2a_pipe_clk"; 2204 2205 #phy-cells = <0>; 2206 2207 status = "disabled"; 2208 }; 2209 2210 ufs_mem_hc: ufs@1d84000 { 2211 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2212 "jedec,ufs-2.0"; 2213 reg = <0 0x01d84000 0 0x3000>; 2214 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2215 phys = <&ufs_mem_phy>; 2216 phy-names = "ufsphy"; 2217 lanes-per-direction = <2>; 2218 #reset-cells = <1>; 2219 resets = <&gcc GCC_UFS_PHY_BCR>; 2220 reset-names = "rst"; 2221 2222 power-domains = <&gcc UFS_PHY_GDSC>; 2223 required-opps = <&rpmhpd_opp_nom>; 2224 2225 iommus = <&apps_smmu 0xe0 0x0>; 2226 dma-coherent; 2227 2228 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2229 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2230 <&gcc GCC_UFS_PHY_AHB_CLK>, 2231 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2232 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2233 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2234 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2235 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2236 clock-names = "core_clk", 2237 "bus_aggr_clk", 2238 "iface_clk", 2239 "core_clk_unipro", 2240 "ref_clk", 2241 "tx_lane0_sync_clk", 2242 "rx_lane0_sync_clk", 2243 "rx_lane1_sync_clk"; 2244 freq-table-hz = <75000000 300000000>, 2245 <0 0>, 2246 <0 0>, 2247 <75000000 300000000>, 2248 <0 0>, 2249 <0 0>, 2250 <0 0>, 2251 <0 0>; 2252 status = "disabled"; 2253 }; 2254 2255 ufs_mem_phy: phy@1d87000 { 2256 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2257 reg = <0 0x01d87000 0 0x1000>; 2258 2259 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2260 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2261 clock-names = "ref", "ref_aux"; 2262 2263 power-domains = <&gcc UFS_PHY_GDSC>; 2264 2265 resets = <&ufs_mem_hc 0>; 2266 reset-names = "ufsphy"; 2267 2268 #phy-cells = <0>; 2269 2270 status = "disabled"; 2271 }; 2272 2273 ufs_card_hc: ufs@1da4000 { 2274 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2275 "jedec,ufs-2.0"; 2276 reg = <0 0x01da4000 0 0x3000>; 2277 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2278 phys = <&ufs_card_phy>; 2279 phy-names = "ufsphy"; 2280 lanes-per-direction = <2>; 2281 #reset-cells = <1>; 2282 resets = <&gcc GCC_UFS_CARD_BCR>; 2283 reset-names = "rst"; 2284 2285 power-domains = <&gcc UFS_CARD_GDSC>; 2286 2287 iommus = <&apps_smmu 0x4a0 0x0>; 2288 dma-coherent; 2289 2290 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2291 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2292 <&gcc GCC_UFS_CARD_AHB_CLK>, 2293 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2294 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2295 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2296 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2297 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2298 clock-names = "core_clk", 2299 "bus_aggr_clk", 2300 "iface_clk", 2301 "core_clk_unipro", 2302 "ref_clk", 2303 "tx_lane0_sync_clk", 2304 "rx_lane0_sync_clk", 2305 "rx_lane1_sync_clk"; 2306 freq-table-hz = <75000000 300000000>, 2307 <0 0>, 2308 <0 0>, 2309 <75000000 300000000>, 2310 <0 0>, 2311 <0 0>, 2312 <0 0>, 2313 <0 0>; 2314 status = "disabled"; 2315 }; 2316 2317 ufs_card_phy: phy@1da7000 { 2318 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2319 reg = <0 0x01da7000 0 0x1000>; 2320 2321 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2322 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2323 clock-names = "ref", "ref_aux"; 2324 2325 power-domains = <&gcc UFS_CARD_GDSC>; 2326 2327 resets = <&ufs_card_hc 0>; 2328 reset-names = "ufsphy"; 2329 2330 #phy-cells = <0>; 2331 2332 status = "disabled"; 2333 }; 2334 2335 tcsr_mutex: hwlock@1f40000 { 2336 compatible = "qcom,tcsr-mutex"; 2337 reg = <0x0 0x01f40000 0x0 0x20000>; 2338 #hwlock-cells = <1>; 2339 }; 2340 2341 tcsr: syscon@1fc0000 { 2342 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2343 reg = <0x0 0x01fc0000 0x0 0x30000>; 2344 }; 2345 2346 gpu: gpu@3d00000 { 2347 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2348 2349 reg = <0 0x03d00000 0 0x40000>, 2350 <0 0x03d9e000 0 0x1000>, 2351 <0 0x03d61000 0 0x800>; 2352 reg-names = "kgsl_3d0_reg_memory", 2353 "cx_mem", 2354 "cx_dbgc"; 2355 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2356 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2357 operating-points-v2 = <&gpu_opp_table>; 2358 2359 qcom,gmu = <&gmu>; 2360 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2361 interconnect-names = "gfx-mem"; 2362 #cooling-cells = <2>; 2363 2364 status = "disabled"; 2365 2366 gpu_opp_table: opp-table { 2367 compatible = "operating-points-v2"; 2368 2369 opp-270000000 { 2370 opp-hz = /bits/ 64 <270000000>; 2371 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2372 opp-peak-kBps = <451000>; 2373 }; 2374 2375 opp-410000000 { 2376 opp-hz = /bits/ 64 <410000000>; 2377 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2378 opp-peak-kBps = <1555000>; 2379 }; 2380 2381 opp-500000000 { 2382 opp-hz = /bits/ 64 <500000000>; 2383 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2384 opp-peak-kBps = <1555000>; 2385 }; 2386 2387 opp-547000000 { 2388 opp-hz = /bits/ 64 <547000000>; 2389 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2390 opp-peak-kBps = <1555000>; 2391 }; 2392 2393 opp-606000000 { 2394 opp-hz = /bits/ 64 <606000000>; 2395 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2396 opp-peak-kBps = <2736000>; 2397 }; 2398 2399 opp-640000000 { 2400 opp-hz = /bits/ 64 <640000000>; 2401 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2402 opp-peak-kBps = <2736000>; 2403 }; 2404 2405 opp-655000000 { 2406 opp-hz = /bits/ 64 <655000000>; 2407 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2408 opp-peak-kBps = <2736000>; 2409 }; 2410 2411 opp-690000000 { 2412 opp-hz = /bits/ 64 <690000000>; 2413 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2414 opp-peak-kBps = <2736000>; 2415 }; 2416 }; 2417 }; 2418 2419 gmu: gmu@3d6a000 { 2420 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 2421 reg = <0 0x03d6a000 0 0x34000>, 2422 <0 0x03de0000 0 0x10000>, 2423 <0 0x0b290000 0 0x10000>; 2424 reg-names = "gmu", "rscc", "gmu_pdc"; 2425 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2427 interrupt-names = "hfi", "gmu"; 2428 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2429 <&gpucc GPU_CC_CXO_CLK>, 2430 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2431 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2432 <&gpucc GPU_CC_AHB_CLK>, 2433 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2434 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2435 clock-names = "gmu", 2436 "cxo", 2437 "axi", 2438 "memnoc", 2439 "ahb", 2440 "hub", 2441 "smmu_vote"; 2442 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2443 <&gpucc GPU_CC_GX_GDSC>; 2444 power-domain-names = "cx", 2445 "gx"; 2446 iommus = <&gpu_smmu 5 0xc00>; 2447 operating-points-v2 = <&gmu_opp_table>; 2448 2449 gmu_opp_table: opp-table { 2450 compatible = "operating-points-v2"; 2451 2452 opp-200000000 { 2453 opp-hz = /bits/ 64 <200000000>; 2454 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2455 }; 2456 2457 opp-500000000 { 2458 opp-hz = /bits/ 64 <500000000>; 2459 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2460 }; 2461 }; 2462 }; 2463 2464 gpucc: clock-controller@3d90000 { 2465 compatible = "qcom,sc8280xp-gpucc"; 2466 reg = <0 0x03d90000 0 0x9000>; 2467 clocks = <&rpmhcc RPMH_CXO_CLK>, 2468 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2469 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2470 clock-names = "bi_tcxo", 2471 "gcc_gpu_gpll0_clk_src", 2472 "gcc_gpu_gpll0_div_clk_src"; 2473 2474 power-domains = <&rpmhpd SC8280XP_GFX>; 2475 #clock-cells = <1>; 2476 #reset-cells = <1>; 2477 #power-domain-cells = <1>; 2478 }; 2479 2480 gpu_smmu: iommu@3da0000 { 2481 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 2482 "qcom,smmu-500", "arm,mmu-500"; 2483 reg = <0 0x03da0000 0 0x20000>; 2484 #iommu-cells = <2>; 2485 #global-interrupts = <2>; 2486 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 2500 2501 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2502 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2503 <&gpucc GPU_CC_AHB_CLK>, 2504 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2505 <&gpucc GPU_CC_CX_GMU_CLK>, 2506 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2507 <&gpucc GPU_CC_HUB_AON_CLK>; 2508 clock-names = "gcc_gpu_memnoc_gfx_clk", 2509 "gcc_gpu_snoc_dvm_gfx_clk", 2510 "gpu_cc_ahb_clk", 2511 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2512 "gpu_cc_cx_gmu_clk", 2513 "gpu_cc_hub_cx_int_clk", 2514 "gpu_cc_hub_aon_clk"; 2515 2516 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2517 dma-coherent; 2518 }; 2519 2520 usb_0_hsphy: phy@88e5000 { 2521 compatible = "qcom,sc8280xp-usb-hs-phy", 2522 "qcom,usb-snps-hs-5nm-phy"; 2523 reg = <0 0x088e5000 0 0x400>; 2524 clocks = <&rpmhcc RPMH_CXO_CLK>; 2525 clock-names = "ref"; 2526 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2527 2528 #phy-cells = <0>; 2529 2530 status = "disabled"; 2531 }; 2532 2533 usb_2_hsphy0: phy@88e7000 { 2534 compatible = "qcom,sc8280xp-usb-hs-phy", 2535 "qcom,usb-snps-hs-5nm-phy"; 2536 reg = <0 0x088e7000 0 0x400>; 2537 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2538 clock-names = "ref"; 2539 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2540 2541 #phy-cells = <0>; 2542 2543 status = "disabled"; 2544 }; 2545 2546 usb_2_hsphy1: phy@88e8000 { 2547 compatible = "qcom,sc8280xp-usb-hs-phy", 2548 "qcom,usb-snps-hs-5nm-phy"; 2549 reg = <0 0x088e8000 0 0x400>; 2550 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2551 clock-names = "ref"; 2552 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2553 2554 #phy-cells = <0>; 2555 2556 status = "disabled"; 2557 }; 2558 2559 usb_2_hsphy2: phy@88e9000 { 2560 compatible = "qcom,sc8280xp-usb-hs-phy", 2561 "qcom,usb-snps-hs-5nm-phy"; 2562 reg = <0 0x088e9000 0 0x400>; 2563 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2564 clock-names = "ref"; 2565 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2566 2567 #phy-cells = <0>; 2568 2569 status = "disabled"; 2570 }; 2571 2572 usb_2_hsphy3: phy@88ea000 { 2573 compatible = "qcom,sc8280xp-usb-hs-phy", 2574 "qcom,usb-snps-hs-5nm-phy"; 2575 reg = <0 0x088ea000 0 0x400>; 2576 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2577 clock-names = "ref"; 2578 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2579 2580 #phy-cells = <0>; 2581 2582 status = "disabled"; 2583 }; 2584 2585 usb_2_qmpphy0: phy@88ef000 { 2586 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2587 reg = <0 0x088ef000 0 0x2000>; 2588 2589 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2590 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2591 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2592 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2593 clock-names = "aux", "ref", "com_aux", "pipe"; 2594 2595 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2596 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2597 reset-names = "phy", "phy_phy"; 2598 2599 power-domains = <&gcc USB30_MP_GDSC>; 2600 2601 #clock-cells = <0>; 2602 clock-output-names = "usb2_phy0_pipe_clk"; 2603 2604 #phy-cells = <0>; 2605 2606 status = "disabled"; 2607 }; 2608 2609 usb_2_qmpphy1: phy@88f1000 { 2610 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2611 reg = <0 0x088f1000 0 0x2000>; 2612 2613 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2614 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2615 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2616 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2617 clock-names = "aux", "ref", "com_aux", "pipe"; 2618 2619 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2620 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2621 reset-names = "phy", "phy_phy"; 2622 2623 power-domains = <&gcc USB30_MP_GDSC>; 2624 2625 #clock-cells = <0>; 2626 clock-output-names = "usb2_phy1_pipe_clk"; 2627 2628 #phy-cells = <0>; 2629 2630 status = "disabled"; 2631 }; 2632 2633 remoteproc_adsp: remoteproc@3000000 { 2634 compatible = "qcom,sc8280xp-adsp-pas"; 2635 reg = <0 0x03000000 0 0x100>; 2636 2637 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2638 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2639 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2640 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2641 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2642 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2643 interrupt-names = "wdog", "fatal", "ready", 2644 "handover", "stop-ack", "shutdown-ack"; 2645 2646 clocks = <&rpmhcc RPMH_CXO_CLK>; 2647 clock-names = "xo"; 2648 2649 power-domains = <&rpmhpd SC8280XP_LCX>, 2650 <&rpmhpd SC8280XP_LMX>; 2651 power-domain-names = "lcx", "lmx"; 2652 2653 memory-region = <&pil_adsp_mem>; 2654 2655 qcom,qmp = <&aoss_qmp>; 2656 2657 qcom,smem-states = <&smp2p_adsp_out 0>; 2658 qcom,smem-state-names = "stop"; 2659 2660 status = "disabled"; 2661 2662 remoteproc_adsp_glink: glink-edge { 2663 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2664 IPCC_MPROC_SIGNAL_GLINK_QMP 2665 IRQ_TYPE_EDGE_RISING>; 2666 mboxes = <&ipcc IPCC_CLIENT_LPASS 2667 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2668 2669 label = "lpass"; 2670 qcom,remote-pid = <2>; 2671 2672 gpr { 2673 compatible = "qcom,gpr"; 2674 qcom,glink-channels = "adsp_apps"; 2675 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2676 qcom,intents = <512 20>; 2677 #address-cells = <1>; 2678 #size-cells = <0>; 2679 2680 q6apm: service@1 { 2681 compatible = "qcom,q6apm"; 2682 reg = <GPR_APM_MODULE_IID>; 2683 #sound-dai-cells = <0>; 2684 qcom,protection-domain = "avs/audio", 2685 "msm/adsp/audio_pd"; 2686 q6apmdai: dais { 2687 compatible = "qcom,q6apm-dais"; 2688 iommus = <&apps_smmu 0x0c01 0x0>; 2689 }; 2690 2691 q6apmbedai: bedais { 2692 compatible = "qcom,q6apm-lpass-dais"; 2693 #sound-dai-cells = <1>; 2694 }; 2695 }; 2696 2697 q6prm: service@2 { 2698 compatible = "qcom,q6prm"; 2699 reg = <GPR_PRM_MODULE_IID>; 2700 qcom,protection-domain = "avs/audio", 2701 "msm/adsp/audio_pd"; 2702 q6prmcc: clock-controller { 2703 compatible = "qcom,q6prm-lpass-clocks"; 2704 #clock-cells = <2>; 2705 }; 2706 }; 2707 }; 2708 }; 2709 }; 2710 2711 rxmacro: rxmacro@3200000 { 2712 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2713 reg = <0 0x03200000 0 0x1000>; 2714 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2715 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2716 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2717 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2718 <&vamacro>; 2719 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2720 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2721 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2722 assigned-clock-rates = <19200000>, <19200000>; 2723 2724 clock-output-names = "mclk"; 2725 #clock-cells = <0>; 2726 #sound-dai-cells = <1>; 2727 2728 pinctrl-names = "default"; 2729 pinctrl-0 = <&rx_swr_default>; 2730 2731 status = "disabled"; 2732 }; 2733 2734 swr1: soundwire-controller@3210000 { 2735 compatible = "qcom,soundwire-v1.6.0"; 2736 reg = <0 0x03210000 0 0x2000>; 2737 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2738 clocks = <&rxmacro>; 2739 clock-names = "iface"; 2740 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2741 reset-names = "swr_audio_cgcr"; 2742 label = "RX"; 2743 2744 qcom,din-ports = <0>; 2745 qcom,dout-ports = <5>; 2746 2747 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2748 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2749 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2750 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2751 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2752 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2753 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2754 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2755 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2756 2757 #sound-dai-cells = <1>; 2758 #address-cells = <2>; 2759 #size-cells = <0>; 2760 2761 status = "disabled"; 2762 }; 2763 2764 txmacro: txmacro@3220000 { 2765 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2766 reg = <0 0x03220000 0 0x1000>; 2767 pinctrl-names = "default"; 2768 pinctrl-0 = <&tx_swr_default>; 2769 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2770 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2771 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2772 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2773 <&vamacro>; 2774 2775 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2776 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2777 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2778 assigned-clock-rates = <19200000>, <19200000>; 2779 clock-output-names = "mclk"; 2780 2781 #clock-cells = <0>; 2782 #sound-dai-cells = <1>; 2783 2784 status = "disabled"; 2785 }; 2786 2787 wsamacro: codec@3240000 { 2788 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2789 reg = <0 0x03240000 0 0x1000>; 2790 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2791 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2792 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2793 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2794 <&vamacro>; 2795 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2796 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2797 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2798 assigned-clock-rates = <19200000>, <19200000>; 2799 2800 #clock-cells = <0>; 2801 clock-output-names = "mclk"; 2802 #sound-dai-cells = <1>; 2803 2804 pinctrl-names = "default"; 2805 pinctrl-0 = <&wsa_swr_default>; 2806 2807 status = "disabled"; 2808 }; 2809 2810 swr0: soundwire-controller@3250000 { 2811 reg = <0 0x03250000 0 0x2000>; 2812 compatible = "qcom,soundwire-v1.6.0"; 2813 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2814 clocks = <&wsamacro>; 2815 clock-names = "iface"; 2816 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2817 reset-names = "swr_audio_cgcr"; 2818 label = "WSA"; 2819 2820 qcom,din-ports = <2>; 2821 qcom,dout-ports = <6>; 2822 2823 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2824 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2825 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2826 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2827 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2828 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2829 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2830 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2831 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2832 2833 #sound-dai-cells = <1>; 2834 #address-cells = <2>; 2835 #size-cells = <0>; 2836 2837 status = "disabled"; 2838 }; 2839 2840 lpass_audiocc: clock-controller@32a9000 { 2841 compatible = "qcom,sc8280xp-lpassaudiocc"; 2842 reg = <0 0x032a9000 0 0x1000>; 2843 #clock-cells = <1>; 2844 #reset-cells = <1>; 2845 }; 2846 2847 swr2: soundwire-controller@3330000 { 2848 compatible = "qcom,soundwire-v1.6.0"; 2849 reg = <0 0x03330000 0 0x2000>; 2850 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2852 interrupt-names = "core", "wakeup"; 2853 2854 clocks = <&txmacro>; 2855 clock-names = "iface"; 2856 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2857 reset-names = "swr_audio_cgcr"; 2858 label = "TX"; 2859 #sound-dai-cells = <1>; 2860 #address-cells = <2>; 2861 #size-cells = <0>; 2862 2863 qcom,din-ports = <4>; 2864 qcom,dout-ports = <0>; 2865 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2866 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2867 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2868 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2869 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2870 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2871 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2872 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2873 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2874 2875 status = "disabled"; 2876 }; 2877 2878 vamacro: codec@3370000 { 2879 compatible = "qcom,sc8280xp-lpass-va-macro"; 2880 reg = <0 0x03370000 0 0x1000>; 2881 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2882 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2883 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2884 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2885 clock-names = "mclk", "macro", "dcodec", "npl"; 2886 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2887 assigned-clock-rates = <19200000>; 2888 2889 #clock-cells = <0>; 2890 clock-output-names = "fsgen"; 2891 #sound-dai-cells = <1>; 2892 2893 status = "disabled"; 2894 }; 2895 2896 lpass_tlmm: pinctrl@33c0000 { 2897 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2898 reg = <0 0x33c0000 0x0 0x20000>, 2899 <0 0x3550000 0x0 0x10000>; 2900 gpio-controller; 2901 #gpio-cells = <2>; 2902 gpio-ranges = <&lpass_tlmm 0 0 19>; 2903 2904 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2905 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2906 clock-names = "core", "audio"; 2907 2908 status = "disabled"; 2909 2910 tx_swr_default: tx-swr-default-state { 2911 clk-pins { 2912 pins = "gpio0"; 2913 function = "swr_tx_clk"; 2914 drive-strength = <2>; 2915 slew-rate = <1>; 2916 bias-disable; 2917 }; 2918 2919 data-pins { 2920 pins = "gpio1", "gpio2"; 2921 function = "swr_tx_data"; 2922 drive-strength = <2>; 2923 slew-rate = <1>; 2924 bias-bus-hold; 2925 }; 2926 }; 2927 2928 rx_swr_default: rx-swr-default-state { 2929 clk-pins { 2930 pins = "gpio3"; 2931 function = "swr_rx_clk"; 2932 drive-strength = <2>; 2933 slew-rate = <1>; 2934 bias-disable; 2935 }; 2936 2937 data-pins { 2938 pins = "gpio4", "gpio5"; 2939 function = "swr_rx_data"; 2940 drive-strength = <2>; 2941 slew-rate = <1>; 2942 bias-bus-hold; 2943 }; 2944 }; 2945 2946 dmic01_default: dmic01-default-state { 2947 clk-pins { 2948 pins = "gpio6"; 2949 function = "dmic1_clk"; 2950 drive-strength = <8>; 2951 output-high; 2952 }; 2953 2954 data-pins { 2955 pins = "gpio7"; 2956 function = "dmic1_data"; 2957 drive-strength = <8>; 2958 input-enable; 2959 }; 2960 }; 2961 2962 dmic01_sleep: dmic01-sleep-state { 2963 clk-pins { 2964 pins = "gpio6"; 2965 function = "dmic1_clk"; 2966 drive-strength = <2>; 2967 bias-disable; 2968 output-low; 2969 }; 2970 2971 data-pins { 2972 pins = "gpio7"; 2973 function = "dmic1_data"; 2974 drive-strength = <2>; 2975 bias-pull-down; 2976 input-enable; 2977 }; 2978 }; 2979 2980 dmic02_default: dmic02-default-state { 2981 clk-pins { 2982 pins = "gpio8"; 2983 function = "dmic2_clk"; 2984 drive-strength = <8>; 2985 output-high; 2986 }; 2987 2988 data-pins { 2989 pins = "gpio9"; 2990 function = "dmic2_data"; 2991 drive-strength = <8>; 2992 input-enable; 2993 }; 2994 }; 2995 2996 dmic02_sleep: dmic02-sleep-state { 2997 clk-pins { 2998 pins = "gpio8"; 2999 function = "dmic2_clk"; 3000 drive-strength = <2>; 3001 bias-disable; 3002 output-low; 3003 }; 3004 3005 data-pins { 3006 pins = "gpio9"; 3007 function = "dmic2_data"; 3008 drive-strength = <2>; 3009 bias-pull-down; 3010 input-enable; 3011 }; 3012 }; 3013 3014 wsa_swr_default: wsa-swr-default-state { 3015 clk-pins { 3016 pins = "gpio10"; 3017 function = "wsa_swr_clk"; 3018 drive-strength = <2>; 3019 slew-rate = <1>; 3020 bias-disable; 3021 }; 3022 3023 data-pins { 3024 pins = "gpio11"; 3025 function = "wsa_swr_data"; 3026 drive-strength = <2>; 3027 slew-rate = <1>; 3028 bias-bus-hold; 3029 }; 3030 }; 3031 3032 wsa2_swr_default: wsa2-swr-default-state { 3033 clk-pins { 3034 pins = "gpio15"; 3035 function = "wsa2_swr_clk"; 3036 drive-strength = <2>; 3037 slew-rate = <1>; 3038 bias-disable; 3039 }; 3040 3041 data-pins { 3042 pins = "gpio16"; 3043 function = "wsa2_swr_data"; 3044 drive-strength = <2>; 3045 slew-rate = <1>; 3046 bias-bus-hold; 3047 }; 3048 }; 3049 }; 3050 3051 lpasscc: clock-controller@33e0000 { 3052 compatible = "qcom,sc8280xp-lpasscc"; 3053 reg = <0 0x033e0000 0 0x12000>; 3054 #clock-cells = <1>; 3055 #reset-cells = <1>; 3056 }; 3057 3058 sdc2: mmc@8804000 { 3059 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3060 reg = <0 0x08804000 0 0x1000>; 3061 3062 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3064 interrupt-names = "hc_irq", "pwr_irq"; 3065 3066 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3067 <&gcc GCC_SDCC2_APPS_CLK>, 3068 <&rpmhcc RPMH_CXO_CLK>; 3069 clock-names = "iface", "core", "xo"; 3070 resets = <&gcc GCC_SDCC2_BCR>; 3071 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3072 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3073 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3074 iommus = <&apps_smmu 0x4e0 0x0>; 3075 power-domains = <&rpmhpd SC8280XP_CX>; 3076 operating-points-v2 = <&sdc2_opp_table>; 3077 bus-width = <4>; 3078 dma-coherent; 3079 3080 status = "disabled"; 3081 3082 sdc2_opp_table: opp-table { 3083 compatible = "operating-points-v2"; 3084 3085 opp-100000000 { 3086 opp-hz = /bits/ 64 <100000000>; 3087 required-opps = <&rpmhpd_opp_low_svs>; 3088 opp-peak-kBps = <1800000 400000>; 3089 opp-avg-kBps = <100000 0>; 3090 }; 3091 3092 opp-202000000 { 3093 opp-hz = /bits/ 64 <202000000>; 3094 required-opps = <&rpmhpd_opp_svs_l1>; 3095 opp-peak-kBps = <5400000 1600000>; 3096 opp-avg-kBps = <200000 0>; 3097 }; 3098 }; 3099 }; 3100 3101 usb_0_qmpphy: phy@88eb000 { 3102 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3103 reg = <0 0x088eb000 0 0x4000>; 3104 3105 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3106 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3107 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3108 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3109 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3110 3111 power-domains = <&gcc USB30_PRIM_GDSC>; 3112 3113 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3114 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3115 reset-names = "phy", "common"; 3116 3117 #clock-cells = <1>; 3118 #phy-cells = <1>; 3119 3120 status = "disabled"; 3121 3122 ports { 3123 #address-cells = <1>; 3124 #size-cells = <0>; 3125 3126 port@0 { 3127 reg = <0>; 3128 3129 usb_0_qmpphy_out: endpoint {}; 3130 }; 3131 3132 port@2 { 3133 reg = <2>; 3134 3135 usb_0_qmpphy_dp_in: endpoint {}; 3136 }; 3137 }; 3138 }; 3139 3140 usb_1_hsphy: phy@8902000 { 3141 compatible = "qcom,sc8280xp-usb-hs-phy", 3142 "qcom,usb-snps-hs-5nm-phy"; 3143 reg = <0 0x08902000 0 0x400>; 3144 #phy-cells = <0>; 3145 3146 clocks = <&rpmhcc RPMH_CXO_CLK>; 3147 clock-names = "ref"; 3148 3149 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3150 3151 status = "disabled"; 3152 }; 3153 3154 usb_1_qmpphy: phy@8903000 { 3155 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3156 reg = <0 0x08903000 0 0x4000>; 3157 3158 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3159 <&gcc GCC_USB4_CLKREF_CLK>, 3160 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3161 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3162 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3163 3164 power-domains = <&gcc USB30_SEC_GDSC>; 3165 3166 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3167 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3168 reset-names = "phy", "common"; 3169 3170 #clock-cells = <1>; 3171 #phy-cells = <1>; 3172 3173 status = "disabled"; 3174 3175 ports { 3176 #address-cells = <1>; 3177 #size-cells = <0>; 3178 3179 port@0 { 3180 reg = <0>; 3181 3182 usb_1_qmpphy_out: endpoint {}; 3183 }; 3184 3185 port@2 { 3186 reg = <2>; 3187 3188 usb_1_qmpphy_dp_in: endpoint {}; 3189 }; 3190 }; 3191 }; 3192 3193 mdss1_dp0_phy: phy@8909a00 { 3194 compatible = "qcom,sc8280xp-dp-phy"; 3195 reg = <0 0x08909a00 0 0x19c>, 3196 <0 0x08909200 0 0xec>, 3197 <0 0x08909600 0 0xec>, 3198 <0 0x08909000 0 0x1c8>; 3199 3200 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3201 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3202 clock-names = "aux", "cfg_ahb"; 3203 power-domains = <&rpmhpd SC8280XP_MX>; 3204 3205 #clock-cells = <1>; 3206 #phy-cells = <0>; 3207 3208 status = "disabled"; 3209 }; 3210 3211 mdss1_dp1_phy: phy@890ca00 { 3212 compatible = "qcom,sc8280xp-dp-phy"; 3213 reg = <0 0x0890ca00 0 0x19c>, 3214 <0 0x0890c200 0 0xec>, 3215 <0 0x0890c600 0 0xec>, 3216 <0 0x0890c000 0 0x1c8>; 3217 3218 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3219 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3220 clock-names = "aux", "cfg_ahb"; 3221 power-domains = <&rpmhpd SC8280XP_MX>; 3222 3223 #clock-cells = <1>; 3224 #phy-cells = <0>; 3225 3226 status = "disabled"; 3227 }; 3228 3229 pmu@9091000 { 3230 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3231 reg = <0 0x09091000 0 0x1000>; 3232 3233 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3234 3235 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3236 3237 operating-points-v2 = <&llcc_bwmon_opp_table>; 3238 3239 llcc_bwmon_opp_table: opp-table { 3240 compatible = "operating-points-v2"; 3241 3242 opp-0 { 3243 opp-peak-kBps = <762000>; 3244 }; 3245 opp-1 { 3246 opp-peak-kBps = <1720000>; 3247 }; 3248 opp-2 { 3249 opp-peak-kBps = <2086000>; 3250 }; 3251 opp-3 { 3252 opp-peak-kBps = <2597000>; 3253 }; 3254 opp-4 { 3255 opp-peak-kBps = <2929000>; 3256 }; 3257 opp-5 { 3258 opp-peak-kBps = <3879000>; 3259 }; 3260 opp-6 { 3261 opp-peak-kBps = <5161000>; 3262 }; 3263 opp-7 { 3264 opp-peak-kBps = <5931000>; 3265 }; 3266 opp-8 { 3267 opp-peak-kBps = <6515000>; 3268 }; 3269 opp-9 { 3270 opp-peak-kBps = <7980000>; 3271 }; 3272 opp-10 { 3273 opp-peak-kBps = <8136000>; 3274 }; 3275 opp-11 { 3276 opp-peak-kBps = <10437000>; 3277 }; 3278 opp-12 { 3279 opp-peak-kBps = <12191000>; 3280 }; 3281 }; 3282 }; 3283 3284 pmu@90b6400 { 3285 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3286 reg = <0 0x090b6400 0 0x600>; 3287 3288 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3289 3290 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3291 operating-points-v2 = <&cpu_bwmon_opp_table>; 3292 3293 cpu_bwmon_opp_table: opp-table { 3294 compatible = "operating-points-v2"; 3295 3296 opp-0 { 3297 opp-peak-kBps = <2288000>; 3298 }; 3299 opp-1 { 3300 opp-peak-kBps = <4577000>; 3301 }; 3302 opp-2 { 3303 opp-peak-kBps = <7110000>; 3304 }; 3305 opp-3 { 3306 opp-peak-kBps = <9155000>; 3307 }; 3308 opp-4 { 3309 opp-peak-kBps = <12298000>; 3310 }; 3311 opp-5 { 3312 opp-peak-kBps = <14236000>; 3313 }; 3314 opp-6 { 3315 opp-peak-kBps = <15258001>; 3316 }; 3317 }; 3318 }; 3319 3320 system-cache-controller@9200000 { 3321 compatible = "qcom,sc8280xp-llcc"; 3322 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3323 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3324 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3325 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3326 <0 0x09600000 0 0x58000>; 3327 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3328 "llcc3_base", "llcc4_base", "llcc5_base", 3329 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3330 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3331 }; 3332 3333 usb_0: usb@a6f8800 { 3334 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3335 reg = <0 0x0a6f8800 0 0x400>; 3336 #address-cells = <2>; 3337 #size-cells = <2>; 3338 ranges; 3339 3340 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3341 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3342 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3343 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3344 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3345 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3346 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3347 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3348 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3349 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3350 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3351 3352 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3353 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3354 assigned-clock-rates = <19200000>, <200000000>; 3355 3356 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3357 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3358 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3359 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3360 interrupt-names = "pwr_event", 3361 "dp_hs_phy_irq", 3362 "dm_hs_phy_irq", 3363 "ss_phy_irq"; 3364 3365 power-domains = <&gcc USB30_PRIM_GDSC>; 3366 required-opps = <&rpmhpd_opp_nom>; 3367 3368 resets = <&gcc GCC_USB30_PRIM_BCR>; 3369 3370 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3371 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3372 interconnect-names = "usb-ddr", "apps-usb"; 3373 3374 wakeup-source; 3375 3376 status = "disabled"; 3377 3378 usb_0_dwc3: usb@a600000 { 3379 compatible = "snps,dwc3"; 3380 reg = <0 0x0a600000 0 0xcd00>; 3381 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3382 iommus = <&apps_smmu 0x820 0x0>; 3383 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3384 phy-names = "usb2-phy", "usb3-phy"; 3385 3386 port { 3387 usb_0_role_switch: endpoint { 3388 }; 3389 }; 3390 }; 3391 }; 3392 3393 usb_1: usb@a8f8800 { 3394 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3395 reg = <0 0x0a8f8800 0 0x400>; 3396 #address-cells = <2>; 3397 #size-cells = <2>; 3398 ranges; 3399 3400 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3401 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3402 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3403 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3404 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3405 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3406 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3407 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3408 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3409 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3410 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3411 3412 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3413 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3414 assigned-clock-rates = <19200000>, <200000000>; 3415 3416 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3417 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3418 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3419 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3420 interrupt-names = "pwr_event", 3421 "dp_hs_phy_irq", 3422 "dm_hs_phy_irq", 3423 "ss_phy_irq"; 3424 3425 power-domains = <&gcc USB30_SEC_GDSC>; 3426 required-opps = <&rpmhpd_opp_nom>; 3427 3428 resets = <&gcc GCC_USB30_SEC_BCR>; 3429 3430 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3431 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3432 interconnect-names = "usb-ddr", "apps-usb"; 3433 3434 wakeup-source; 3435 3436 status = "disabled"; 3437 3438 usb_1_dwc3: usb@a800000 { 3439 compatible = "snps,dwc3"; 3440 reg = <0 0x0a800000 0 0xcd00>; 3441 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3442 iommus = <&apps_smmu 0x860 0x0>; 3443 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3444 phy-names = "usb2-phy", "usb3-phy"; 3445 3446 port { 3447 usb_1_role_switch: endpoint { 3448 }; 3449 }; 3450 }; 3451 }; 3452 3453 mdss0: display-subsystem@ae00000 { 3454 compatible = "qcom,sc8280xp-mdss"; 3455 reg = <0 0x0ae00000 0 0x1000>; 3456 reg-names = "mdss"; 3457 3458 clocks = <&gcc GCC_DISP_AHB_CLK>, 3459 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3460 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3461 clock-names = "iface", 3462 "ahb", 3463 "core"; 3464 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3465 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3466 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3467 interconnect-names = "mdp0-mem", "mdp1-mem"; 3468 iommus = <&apps_smmu 0x1000 0x402>; 3469 power-domains = <&dispcc0 MDSS_GDSC>; 3470 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3471 3472 interrupt-controller; 3473 #interrupt-cells = <1>; 3474 #address-cells = <2>; 3475 #size-cells = <2>; 3476 ranges; 3477 3478 status = "disabled"; 3479 3480 mdss0_mdp: display-controller@ae01000 { 3481 compatible = "qcom,sc8280xp-dpu"; 3482 reg = <0 0x0ae01000 0 0x8f000>, 3483 <0 0x0aeb0000 0 0x2008>; 3484 reg-names = "mdp", "vbif"; 3485 3486 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3487 <&gcc GCC_DISP_SF_AXI_CLK>, 3488 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3489 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3490 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3491 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3492 clock-names = "bus", 3493 "nrt_bus", 3494 "iface", 3495 "lut", 3496 "core", 3497 "vsync"; 3498 interrupt-parent = <&mdss0>; 3499 interrupts = <0>; 3500 power-domains = <&rpmhpd SC8280XP_MMCX>; 3501 3502 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3503 assigned-clock-rates = <19200000>; 3504 operating-points-v2 = <&mdss0_mdp_opp_table>; 3505 3506 ports { 3507 #address-cells = <1>; 3508 #size-cells = <0>; 3509 3510 port@0 { 3511 reg = <0>; 3512 mdss0_intf0_out: endpoint { 3513 remote-endpoint = <&mdss0_dp0_in>; 3514 }; 3515 }; 3516 3517 port@4 { 3518 reg = <4>; 3519 mdss0_intf4_out: endpoint { 3520 remote-endpoint = <&mdss0_dp1_in>; 3521 }; 3522 }; 3523 3524 port@5 { 3525 reg = <5>; 3526 mdss0_intf5_out: endpoint { 3527 remote-endpoint = <&mdss0_dp3_in>; 3528 }; 3529 }; 3530 3531 port@6 { 3532 reg = <6>; 3533 mdss0_intf6_out: endpoint { 3534 remote-endpoint = <&mdss0_dp2_in>; 3535 }; 3536 }; 3537 }; 3538 3539 mdss0_mdp_opp_table: opp-table { 3540 compatible = "operating-points-v2"; 3541 3542 opp-200000000 { 3543 opp-hz = /bits/ 64 <200000000>; 3544 required-opps = <&rpmhpd_opp_low_svs>; 3545 }; 3546 3547 opp-300000000 { 3548 opp-hz = /bits/ 64 <300000000>; 3549 required-opps = <&rpmhpd_opp_svs>; 3550 }; 3551 3552 opp-375000000 { 3553 opp-hz = /bits/ 64 <375000000>; 3554 required-opps = <&rpmhpd_opp_svs_l1>; 3555 }; 3556 3557 opp-500000000 { 3558 opp-hz = /bits/ 64 <500000000>; 3559 required-opps = <&rpmhpd_opp_nom>; 3560 }; 3561 opp-600000000 { 3562 opp-hz = /bits/ 64 <600000000>; 3563 required-opps = <&rpmhpd_opp_turbo_l1>; 3564 }; 3565 }; 3566 }; 3567 3568 mdss0_dp0: displayport-controller@ae90000 { 3569 compatible = "qcom,sc8280xp-dp"; 3570 reg = <0 0xae90000 0 0x200>, 3571 <0 0xae90200 0 0x200>, 3572 <0 0xae90400 0 0x600>, 3573 <0 0xae91000 0 0x400>, 3574 <0 0xae91400 0 0x400>; 3575 interrupt-parent = <&mdss0>; 3576 interrupts = <12>; 3577 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3578 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3579 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3580 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3581 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3582 clock-names = "core_iface", "core_aux", 3583 "ctrl_link", 3584 "ctrl_link_iface", 3585 "stream_pixel"; 3586 3587 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3588 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3589 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3590 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3591 3592 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3593 phy-names = "dp"; 3594 3595 #sound-dai-cells = <0>; 3596 3597 operating-points-v2 = <&mdss0_dp0_opp_table>; 3598 power-domains = <&rpmhpd SC8280XP_MMCX>; 3599 3600 status = "disabled"; 3601 3602 ports { 3603 #address-cells = <1>; 3604 #size-cells = <0>; 3605 3606 port@0 { 3607 reg = <0>; 3608 3609 mdss0_dp0_in: endpoint { 3610 remote-endpoint = <&mdss0_intf0_out>; 3611 }; 3612 }; 3613 3614 port@1 { 3615 reg = <1>; 3616 3617 mdss0_dp0_out: endpoint { 3618 }; 3619 }; 3620 }; 3621 3622 mdss0_dp0_opp_table: opp-table { 3623 compatible = "operating-points-v2"; 3624 3625 opp-160000000 { 3626 opp-hz = /bits/ 64 <160000000>; 3627 required-opps = <&rpmhpd_opp_low_svs>; 3628 }; 3629 3630 opp-270000000 { 3631 opp-hz = /bits/ 64 <270000000>; 3632 required-opps = <&rpmhpd_opp_svs>; 3633 }; 3634 3635 opp-540000000 { 3636 opp-hz = /bits/ 64 <540000000>; 3637 required-opps = <&rpmhpd_opp_svs_l1>; 3638 }; 3639 3640 opp-810000000 { 3641 opp-hz = /bits/ 64 <810000000>; 3642 required-opps = <&rpmhpd_opp_nom>; 3643 }; 3644 }; 3645 }; 3646 3647 mdss0_dp1: displayport-controller@ae98000 { 3648 compatible = "qcom,sc8280xp-dp"; 3649 reg = <0 0xae98000 0 0x200>, 3650 <0 0xae98200 0 0x200>, 3651 <0 0xae98400 0 0x600>, 3652 <0 0xae99000 0 0x400>, 3653 <0 0xae99400 0 0x400>; 3654 interrupt-parent = <&mdss0>; 3655 interrupts = <13>; 3656 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3657 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3658 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3659 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3660 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3661 clock-names = "core_iface", "core_aux", 3662 "ctrl_link", 3663 "ctrl_link_iface", "stream_pixel"; 3664 3665 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3666 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3667 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3668 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3669 3670 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3671 phy-names = "dp"; 3672 3673 #sound-dai-cells = <0>; 3674 3675 operating-points-v2 = <&mdss0_dp1_opp_table>; 3676 power-domains = <&rpmhpd SC8280XP_MMCX>; 3677 3678 status = "disabled"; 3679 3680 ports { 3681 #address-cells = <1>; 3682 #size-cells = <0>; 3683 3684 port@0 { 3685 reg = <0>; 3686 3687 mdss0_dp1_in: endpoint { 3688 remote-endpoint = <&mdss0_intf4_out>; 3689 }; 3690 }; 3691 3692 port@1 { 3693 reg = <1>; 3694 3695 mdss0_dp1_out: endpoint { 3696 }; 3697 }; 3698 }; 3699 3700 mdss0_dp1_opp_table: opp-table { 3701 compatible = "operating-points-v2"; 3702 3703 opp-160000000 { 3704 opp-hz = /bits/ 64 <160000000>; 3705 required-opps = <&rpmhpd_opp_low_svs>; 3706 }; 3707 3708 opp-270000000 { 3709 opp-hz = /bits/ 64 <270000000>; 3710 required-opps = <&rpmhpd_opp_svs>; 3711 }; 3712 3713 opp-540000000 { 3714 opp-hz = /bits/ 64 <540000000>; 3715 required-opps = <&rpmhpd_opp_svs_l1>; 3716 }; 3717 3718 opp-810000000 { 3719 opp-hz = /bits/ 64 <810000000>; 3720 required-opps = <&rpmhpd_opp_nom>; 3721 }; 3722 }; 3723 }; 3724 3725 mdss0_dp2: displayport-controller@ae9a000 { 3726 compatible = "qcom,sc8280xp-dp"; 3727 reg = <0 0xae9a000 0 0x200>, 3728 <0 0xae9a200 0 0x200>, 3729 <0 0xae9a400 0 0x600>, 3730 <0 0xae9b000 0 0x400>, 3731 <0 0xae9b400 0 0x400>; 3732 3733 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3734 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3735 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3736 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3737 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3738 clock-names = "core_iface", "core_aux", 3739 "ctrl_link", 3740 "ctrl_link_iface", "stream_pixel"; 3741 interrupt-parent = <&mdss0>; 3742 interrupts = <14>; 3743 phys = <&mdss0_dp2_phy>; 3744 phy-names = "dp"; 3745 power-domains = <&rpmhpd SC8280XP_MMCX>; 3746 3747 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3748 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3749 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3750 operating-points-v2 = <&mdss0_dp2_opp_table>; 3751 3752 #sound-dai-cells = <0>; 3753 3754 status = "disabled"; 3755 3756 ports { 3757 #address-cells = <1>; 3758 #size-cells = <0>; 3759 3760 port@0 { 3761 reg = <0>; 3762 mdss0_dp2_in: endpoint { 3763 remote-endpoint = <&mdss0_intf6_out>; 3764 }; 3765 }; 3766 3767 port@1 { 3768 reg = <1>; 3769 }; 3770 }; 3771 3772 mdss0_dp2_opp_table: opp-table { 3773 compatible = "operating-points-v2"; 3774 3775 opp-160000000 { 3776 opp-hz = /bits/ 64 <160000000>; 3777 required-opps = <&rpmhpd_opp_low_svs>; 3778 }; 3779 3780 opp-270000000 { 3781 opp-hz = /bits/ 64 <270000000>; 3782 required-opps = <&rpmhpd_opp_svs>; 3783 }; 3784 3785 opp-540000000 { 3786 opp-hz = /bits/ 64 <540000000>; 3787 required-opps = <&rpmhpd_opp_svs_l1>; 3788 }; 3789 3790 opp-810000000 { 3791 opp-hz = /bits/ 64 <810000000>; 3792 required-opps = <&rpmhpd_opp_nom>; 3793 }; 3794 }; 3795 }; 3796 3797 mdss0_dp3: displayport-controller@aea0000 { 3798 compatible = "qcom,sc8280xp-dp"; 3799 reg = <0 0xaea0000 0 0x200>, 3800 <0 0xaea0200 0 0x200>, 3801 <0 0xaea0400 0 0x600>, 3802 <0 0xaea1000 0 0x400>, 3803 <0 0xaea1400 0 0x400>; 3804 3805 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3806 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3807 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3808 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3809 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3810 clock-names = "core_iface", "core_aux", 3811 "ctrl_link", 3812 "ctrl_link_iface", "stream_pixel"; 3813 interrupt-parent = <&mdss0>; 3814 interrupts = <15>; 3815 phys = <&mdss0_dp3_phy>; 3816 phy-names = "dp"; 3817 power-domains = <&rpmhpd SC8280XP_MMCX>; 3818 3819 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3820 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3821 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3822 operating-points-v2 = <&mdss0_dp3_opp_table>; 3823 3824 #sound-dai-cells = <0>; 3825 3826 status = "disabled"; 3827 3828 ports { 3829 #address-cells = <1>; 3830 #size-cells = <0>; 3831 3832 port@0 { 3833 reg = <0>; 3834 mdss0_dp3_in: endpoint { 3835 remote-endpoint = <&mdss0_intf5_out>; 3836 }; 3837 }; 3838 3839 port@1 { 3840 reg = <1>; 3841 }; 3842 }; 3843 3844 mdss0_dp3_opp_table: opp-table { 3845 compatible = "operating-points-v2"; 3846 3847 opp-160000000 { 3848 opp-hz = /bits/ 64 <160000000>; 3849 required-opps = <&rpmhpd_opp_low_svs>; 3850 }; 3851 3852 opp-270000000 { 3853 opp-hz = /bits/ 64 <270000000>; 3854 required-opps = <&rpmhpd_opp_svs>; 3855 }; 3856 3857 opp-540000000 { 3858 opp-hz = /bits/ 64 <540000000>; 3859 required-opps = <&rpmhpd_opp_svs_l1>; 3860 }; 3861 3862 opp-810000000 { 3863 opp-hz = /bits/ 64 <810000000>; 3864 required-opps = <&rpmhpd_opp_nom>; 3865 }; 3866 }; 3867 }; 3868 }; 3869 3870 mdss0_dp2_phy: phy@aec2a00 { 3871 compatible = "qcom,sc8280xp-dp-phy"; 3872 reg = <0 0x0aec2a00 0 0x19c>, 3873 <0 0x0aec2200 0 0xec>, 3874 <0 0x0aec2600 0 0xec>, 3875 <0 0x0aec2000 0 0x1c8>; 3876 3877 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3878 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3879 clock-names = "aux", "cfg_ahb"; 3880 power-domains = <&rpmhpd SC8280XP_MX>; 3881 3882 #clock-cells = <1>; 3883 #phy-cells = <0>; 3884 3885 status = "disabled"; 3886 }; 3887 3888 mdss0_dp3_phy: phy@aec5a00 { 3889 compatible = "qcom,sc8280xp-dp-phy"; 3890 reg = <0 0x0aec5a00 0 0x19c>, 3891 <0 0x0aec5200 0 0xec>, 3892 <0 0x0aec5600 0 0xec>, 3893 <0 0x0aec5000 0 0x1c8>; 3894 3895 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3896 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3897 clock-names = "aux", "cfg_ahb"; 3898 power-domains = <&rpmhpd SC8280XP_MX>; 3899 3900 #clock-cells = <1>; 3901 #phy-cells = <0>; 3902 3903 status = "disabled"; 3904 }; 3905 3906 dispcc0: clock-controller@af00000 { 3907 compatible = "qcom,sc8280xp-dispcc0"; 3908 reg = <0 0x0af00000 0 0x20000>; 3909 3910 clocks = <&gcc GCC_DISP_AHB_CLK>, 3911 <&rpmhcc RPMH_CXO_CLK>, 3912 <&sleep_clk>, 3913 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3914 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3915 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3916 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3917 <&mdss0_dp2_phy 0>, 3918 <&mdss0_dp2_phy 1>, 3919 <&mdss0_dp3_phy 0>, 3920 <&mdss0_dp3_phy 1>, 3921 <0>, 3922 <0>, 3923 <0>, 3924 <0>; 3925 power-domains = <&rpmhpd SC8280XP_MMCX>; 3926 3927 #clock-cells = <1>; 3928 #power-domain-cells = <1>; 3929 #reset-cells = <1>; 3930 3931 status = "disabled"; 3932 }; 3933 3934 pdc: interrupt-controller@b220000 { 3935 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3936 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3937 qcom,pdc-ranges = <0 480 40>, 3938 <40 140 14>, 3939 <54 263 1>, 3940 <55 306 4>, 3941 <59 312 3>, 3942 <62 374 2>, 3943 <64 434 2>, 3944 <66 438 3>, 3945 <69 86 1>, 3946 <70 520 54>, 3947 <124 609 28>, 3948 <159 638 1>, 3949 <160 720 8>, 3950 <168 801 1>, 3951 <169 728 30>, 3952 <199 416 2>, 3953 <201 449 1>, 3954 <202 89 1>, 3955 <203 451 1>, 3956 <204 462 1>, 3957 <205 264 1>, 3958 <206 579 1>, 3959 <207 653 1>, 3960 <208 656 1>, 3961 <209 659 1>, 3962 <210 122 1>, 3963 <211 699 1>, 3964 <212 705 1>, 3965 <213 450 1>, 3966 <214 643 1>, 3967 <216 646 5>, 3968 <221 390 5>, 3969 <226 700 3>, 3970 <229 240 3>, 3971 <232 269 1>, 3972 <233 377 1>, 3973 <234 372 1>, 3974 <235 138 1>, 3975 <236 857 1>, 3976 <237 860 1>, 3977 <238 137 1>, 3978 <239 668 1>, 3979 <240 366 1>, 3980 <241 949 1>, 3981 <242 815 5>, 3982 <247 769 1>, 3983 <248 768 1>, 3984 <249 663 1>, 3985 <250 799 2>, 3986 <252 798 1>, 3987 <253 765 1>, 3988 <254 763 1>, 3989 <255 454 1>, 3990 <258 139 1>, 3991 <259 786 2>, 3992 <261 370 2>, 3993 <263 158 2>; 3994 #interrupt-cells = <2>; 3995 interrupt-parent = <&intc>; 3996 interrupt-controller; 3997 }; 3998 3999 tsens0: thermal-sensor@c263000 { 4000 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4001 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4002 <0 0x0c222000 0 0x8>; /* SROT */ 4003 #qcom,sensors = <14>; 4004 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 4005 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 4006 interrupt-names = "uplow", "critical"; 4007 #thermal-sensor-cells = <1>; 4008 }; 4009 4010 tsens1: thermal-sensor@c265000 { 4011 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4012 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4013 <0 0x0c223000 0 0x8>; /* SROT */ 4014 #qcom,sensors = <16>; 4015 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4016 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4017 interrupt-names = "uplow", "critical"; 4018 #thermal-sensor-cells = <1>; 4019 }; 4020 4021 aoss_qmp: power-management@c300000 { 4022 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4023 reg = <0 0x0c300000 0 0x400>; 4024 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4025 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4026 4027 #clock-cells = <0>; 4028 }; 4029 4030 sram@c3f0000 { 4031 compatible = "qcom,rpmh-stats"; 4032 reg = <0 0x0c3f0000 0 0x400>; 4033 }; 4034 4035 spmi_bus: spmi@c440000 { 4036 compatible = "qcom,spmi-pmic-arb"; 4037 reg = <0 0x0c440000 0 0x1100>, 4038 <0 0x0c600000 0 0x2000000>, 4039 <0 0x0e600000 0 0x100000>, 4040 <0 0x0e700000 0 0xa0000>, 4041 <0 0x0c40a000 0 0x26000>; 4042 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4043 interrupt-names = "periph_irq"; 4044 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4045 qcom,ee = <0>; 4046 qcom,channel = <0>; 4047 #address-cells = <2>; 4048 #size-cells = <0>; 4049 interrupt-controller; 4050 #interrupt-cells = <4>; 4051 }; 4052 4053 tlmm: pinctrl@f100000 { 4054 compatible = "qcom,sc8280xp-tlmm"; 4055 reg = <0 0x0f100000 0 0x300000>; 4056 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4057 gpio-controller; 4058 #gpio-cells = <2>; 4059 interrupt-controller; 4060 #interrupt-cells = <2>; 4061 gpio-ranges = <&tlmm 0 0 230>; 4062 wakeup-parent = <&pdc>; 4063 }; 4064 4065 apps_smmu: iommu@15000000 { 4066 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 4067 reg = <0 0x15000000 0 0x100000>; 4068 #iommu-cells = <2>; 4069 #global-interrupts = <2>; 4070 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 4200 }; 4201 4202 intc: interrupt-controller@17a00000 { 4203 compatible = "arm,gic-v3"; 4204 interrupt-controller; 4205 #interrupt-cells = <3>; 4206 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4207 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4208 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4209 #redistributor-regions = <1>; 4210 redistributor-stride = <0 0x20000>; 4211 4212 #address-cells = <2>; 4213 #size-cells = <2>; 4214 ranges; 4215 4216 msi-controller@17a40000 { 4217 compatible = "arm,gic-v3-its"; 4218 reg = <0 0x17a40000 0 0x20000>; 4219 msi-controller; 4220 #msi-cells = <1>; 4221 }; 4222 }; 4223 4224 watchdog@17c10000 { 4225 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 4226 reg = <0 0x17c10000 0 0x1000>; 4227 clocks = <&sleep_clk>; 4228 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4229 }; 4230 4231 timer@17c20000 { 4232 compatible = "arm,armv7-timer-mem"; 4233 reg = <0x0 0x17c20000 0x0 0x1000>; 4234 #address-cells = <1>; 4235 #size-cells = <1>; 4236 ranges = <0x0 0x0 0x0 0x20000000>; 4237 4238 frame@17c21000 { 4239 frame-number = <0>; 4240 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4242 reg = <0x17c21000 0x1000>, 4243 <0x17c22000 0x1000>; 4244 }; 4245 4246 frame@17c23000 { 4247 frame-number = <1>; 4248 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4249 reg = <0x17c23000 0x1000>; 4250 status = "disabled"; 4251 }; 4252 4253 frame@17c25000 { 4254 frame-number = <2>; 4255 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4256 reg = <0x17c25000 0x1000>; 4257 status = "disabled"; 4258 }; 4259 4260 frame@17c27000 { 4261 frame-number = <3>; 4262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4263 reg = <0x17c26000 0x1000>; 4264 status = "disabled"; 4265 }; 4266 4267 frame@17c29000 { 4268 frame-number = <4>; 4269 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4270 reg = <0x17c29000 0x1000>; 4271 status = "disabled"; 4272 }; 4273 4274 frame@17c2b000 { 4275 frame-number = <5>; 4276 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4277 reg = <0x17c2b000 0x1000>; 4278 status = "disabled"; 4279 }; 4280 4281 frame@17c2d000 { 4282 frame-number = <6>; 4283 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4284 reg = <0x17c2d000 0x1000>; 4285 status = "disabled"; 4286 }; 4287 }; 4288 4289 apps_rsc: rsc@18200000 { 4290 compatible = "qcom,rpmh-rsc"; 4291 reg = <0x0 0x18200000 0x0 0x10000>, 4292 <0x0 0x18210000 0x0 0x10000>, 4293 <0x0 0x18220000 0x0 0x10000>; 4294 reg-names = "drv-0", "drv-1", "drv-2"; 4295 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4298 qcom,tcs-offset = <0xd00>; 4299 qcom,drv-id = <2>; 4300 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4301 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4302 label = "apps_rsc"; 4303 power-domains = <&CLUSTER_PD>; 4304 4305 apps_bcm_voter: bcm-voter { 4306 compatible = "qcom,bcm-voter"; 4307 }; 4308 4309 rpmhcc: clock-controller { 4310 compatible = "qcom,sc8280xp-rpmh-clk"; 4311 #clock-cells = <1>; 4312 clock-names = "xo"; 4313 clocks = <&xo_board_clk>; 4314 }; 4315 4316 rpmhpd: power-controller { 4317 compatible = "qcom,sc8280xp-rpmhpd"; 4318 #power-domain-cells = <1>; 4319 operating-points-v2 = <&rpmhpd_opp_table>; 4320 4321 rpmhpd_opp_table: opp-table { 4322 compatible = "operating-points-v2"; 4323 4324 rpmhpd_opp_ret: opp1 { 4325 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4326 }; 4327 4328 rpmhpd_opp_min_svs: opp2 { 4329 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4330 }; 4331 4332 rpmhpd_opp_low_svs: opp3 { 4333 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4334 }; 4335 4336 rpmhpd_opp_svs: opp4 { 4337 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4338 }; 4339 4340 rpmhpd_opp_svs_l1: opp5 { 4341 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4342 }; 4343 4344 rpmhpd_opp_nom: opp6 { 4345 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4346 }; 4347 4348 rpmhpd_opp_nom_l1: opp7 { 4349 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4350 }; 4351 4352 rpmhpd_opp_nom_l2: opp8 { 4353 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4354 }; 4355 4356 rpmhpd_opp_turbo: opp9 { 4357 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4358 }; 4359 4360 rpmhpd_opp_turbo_l1: opp10 { 4361 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4362 }; 4363 }; 4364 }; 4365 }; 4366 4367 epss_l3: interconnect@18590000 { 4368 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4369 reg = <0 0x18590000 0 0x1000>; 4370 4371 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4372 clock-names = "xo", "alternate"; 4373 4374 #interconnect-cells = <1>; 4375 }; 4376 4377 cpufreq_hw: cpufreq@18591000 { 4378 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4379 reg = <0 0x18591000 0 0x1000>, 4380 <0 0x18592000 0 0x1000>; 4381 reg-names = "freq-domain0", "freq-domain1"; 4382 4383 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4384 clock-names = "xo", "alternate"; 4385 4386 #freq-domain-cells = <1>; 4387 #clock-cells = <1>; 4388 }; 4389 4390 remoteproc_nsp0: remoteproc@1b300000 { 4391 compatible = "qcom,sc8280xp-nsp0-pas"; 4392 reg = <0 0x1b300000 0 0x100>; 4393 4394 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4395 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4396 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4397 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4398 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4399 interrupt-names = "wdog", "fatal", "ready", 4400 "handover", "stop-ack"; 4401 4402 clocks = <&rpmhcc RPMH_CXO_CLK>; 4403 clock-names = "xo"; 4404 4405 power-domains = <&rpmhpd SC8280XP_NSP>; 4406 power-domain-names = "nsp"; 4407 4408 memory-region = <&pil_nsp0_mem>; 4409 4410 qcom,smem-states = <&smp2p_nsp0_out 0>; 4411 qcom,smem-state-names = "stop"; 4412 4413 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4414 4415 status = "disabled"; 4416 4417 glink-edge { 4418 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4419 IPCC_MPROC_SIGNAL_GLINK_QMP 4420 IRQ_TYPE_EDGE_RISING>; 4421 mboxes = <&ipcc IPCC_CLIENT_CDSP 4422 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4423 4424 label = "nsp0"; 4425 qcom,remote-pid = <5>; 4426 4427 fastrpc { 4428 compatible = "qcom,fastrpc"; 4429 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4430 label = "cdsp"; 4431 #address-cells = <1>; 4432 #size-cells = <0>; 4433 4434 compute-cb@1 { 4435 compatible = "qcom,fastrpc-compute-cb"; 4436 reg = <1>; 4437 iommus = <&apps_smmu 0x3181 0x0420>; 4438 }; 4439 4440 compute-cb@2 { 4441 compatible = "qcom,fastrpc-compute-cb"; 4442 reg = <2>; 4443 iommus = <&apps_smmu 0x3182 0x0420>; 4444 }; 4445 4446 compute-cb@3 { 4447 compatible = "qcom,fastrpc-compute-cb"; 4448 reg = <3>; 4449 iommus = <&apps_smmu 0x3183 0x0420>; 4450 }; 4451 4452 compute-cb@4 { 4453 compatible = "qcom,fastrpc-compute-cb"; 4454 reg = <4>; 4455 iommus = <&apps_smmu 0x3184 0x0420>; 4456 }; 4457 4458 compute-cb@5 { 4459 compatible = "qcom,fastrpc-compute-cb"; 4460 reg = <5>; 4461 iommus = <&apps_smmu 0x3185 0x0420>; 4462 }; 4463 4464 compute-cb@6 { 4465 compatible = "qcom,fastrpc-compute-cb"; 4466 reg = <6>; 4467 iommus = <&apps_smmu 0x3186 0x0420>; 4468 }; 4469 4470 compute-cb@7 { 4471 compatible = "qcom,fastrpc-compute-cb"; 4472 reg = <7>; 4473 iommus = <&apps_smmu 0x3187 0x0420>; 4474 }; 4475 4476 compute-cb@8 { 4477 compatible = "qcom,fastrpc-compute-cb"; 4478 reg = <8>; 4479 iommus = <&apps_smmu 0x3188 0x0420>; 4480 }; 4481 4482 compute-cb@9 { 4483 compatible = "qcom,fastrpc-compute-cb"; 4484 reg = <9>; 4485 iommus = <&apps_smmu 0x318b 0x0420>; 4486 }; 4487 4488 compute-cb@10 { 4489 compatible = "qcom,fastrpc-compute-cb"; 4490 reg = <10>; 4491 iommus = <&apps_smmu 0x318b 0x0420>; 4492 }; 4493 4494 compute-cb@11 { 4495 compatible = "qcom,fastrpc-compute-cb"; 4496 reg = <11>; 4497 iommus = <&apps_smmu 0x318c 0x0420>; 4498 }; 4499 4500 compute-cb@12 { 4501 compatible = "qcom,fastrpc-compute-cb"; 4502 reg = <12>; 4503 iommus = <&apps_smmu 0x318d 0x0420>; 4504 }; 4505 4506 compute-cb@13 { 4507 compatible = "qcom,fastrpc-compute-cb"; 4508 reg = <13>; 4509 iommus = <&apps_smmu 0x318e 0x0420>; 4510 }; 4511 4512 compute-cb@14 { 4513 compatible = "qcom,fastrpc-compute-cb"; 4514 reg = <14>; 4515 iommus = <&apps_smmu 0x318f 0x0420>; 4516 }; 4517 }; 4518 }; 4519 }; 4520 4521 remoteproc_nsp1: remoteproc@21300000 { 4522 compatible = "qcom,sc8280xp-nsp1-pas"; 4523 reg = <0 0x21300000 0 0x100>; 4524 4525 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4526 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4527 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4528 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4529 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4530 interrupt-names = "wdog", "fatal", "ready", 4531 "handover", "stop-ack"; 4532 4533 clocks = <&rpmhcc RPMH_CXO_CLK>; 4534 clock-names = "xo"; 4535 4536 power-domains = <&rpmhpd SC8280XP_NSP>; 4537 power-domain-names = "nsp"; 4538 4539 memory-region = <&pil_nsp1_mem>; 4540 4541 qcom,smem-states = <&smp2p_nsp1_out 0>; 4542 qcom,smem-state-names = "stop"; 4543 4544 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4545 4546 status = "disabled"; 4547 4548 glink-edge { 4549 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4550 IPCC_MPROC_SIGNAL_GLINK_QMP 4551 IRQ_TYPE_EDGE_RISING>; 4552 mboxes = <&ipcc IPCC_CLIENT_NSP1 4553 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4554 4555 label = "nsp1"; 4556 qcom,remote-pid = <12>; 4557 }; 4558 }; 4559 4560 mdss1: display-subsystem@22000000 { 4561 compatible = "qcom,sc8280xp-mdss"; 4562 reg = <0 0x22000000 0 0x1000>; 4563 reg-names = "mdss"; 4564 4565 clocks = <&gcc GCC_DISP_AHB_CLK>, 4566 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4567 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4568 clock-names = "iface", 4569 "ahb", 4570 "core"; 4571 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4572 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4573 interconnect-names = "mdp0-mem", "mdp1-mem"; 4574 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4575 4576 iommus = <&apps_smmu 0x1800 0x402>; 4577 power-domains = <&dispcc1 MDSS_GDSC>; 4578 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4579 4580 interrupt-controller; 4581 #interrupt-cells = <1>; 4582 #address-cells = <2>; 4583 #size-cells = <2>; 4584 ranges; 4585 4586 status = "disabled"; 4587 4588 mdss1_mdp: display-controller@22001000 { 4589 compatible = "qcom,sc8280xp-dpu"; 4590 reg = <0 0x22001000 0 0x8f000>, 4591 <0 0x220b0000 0 0x2008>; 4592 reg-names = "mdp", "vbif"; 4593 4594 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4595 <&gcc GCC_DISP_SF_AXI_CLK>, 4596 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4597 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4598 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4599 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4600 clock-names = "bus", 4601 "nrt_bus", 4602 "iface", 4603 "lut", 4604 "core", 4605 "vsync"; 4606 interrupt-parent = <&mdss1>; 4607 interrupts = <0>; 4608 power-domains = <&rpmhpd SC8280XP_MMCX>; 4609 4610 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4611 assigned-clock-rates = <19200000>; 4612 operating-points-v2 = <&mdss1_mdp_opp_table>; 4613 4614 ports { 4615 #address-cells = <1>; 4616 #size-cells = <0>; 4617 4618 port@0 { 4619 reg = <0>; 4620 mdss1_intf0_out: endpoint { 4621 remote-endpoint = <&mdss1_dp0_in>; 4622 }; 4623 }; 4624 4625 port@4 { 4626 reg = <4>; 4627 mdss1_intf4_out: endpoint { 4628 remote-endpoint = <&mdss1_dp1_in>; 4629 }; 4630 }; 4631 4632 port@5 { 4633 reg = <5>; 4634 mdss1_intf5_out: endpoint { 4635 remote-endpoint = <&mdss1_dp3_in>; 4636 }; 4637 }; 4638 4639 port@6 { 4640 reg = <6>; 4641 mdss1_intf6_out: endpoint { 4642 remote-endpoint = <&mdss1_dp2_in>; 4643 }; 4644 }; 4645 }; 4646 4647 mdss1_mdp_opp_table: opp-table { 4648 compatible = "operating-points-v2"; 4649 4650 opp-200000000 { 4651 opp-hz = /bits/ 64 <200000000>; 4652 required-opps = <&rpmhpd_opp_low_svs>; 4653 }; 4654 4655 opp-300000000 { 4656 opp-hz = /bits/ 64 <300000000>; 4657 required-opps = <&rpmhpd_opp_svs>; 4658 }; 4659 4660 opp-375000000 { 4661 opp-hz = /bits/ 64 <375000000>; 4662 required-opps = <&rpmhpd_opp_svs_l1>; 4663 }; 4664 4665 opp-500000000 { 4666 opp-hz = /bits/ 64 <500000000>; 4667 required-opps = <&rpmhpd_opp_nom>; 4668 }; 4669 opp-600000000 { 4670 opp-hz = /bits/ 64 <600000000>; 4671 required-opps = <&rpmhpd_opp_turbo_l1>; 4672 }; 4673 }; 4674 }; 4675 4676 mdss1_dp0: displayport-controller@22090000 { 4677 compatible = "qcom,sc8280xp-dp"; 4678 reg = <0 0x22090000 0 0x200>, 4679 <0 0x22090200 0 0x200>, 4680 <0 0x22090400 0 0x600>, 4681 <0 0x22091000 0 0x400>, 4682 <0 0x22091400 0 0x400>; 4683 4684 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4685 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4686 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4687 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4688 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4689 clock-names = "core_iface", "core_aux", 4690 "ctrl_link", 4691 "ctrl_link_iface", "stream_pixel"; 4692 interrupt-parent = <&mdss1>; 4693 interrupts = <12>; 4694 phys = <&mdss1_dp0_phy>; 4695 phy-names = "dp"; 4696 power-domains = <&rpmhpd SC8280XP_MMCX>; 4697 4698 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4699 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4700 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4701 operating-points-v2 = <&mdss1_dp0_opp_table>; 4702 4703 #sound-dai-cells = <0>; 4704 4705 status = "disabled"; 4706 4707 ports { 4708 #address-cells = <1>; 4709 #size-cells = <0>; 4710 4711 port@0 { 4712 reg = <0>; 4713 mdss1_dp0_in: endpoint { 4714 remote-endpoint = <&mdss1_intf0_out>; 4715 }; 4716 }; 4717 4718 port@1 { 4719 reg = <1>; 4720 }; 4721 }; 4722 4723 mdss1_dp0_opp_table: opp-table { 4724 compatible = "operating-points-v2"; 4725 4726 opp-160000000 { 4727 opp-hz = /bits/ 64 <160000000>; 4728 required-opps = <&rpmhpd_opp_low_svs>; 4729 }; 4730 4731 opp-270000000 { 4732 opp-hz = /bits/ 64 <270000000>; 4733 required-opps = <&rpmhpd_opp_svs>; 4734 }; 4735 4736 opp-540000000 { 4737 opp-hz = /bits/ 64 <540000000>; 4738 required-opps = <&rpmhpd_opp_svs_l1>; 4739 }; 4740 4741 opp-810000000 { 4742 opp-hz = /bits/ 64 <810000000>; 4743 required-opps = <&rpmhpd_opp_nom>; 4744 }; 4745 }; 4746 }; 4747 4748 mdss1_dp1: displayport-controller@22098000 { 4749 compatible = "qcom,sc8280xp-dp"; 4750 reg = <0 0x22098000 0 0x200>, 4751 <0 0x22098200 0 0x200>, 4752 <0 0x22098400 0 0x600>, 4753 <0 0x22099000 0 0x400>, 4754 <0 0x22099400 0 0x400>; 4755 4756 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4757 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4758 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4759 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4760 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4761 clock-names = "core_iface", "core_aux", 4762 "ctrl_link", 4763 "ctrl_link_iface", "stream_pixel"; 4764 interrupt-parent = <&mdss1>; 4765 interrupts = <13>; 4766 phys = <&mdss1_dp1_phy>; 4767 phy-names = "dp"; 4768 power-domains = <&rpmhpd SC8280XP_MMCX>; 4769 4770 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4771 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4772 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4773 operating-points-v2 = <&mdss1_dp1_opp_table>; 4774 4775 #sound-dai-cells = <0>; 4776 4777 status = "disabled"; 4778 4779 ports { 4780 #address-cells = <1>; 4781 #size-cells = <0>; 4782 4783 port@0 { 4784 reg = <0>; 4785 mdss1_dp1_in: endpoint { 4786 remote-endpoint = <&mdss1_intf4_out>; 4787 }; 4788 }; 4789 4790 port@1 { 4791 reg = <1>; 4792 }; 4793 }; 4794 4795 mdss1_dp1_opp_table: opp-table { 4796 compatible = "operating-points-v2"; 4797 4798 opp-160000000 { 4799 opp-hz = /bits/ 64 <160000000>; 4800 required-opps = <&rpmhpd_opp_low_svs>; 4801 }; 4802 4803 opp-270000000 { 4804 opp-hz = /bits/ 64 <270000000>; 4805 required-opps = <&rpmhpd_opp_svs>; 4806 }; 4807 4808 opp-540000000 { 4809 opp-hz = /bits/ 64 <540000000>; 4810 required-opps = <&rpmhpd_opp_svs_l1>; 4811 }; 4812 4813 opp-810000000 { 4814 opp-hz = /bits/ 64 <810000000>; 4815 required-opps = <&rpmhpd_opp_nom>; 4816 }; 4817 }; 4818 }; 4819 4820 mdss1_dp2: displayport-controller@2209a000 { 4821 compatible = "qcom,sc8280xp-dp"; 4822 reg = <0 0x2209a000 0 0x200>, 4823 <0 0x2209a200 0 0x200>, 4824 <0 0x2209a400 0 0x600>, 4825 <0 0x2209b000 0 0x400>, 4826 <0 0x2209b400 0 0x400>; 4827 4828 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4829 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4830 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4831 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4832 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4833 clock-names = "core_iface", "core_aux", 4834 "ctrl_link", 4835 "ctrl_link_iface", "stream_pixel"; 4836 interrupt-parent = <&mdss1>; 4837 interrupts = <14>; 4838 phys = <&mdss1_dp2_phy>; 4839 phy-names = "dp"; 4840 power-domains = <&rpmhpd SC8280XP_MMCX>; 4841 4842 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4843 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4844 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4845 operating-points-v2 = <&mdss1_dp2_opp_table>; 4846 4847 #sound-dai-cells = <0>; 4848 4849 status = "disabled"; 4850 4851 ports { 4852 #address-cells = <1>; 4853 #size-cells = <0>; 4854 4855 port@0 { 4856 reg = <0>; 4857 mdss1_dp2_in: endpoint { 4858 remote-endpoint = <&mdss1_intf6_out>; 4859 }; 4860 }; 4861 4862 port@1 { 4863 reg = <1>; 4864 }; 4865 }; 4866 4867 mdss1_dp2_opp_table: opp-table { 4868 compatible = "operating-points-v2"; 4869 4870 opp-160000000 { 4871 opp-hz = /bits/ 64 <160000000>; 4872 required-opps = <&rpmhpd_opp_low_svs>; 4873 }; 4874 4875 opp-270000000 { 4876 opp-hz = /bits/ 64 <270000000>; 4877 required-opps = <&rpmhpd_opp_svs>; 4878 }; 4879 4880 opp-540000000 { 4881 opp-hz = /bits/ 64 <540000000>; 4882 required-opps = <&rpmhpd_opp_svs_l1>; 4883 }; 4884 4885 opp-810000000 { 4886 opp-hz = /bits/ 64 <810000000>; 4887 required-opps = <&rpmhpd_opp_nom>; 4888 }; 4889 }; 4890 }; 4891 4892 mdss1_dp3: displayport-controller@220a0000 { 4893 compatible = "qcom,sc8280xp-dp"; 4894 reg = <0 0x220a0000 0 0x200>, 4895 <0 0x220a0200 0 0x200>, 4896 <0 0x220a0400 0 0x600>, 4897 <0 0x220a1000 0 0x400>, 4898 <0 0x220a1400 0 0x400>; 4899 4900 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4901 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4902 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4903 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4904 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4905 clock-names = "core_iface", "core_aux", 4906 "ctrl_link", 4907 "ctrl_link_iface", "stream_pixel"; 4908 interrupt-parent = <&mdss1>; 4909 interrupts = <15>; 4910 phys = <&mdss1_dp3_phy>; 4911 phy-names = "dp"; 4912 power-domains = <&rpmhpd SC8280XP_MMCX>; 4913 4914 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4915 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4916 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4917 operating-points-v2 = <&mdss1_dp3_opp_table>; 4918 4919 #sound-dai-cells = <0>; 4920 4921 status = "disabled"; 4922 4923 ports { 4924 #address-cells = <1>; 4925 #size-cells = <0>; 4926 4927 port@0 { 4928 reg = <0>; 4929 mdss1_dp3_in: endpoint { 4930 remote-endpoint = <&mdss1_intf5_out>; 4931 }; 4932 }; 4933 4934 port@1 { 4935 reg = <1>; 4936 }; 4937 }; 4938 4939 mdss1_dp3_opp_table: opp-table { 4940 compatible = "operating-points-v2"; 4941 4942 opp-160000000 { 4943 opp-hz = /bits/ 64 <160000000>; 4944 required-opps = <&rpmhpd_opp_low_svs>; 4945 }; 4946 4947 opp-270000000 { 4948 opp-hz = /bits/ 64 <270000000>; 4949 required-opps = <&rpmhpd_opp_svs>; 4950 }; 4951 4952 opp-540000000 { 4953 opp-hz = /bits/ 64 <540000000>; 4954 required-opps = <&rpmhpd_opp_svs_l1>; 4955 }; 4956 4957 opp-810000000 { 4958 opp-hz = /bits/ 64 <810000000>; 4959 required-opps = <&rpmhpd_opp_nom>; 4960 }; 4961 }; 4962 }; 4963 }; 4964 4965 mdss1_dp2_phy: phy@220c2a00 { 4966 compatible = "qcom,sc8280xp-dp-phy"; 4967 reg = <0 0x220c2a00 0 0x19c>, 4968 <0 0x220c2200 0 0xec>, 4969 <0 0x220c2600 0 0xec>, 4970 <0 0x220c2000 0 0x1c8>; 4971 4972 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4973 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4974 clock-names = "aux", "cfg_ahb"; 4975 power-domains = <&rpmhpd SC8280XP_MX>; 4976 4977 #clock-cells = <1>; 4978 #phy-cells = <0>; 4979 4980 status = "disabled"; 4981 }; 4982 4983 mdss1_dp3_phy: phy@220c5a00 { 4984 compatible = "qcom,sc8280xp-dp-phy"; 4985 reg = <0 0x220c5a00 0 0x19c>, 4986 <0 0x220c5200 0 0xec>, 4987 <0 0x220c5600 0 0xec>, 4988 <0 0x220c5000 0 0x1c8>; 4989 4990 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4991 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4992 clock-names = "aux", "cfg_ahb"; 4993 power-domains = <&rpmhpd SC8280XP_MX>; 4994 4995 #clock-cells = <1>; 4996 #phy-cells = <0>; 4997 4998 status = "disabled"; 4999 }; 5000 5001 dispcc1: clock-controller@22100000 { 5002 compatible = "qcom,sc8280xp-dispcc1"; 5003 reg = <0 0x22100000 0 0x20000>; 5004 5005 clocks = <&gcc GCC_DISP_AHB_CLK>, 5006 <&rpmhcc RPMH_CXO_CLK>, 5007 <0>, 5008 <&mdss1_dp0_phy 0>, 5009 <&mdss1_dp0_phy 1>, 5010 <&mdss1_dp1_phy 0>, 5011 <&mdss1_dp1_phy 1>, 5012 <&mdss1_dp2_phy 0>, 5013 <&mdss1_dp2_phy 1>, 5014 <&mdss1_dp3_phy 0>, 5015 <&mdss1_dp3_phy 1>, 5016 <0>, 5017 <0>, 5018 <0>, 5019 <0>; 5020 power-domains = <&rpmhpd SC8280XP_MMCX>; 5021 5022 #clock-cells = <1>; 5023 #power-domain-cells = <1>; 5024 #reset-cells = <1>; 5025 5026 status = "disabled"; 5027 }; 5028 5029 ethernet1: ethernet@23000000 { 5030 compatible = "qcom,sc8280xp-ethqos"; 5031 reg = <0x0 0x23000000 0x0 0x10000>, 5032 <0x0 0x23016000 0x0 0x100>; 5033 reg-names = "stmmaceth", "rgmii"; 5034 5035 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 5036 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 5037 <&gcc GCC_EMAC1_PTP_CLK>, 5038 <&gcc GCC_EMAC1_RGMII_CLK>; 5039 clock-names = "stmmaceth", 5040 "pclk", 5041 "ptp_ref", 5042 "rgmii"; 5043 5044 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 5046 interrupt-names = "macirq", "eth_lpi"; 5047 5048 iommus = <&apps_smmu 0x40 0xf>; 5049 power-domains = <&gcc EMAC_1_GDSC>; 5050 5051 snps,tso; 5052 snps,pbl = <32>; 5053 rx-fifo-depth = <4096>; 5054 tx-fifo-depth = <4096>; 5055 5056 status = "disabled"; 5057 }; 5058 }; 5059 5060 sound: sound { 5061 }; 5062 5063 thermal-zones { 5064 cpu0-thermal { 5065 polling-delay-passive = <250>; 5066 polling-delay = <1000>; 5067 5068 thermal-sensors = <&tsens0 1>; 5069 5070 trips { 5071 cpu-crit { 5072 temperature = <110000>; 5073 hysteresis = <1000>; 5074 type = "critical"; 5075 }; 5076 }; 5077 }; 5078 5079 cpu1-thermal { 5080 polling-delay-passive = <250>; 5081 polling-delay = <1000>; 5082 5083 thermal-sensors = <&tsens0 2>; 5084 5085 trips { 5086 cpu-crit { 5087 temperature = <110000>; 5088 hysteresis = <1000>; 5089 type = "critical"; 5090 }; 5091 }; 5092 }; 5093 5094 cpu2-thermal { 5095 polling-delay-passive = <250>; 5096 polling-delay = <1000>; 5097 5098 thermal-sensors = <&tsens0 3>; 5099 5100 trips { 5101 cpu-crit { 5102 temperature = <110000>; 5103 hysteresis = <1000>; 5104 type = "critical"; 5105 }; 5106 }; 5107 }; 5108 5109 cpu3-thermal { 5110 polling-delay-passive = <250>; 5111 polling-delay = <1000>; 5112 5113 thermal-sensors = <&tsens0 4>; 5114 5115 trips { 5116 cpu-crit { 5117 temperature = <110000>; 5118 hysteresis = <1000>; 5119 type = "critical"; 5120 }; 5121 }; 5122 }; 5123 5124 cpu4-thermal { 5125 polling-delay-passive = <250>; 5126 polling-delay = <1000>; 5127 5128 thermal-sensors = <&tsens0 5>; 5129 5130 trips { 5131 cpu-crit { 5132 temperature = <110000>; 5133 hysteresis = <1000>; 5134 type = "critical"; 5135 }; 5136 }; 5137 }; 5138 5139 cpu5-thermal { 5140 polling-delay-passive = <250>; 5141 polling-delay = <1000>; 5142 5143 thermal-sensors = <&tsens0 6>; 5144 5145 trips { 5146 cpu-crit { 5147 temperature = <110000>; 5148 hysteresis = <1000>; 5149 type = "critical"; 5150 }; 5151 }; 5152 }; 5153 5154 cpu6-thermal { 5155 polling-delay-passive = <250>; 5156 polling-delay = <1000>; 5157 5158 thermal-sensors = <&tsens0 7>; 5159 5160 trips { 5161 cpu-crit { 5162 temperature = <110000>; 5163 hysteresis = <1000>; 5164 type = "critical"; 5165 }; 5166 }; 5167 }; 5168 5169 cpu7-thermal { 5170 polling-delay-passive = <250>; 5171 polling-delay = <1000>; 5172 5173 thermal-sensors = <&tsens0 8>; 5174 5175 trips { 5176 cpu-crit { 5177 temperature = <110000>; 5178 hysteresis = <1000>; 5179 type = "critical"; 5180 }; 5181 }; 5182 }; 5183 5184 cluster0-thermal { 5185 polling-delay-passive = <250>; 5186 polling-delay = <1000>; 5187 5188 thermal-sensors = <&tsens0 9>; 5189 5190 trips { 5191 cpu-crit { 5192 temperature = <110000>; 5193 hysteresis = <1000>; 5194 type = "critical"; 5195 }; 5196 }; 5197 }; 5198 5199 mem-thermal { 5200 polling-delay-passive = <250>; 5201 polling-delay = <1000>; 5202 5203 thermal-sensors = <&tsens1 15>; 5204 5205 trips { 5206 trip-point0 { 5207 temperature = <90000>; 5208 hysteresis = <2000>; 5209 type = "hot"; 5210 }; 5211 }; 5212 }; 5213 }; 5214 5215 timer { 5216 compatible = "arm,armv8-timer"; 5217 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5218 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5219 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5220 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5221 }; 5222}; 5223