1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Cheza device tree source (common between revisions) 4 * 5 * Copyright 2018 Google LLC. 6 */ 7 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 10#include "sdm845.dtsi" 11 12/* PMICs depend on spmi_bus label and so must come after SoC */ 13#include "pm8005.dtsi" 14#include "pm8998.dtsi" 15 16/ { 17 aliases { 18 bluetooth0 = &bluetooth; 19 hsuart0 = &uart6; 20 serial0 = &uart9; 21 wifi0 = &wifi; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 backlight: backlight { 29 compatible = "pwm-backlight"; 30 pwms = <&cros_ec_pwm 0>; 31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 32 power-supply = <&ppvar_sys>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&ap_edp_bklten>; 35 }; 36 37 /* FIXED REGULATORS - parents above children */ 38 39 /* This is the top level supply and variable voltage */ 40 ppvar_sys: ppvar-sys-regulator { 41 compatible = "regulator-fixed"; 42 regulator-name = "ppvar_sys"; 43 regulator-always-on; 44 regulator-boot-on; 45 }; 46 47 /* This divides ppvar_sys by 2, so voltage is variable */ 48 src_vph_pwr: src-vph-pwr-regulator { 49 compatible = "regulator-fixed"; 50 regulator-name = "src_vph_pwr"; 51 52 /* EC turns on with switchcap_on_l; always on for AP */ 53 regulator-always-on; 54 regulator-boot-on; 55 56 vin-supply = <&ppvar_sys>; 57 }; 58 59 pp5000_a: pp5000-a-regulator { 60 compatible = "regulator-fixed"; 61 regulator-name = "pp5000_a"; 62 63 /* EC turns on with en_pp5000_a; always on for AP */ 64 regulator-always-on; 65 regulator-boot-on; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 69 vin-supply = <&ppvar_sys>; 70 }; 71 72 src_vreg_bob: src-vreg-bob-regulator { 73 compatible = "regulator-fixed"; 74 regulator-name = "src_vreg_bob"; 75 76 /* EC turns on with vbob_en; always on for AP */ 77 regulator-always-on; 78 regulator-boot-on; 79 regulator-min-microvolt = <3600000>; 80 regulator-max-microvolt = <3600000>; 81 82 vin-supply = <&ppvar_sys>; 83 }; 84 85 pp3300_dx_edp: pp3300-dx-edp-regulator { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp3300_dx_edp"; 88 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 92 gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&en_pp3300_dx_edp>; 96 }; 97 98 /* 99 * Apparently RPMh does not provide support for PM8998 S4 because it 100 * is always-on; model it as a fixed regulator. 101 */ 102 src_pp1800_s4a: pm8998-smps4 { 103 compatible = "regulator-fixed"; 104 regulator-name = "src_pp1800_s4a"; 105 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 109 regulator-always-on; 110 regulator-boot-on; 111 112 vin-supply = <&src_vph_pwr>; 113 }; 114 115 /* BOARD-SPECIFIC TOP LEVEL NODES */ 116 117 gpio-keys { 118 compatible = "gpio-keys"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pen_eject_odl>; 121 122 switch-pen-insert { 123 label = "Pen Insert"; 124 /* Insert = low, eject = high */ 125 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 126 linux,code = <SW_PEN_INSERTED>; 127 linux,input-type = <EV_SW>; 128 wakeup-source; 129 }; 130 }; 131 132 panel: panel { 133 compatible = "innolux,p120zdg-bf1"; 134 power-supply = <&pp3300_dx_edp>; 135 backlight = <&backlight>; 136 no-hpd; 137 138 ports { 139 panel_in: port { 140 panel_in_edp: endpoint { 141 remote-endpoint = <&sn65dsi86_out>; 142 }; 143 }; 144 }; 145 }; 146}; 147 148&psci { 149 /delete-node/ cpu0; 150 /delete-node/ cpu1; 151 /delete-node/ cpu2; 152 /delete-node/ cpu3; 153 /delete-node/ cpu4; 154 /delete-node/ cpu5; 155 /delete-node/ cpu6; 156 /delete-node/ cpu7; 157 /delete-node/ cpu-cluster0; 158}; 159 160&cpus { 161 /delete-node/ domain-idle-states; 162}; 163 164&cpu_idle_states { 165 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 166 compatible = "arm,idle-state"; 167 idle-state-name = "little-power-down"; 168 arm,psci-suspend-param = <0x40000003>; 169 entry-latency-us = <350>; 170 exit-latency-us = <461>; 171 min-residency-us = <1890>; 172 local-timer-stop; 173 }; 174 175 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 176 compatible = "arm,idle-state"; 177 idle-state-name = "little-rail-power-down"; 178 arm,psci-suspend-param = <0x40000004>; 179 entry-latency-us = <360>; 180 exit-latency-us = <531>; 181 min-residency-us = <3934>; 182 local-timer-stop; 183 }; 184 185 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 186 compatible = "arm,idle-state"; 187 idle-state-name = "big-power-down"; 188 arm,psci-suspend-param = <0x40000003>; 189 entry-latency-us = <264>; 190 exit-latency-us = <621>; 191 min-residency-us = <952>; 192 local-timer-stop; 193 }; 194 195 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 196 compatible = "arm,idle-state"; 197 idle-state-name = "big-rail-power-down"; 198 arm,psci-suspend-param = <0x40000004>; 199 entry-latency-us = <702>; 200 exit-latency-us = <1061>; 201 min-residency-us = <4488>; 202 local-timer-stop; 203 }; 204 205 CLUSTER_SLEEP_0: cluster-sleep-0 { 206 compatible = "arm,idle-state"; 207 idle-state-name = "cluster-power-down"; 208 arm,psci-suspend-param = <0x400000F4>; 209 entry-latency-us = <3263>; 210 exit-latency-us = <6562>; 211 min-residency-us = <9987>; 212 local-timer-stop; 213 }; 214}; 215 216&CPU0 { 217 /delete-property/ power-domains; 218 /delete-property/ power-domain-names; 219 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 220 &LITTLE_CPU_SLEEP_1 221 &CLUSTER_SLEEP_0>; 222}; 223 224&CPU1 { 225 /delete-property/ power-domains; 226 /delete-property/ power-domain-names; 227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 228 &LITTLE_CPU_SLEEP_1 229 &CLUSTER_SLEEP_0>; 230}; 231 232&CPU2 { 233 /delete-property/ power-domains; 234 /delete-property/ power-domain-names; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238}; 239 240&CPU3 { 241 /delete-property/ power-domains; 242 /delete-property/ power-domain-names; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246}; 247 248&CPU4 { 249 /delete-property/ power-domains; 250 /delete-property/ power-domain-names; 251 cpu-idle-states = <&BIG_CPU_SLEEP_0 252 &BIG_CPU_SLEEP_1 253 &CLUSTER_SLEEP_0>; 254}; 255 256&CPU5 { 257 /delete-property/ power-domains; 258 /delete-property/ power-domain-names; 259 cpu-idle-states = <&BIG_CPU_SLEEP_0 260 &BIG_CPU_SLEEP_1 261 &CLUSTER_SLEEP_0>; 262}; 263 264&CPU6 { 265 /delete-property/ power-domains; 266 /delete-property/ power-domain-names; 267 cpu-idle-states = <&BIG_CPU_SLEEP_0 268 &BIG_CPU_SLEEP_1 269 &CLUSTER_SLEEP_0>; 270}; 271 272&CPU7 { 273 /delete-property/ power-domains; 274 /delete-property/ power-domain-names; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278}; 279 280/* 281 * Reserved memory changes 282 * 283 * Putting this all together (out of order with the rest of the file) to keep 284 * all modifications to the memory map (from sdm845.dtsi) in one place. 285 */ 286 287/* 288 * Our mpss_region is 8MB bigger than the default one and that conflicts 289 * with venus_mem and cdsp_mem. 290 * 291 * For venus_mem we'll delete and re-create at a different address. 292 * 293 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but 294 * that also means we need to delete cdsp_pas. 295 */ 296/delete-node/ &venus_mem; 297/delete-node/ &cdsp_mem; 298/delete-node/ &cdsp_pas; 299/delete-node/ &gpu_mem; 300 301/* Increase the size from 120 MB to 128 MB */ 302&mpss_region { 303 reg = <0 0x8e000000 0 0x8000000>; 304}; 305 306/* Increase the size from 2MB to 8MB */ 307&rmtfs_mem { 308 reg = <0 0x88f00000 0 0x800000>; 309}; 310 311/ { 312 reserved-memory { 313 venus_mem: memory@96000000 { 314 reg = <0 0x96000000 0 0x500000>; 315 no-map; 316 }; 317 }; 318}; 319 320&qspi { 321 status = "okay"; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; 324 325 flash@0 { 326 compatible = "jedec,spi-nor"; 327 reg = <0>; 328 329 /* 330 * In theory chip supports up to 104 MHz and controller up 331 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use 332 * that for now. b:117440651 333 */ 334 spi-max-frequency = <25000000>; 335 spi-tx-bus-width = <2>; 336 spi-rx-bus-width = <2>; 337 }; 338}; 339 340 341&apps_rsc { 342 pm8998-rpmh-regulators { 343 compatible = "qcom,pm8998-rpmh-regulators"; 344 qcom,pmic-id = "a"; 345 346 vdd-s1-supply = <&src_vph_pwr>; 347 vdd-s2-supply = <&src_vph_pwr>; 348 vdd-s3-supply = <&src_vph_pwr>; 349 vdd-s4-supply = <&src_vph_pwr>; 350 vdd-s5-supply = <&src_vph_pwr>; 351 vdd-s6-supply = <&src_vph_pwr>; 352 vdd-s7-supply = <&src_vph_pwr>; 353 vdd-s8-supply = <&src_vph_pwr>; 354 vdd-s9-supply = <&src_vph_pwr>; 355 vdd-s10-supply = <&src_vph_pwr>; 356 vdd-s11-supply = <&src_vph_pwr>; 357 vdd-s12-supply = <&src_vph_pwr>; 358 vdd-s13-supply = <&src_vph_pwr>; 359 vdd-l1-l27-supply = <&src_pp1025_s7a>; 360 vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; 361 vdd-l3-l11-supply = <&src_pp1025_s7a>; 362 vdd-l4-l5-supply = <&src_pp1025_s7a>; 363 vdd-l6-supply = <&src_vph_pwr>; 364 vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; 365 vdd-l9-supply = <&src_pp2040_s5a>; 366 vdd-l10-l23-l25-supply = <&src_vreg_bob>; 367 vdd-l13-l19-l21-supply = <&src_vreg_bob>; 368 vdd-l16-l28-supply = <&src_vreg_bob>; 369 vdd-l18-l22-supply = <&src_vreg_bob>; 370 vdd-l20-l24-supply = <&src_vreg_bob>; 371 vdd-l26-supply = <&src_pp1350_s3a>; 372 vin-lvs-1-2-supply = <&src_pp1800_s4a>; 373 374 src_pp1125_s2a: smps2 { 375 regulator-min-microvolt = <1100000>; 376 regulator-max-microvolt = <1100000>; 377 }; 378 379 src_pp1350_s3a: smps3 { 380 regulator-min-microvolt = <1352000>; 381 regulator-max-microvolt = <1352000>; 382 }; 383 384 src_pp2040_s5a: smps5 { 385 regulator-min-microvolt = <1904000>; 386 regulator-max-microvolt = <2040000>; 387 }; 388 389 src_pp1025_s7a: smps7 { 390 regulator-min-microvolt = <900000>; 391 regulator-max-microvolt = <1028000>; 392 }; 393 394 vdd_qusb_hs0: 395 vdda_hp_pcie_core: 396 vdda_mipi_csi0_0p9: 397 vdda_mipi_csi1_0p9: 398 vdda_mipi_csi2_0p9: 399 vdda_mipi_dsi0_pll: 400 vdda_mipi_dsi1_pll: 401 vdda_qlink_lv: 402 vdda_qlink_lv_ck: 403 vdda_qrefs_0p875: 404 vdda_pcie_core: 405 vdda_pll_cc_ebi01: 406 vdda_pll_cc_ebi23: 407 vdda_sp_sensor: 408 vdda_ufs1_core: 409 vdda_ufs2_core: 410 vdda_usb1_ss_core: 411 vdda_usb2_ss_core: 412 src_pp875_l1a: ldo1 { 413 regulator-min-microvolt = <880000>; 414 regulator-max-microvolt = <880000>; 415 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 416 }; 417 418 vddpx_10: 419 src_pp1200_l2a: ldo2 { 420 regulator-min-microvolt = <1200000>; 421 regulator-max-microvolt = <1200000>; 422 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 423 424 /* TODO: why??? */ 425 regulator-always-on; 426 }; 427 428 pp1000_l3a_sdr845: ldo3 { 429 regulator-min-microvolt = <1000000>; 430 regulator-max-microvolt = <1000000>; 431 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 432 }; 433 434 vdd_wcss_cx: 435 vdd_wcss_mx: 436 vdda_wcss_pll: 437 src_pp800_l5a: ldo5 { 438 regulator-min-microvolt = <800000>; 439 regulator-max-microvolt = <800000>; 440 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 441 }; 442 443 vddpx_13: 444 src_pp1800_l6a: ldo6 { 445 regulator-min-microvolt = <1856000>; 446 regulator-max-microvolt = <1856000>; 447 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 448 }; 449 450 pp1800_l7a_wcn3990: ldo7 { 451 regulator-min-microvolt = <1800000>; 452 regulator-max-microvolt = <1800000>; 453 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 454 }; 455 456 src_pp1200_l8a: ldo8 { 457 regulator-min-microvolt = <1200000>; 458 regulator-max-microvolt = <1248000>; 459 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 460 }; 461 462 pp1800_dx_pen: 463 src_pp1800_l9a: ldo9 { 464 regulator-min-microvolt = <1800000>; 465 regulator-max-microvolt = <1800000>; 466 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 467 }; 468 469 src_pp1800_l10a: ldo10 { 470 regulator-min-microvolt = <1800000>; 471 regulator-max-microvolt = <1800000>; 472 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 473 }; 474 475 pp1000_l11a_sdr845: ldo11 { 476 regulator-min-microvolt = <1000000>; 477 regulator-max-microvolt = <1048000>; 478 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 479 }; 480 481 vdd_qfprom: 482 vdd_qfprom_sp: 483 vdda_apc1_cs_1p8: 484 vdda_gfx_cs_1p8: 485 vdda_qrefs_1p8: 486 vdda_qusb_hs0_1p8: 487 vddpx_11: 488 src_pp1800_l12a: ldo12 { 489 regulator-min-microvolt = <1800000>; 490 regulator-max-microvolt = <1800000>; 491 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 492 }; 493 494 vddpx_2: 495 src_pp2950_l13a: ldo13 { 496 regulator-min-microvolt = <1800000>; 497 regulator-max-microvolt = <2960000>; 498 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 499 }; 500 501 src_pp1800_l14a: ldo14 { 502 regulator-min-microvolt = <1800000>; 503 regulator-max-microvolt = <1800000>; 504 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 505 }; 506 507 src_pp1800_l15a: ldo15 { 508 regulator-min-microvolt = <1800000>; 509 regulator-max-microvolt = <1800000>; 510 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 511 }; 512 513 pp2700_l16a: ldo16 { 514 regulator-min-microvolt = <2704000>; 515 regulator-max-microvolt = <2704000>; 516 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 517 }; 518 519 src_pp1300_l17a: ldo17 { 520 regulator-min-microvolt = <1304000>; 521 regulator-max-microvolt = <1304000>; 522 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 523 }; 524 525 pp2700_l18a: ldo18 { 526 regulator-min-microvolt = <2704000>; 527 regulator-max-microvolt = <2960000>; 528 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 529 }; 530 531 /* 532 * NOTE: this rail should have been called 533 * src_pp3300_l19a in the schematic 534 */ 535 src_pp3000_l19a: ldo19 { 536 regulator-min-microvolt = <3304000>; 537 regulator-max-microvolt = <3304000>; 538 539 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 540 }; 541 542 src_pp2950_l20a: ldo20 { 543 regulator-min-microvolt = <2704000>; 544 regulator-max-microvolt = <2960000>; 545 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 546 }; 547 548 src_pp2950_l21a: ldo21 { 549 regulator-min-microvolt = <2704000>; 550 regulator-max-microvolt = <2960000>; 551 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 552 }; 553 554 pp3300_hub: 555 src_pp3300_l22a: ldo22 { 556 regulator-min-microvolt = <3304000>; 557 regulator-max-microvolt = <3304000>; 558 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 559 /* 560 * HACK: Should add a usb hub node and driver 561 * to turn this on and off at suspend/resume time 562 */ 563 regulator-boot-on; 564 regulator-always-on; 565 }; 566 567 pp3300_l23a_ch1_wcn3990: ldo23 { 568 regulator-min-microvolt = <3000000>; 569 regulator-max-microvolt = <3312000>; 570 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 571 }; 572 573 vdda_qusb_hs0_3p1: 574 src_pp3075_l24a: ldo24 { 575 regulator-min-microvolt = <3088000>; 576 regulator-max-microvolt = <3088000>; 577 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 578 }; 579 580 pp3300_l25a_ch0_wcn3990: ldo25 { 581 regulator-min-microvolt = <3304000>; 582 regulator-max-microvolt = <3304000>; 583 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 584 }; 585 586 pp1200_hub: 587 vdda_hp_pcie_1p2: 588 vdda_hv_ebi0: 589 vdda_hv_ebi1: 590 vdda_hv_ebi2: 591 vdda_hv_ebi3: 592 vdda_mipi_csi_1p25: 593 vdda_mipi_dsi0_1p2: 594 vdda_mipi_dsi1_1p2: 595 vdda_pcie_1p2: 596 vdda_ufs1_1p2: 597 vdda_ufs2_1p2: 598 vdda_usb1_ss_1p2: 599 vdda_usb2_ss_1p2: 600 src_pp1200_l26a: ldo26 { 601 regulator-min-microvolt = <1200000>; 602 regulator-max-microvolt = <1200000>; 603 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 604 }; 605 606 pp3300_dx_pen: 607 src_pp3300_l28a: ldo28 { 608 regulator-min-microvolt = <3304000>; 609 regulator-max-microvolt = <3304000>; 610 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 611 }; 612 613 src_pp1800_lvs1: lvs1 { 614 regulator-min-microvolt = <1800000>; 615 regulator-max-microvolt = <1800000>; 616 }; 617 618 src_pp1800_lvs2: lvs2 { 619 regulator-min-microvolt = <1800000>; 620 regulator-max-microvolt = <1800000>; 621 }; 622 }; 623 624 pm8005-rpmh-regulators { 625 compatible = "qcom,pm8005-rpmh-regulators"; 626 qcom,pmic-id = "c"; 627 628 vdd-s1-supply = <&src_vph_pwr>; 629 vdd-s2-supply = <&src_vph_pwr>; 630 vdd-s3-supply = <&src_vph_pwr>; 631 vdd-s4-supply = <&src_vph_pwr>; 632 633 src_pp600_s3c: smps3 { 634 regulator-min-microvolt = <600000>; 635 regulator-max-microvolt = <600000>; 636 }; 637 }; 638}; 639 640&dsi0 { 641 status = "okay"; 642 vdda-supply = <&vdda_mipi_dsi0_1p2>; 643 644 ports { 645 port@1 { 646 endpoint { 647 remote-endpoint = <&sn65dsi86_in>; 648 data-lanes = <0 1 2 3>; 649 }; 650 }; 651 }; 652}; 653 654&dsi0_phy { 655 status = "okay"; 656 vdds-supply = <&vdda_mipi_dsi0_pll>; 657}; 658 659edp_brij_i2c: &i2c3 { 660 status = "okay"; 661 clock-frequency = <400000>; 662 663 sn65dsi86_bridge: bridge@2d { 664 compatible = "ti,sn65dsi86"; 665 reg = <0x2d>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&edp_brij_en &edp_brij_irq>; 668 669 interrupt-parent = <&tlmm>; 670 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 671 672 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 673 674 vpll-supply = <&src_pp1800_s4a>; 675 vccio-supply = <&src_pp1800_s4a>; 676 vcca-supply = <&src_pp1200_l2a>; 677 vcc-supply = <&src_pp1200_l2a>; 678 679 clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 680 clock-names = "refclk"; 681 682 no-hpd; 683 684 ports { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 688 port@0 { 689 reg = <0>; 690 sn65dsi86_in: endpoint { 691 remote-endpoint = <&dsi0_out>; 692 }; 693 }; 694 695 port@1 { 696 reg = <1>; 697 sn65dsi86_out: endpoint { 698 remote-endpoint = <&panel_in_edp>; 699 }; 700 }; 701 }; 702 }; 703}; 704 705ap_pen_1v8: &i2c11 { 706 status = "okay"; 707 clock-frequency = <400000>; 708 709 digitizer@9 { 710 compatible = "wacom,w9013", "hid-over-i2c"; 711 reg = <0x9>; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; 714 715 vdd-supply = <&pp3300_dx_pen>; 716 vddl-supply = <&pp1800_dx_pen>; 717 post-power-on-delay-ms = <100>; 718 719 interrupt-parent = <&tlmm>; 720 interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 721 722 hid-descr-addr = <0x1>; 723 }; 724}; 725 726amp_i2c: &i2c12 { 727 status = "okay"; 728 clock-frequency = <400000>; 729}; 730 731ap_ts_i2c: &i2c14 { 732 status = "okay"; 733 clock-frequency = <400000>; 734 735 touchscreen@10 { 736 compatible = "elan,ekth3500"; 737 reg = <0x10>; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&ts_int_l &ts_reset_l>; 740 741 interrupt-parent = <&tlmm>; 742 interrupts = <125 IRQ_TYPE_LEVEL_LOW>; 743 744 vcc33-supply = <&src_pp3300_l28a>; 745 746 reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 747 }; 748}; 749 750&gmu { 751 status = "okay"; 752}; 753 754&gpu { 755 status = "okay"; 756}; 757 758&ipa { 759 status = "okay"; 760 modem-init; 761}; 762 763&lpasscc { 764 status = "okay"; 765}; 766 767&mdss { 768 status = "okay"; 769}; 770 771/* 772 * Cheza fw does not properly program the GPU aperture to allow the 773 * GPU to update the SMMU pagetables for context switches. Work 774 * around this by dropping the "qcom,adreno-smmu" compat string. 775 */ 776&adreno_smmu { 777 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 778}; 779 780&mss_pil { 781 status = "okay"; 782 783 iommus = <&apps_smmu 0x781 0x0>, 784 <&apps_smmu 0x724 0x3>; 785}; 786 787&pm8998_pwrkey { 788 status = "disabled"; 789}; 790 791&qupv3_id_0 { 792 status = "okay"; 793 iommus = <&apps_smmu 0x0 0x3>; 794}; 795 796&qupv3_id_1 { 797 status = "okay"; 798 iommus = <&apps_smmu 0x6c0 0x3>; 799}; 800 801&sdhc_2 { 802 status = "okay"; 803 804 pinctrl-names = "default"; 805 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; 806 807 vmmc-supply = <&src_pp2950_l21a>; 808 vqmmc-supply = <&vddpx_2>; 809 810 cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; 811}; 812 813&spi0 { 814 status = "okay"; 815}; 816 817&spi5 { 818 status = "okay"; 819 820 tpm@0 { 821 compatible = "google,cr50"; 822 reg = <0>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&h1_ap_int_odl>; 825 spi-max-frequency = <800000>; 826 interrupt-parent = <&tlmm>; 827 interrupts = <129 IRQ_TYPE_EDGE_RISING>; 828 }; 829}; 830 831&spi10 { 832 status = "okay"; 833 834 cros_ec: ec@0 { 835 compatible = "google,cros-ec-spi"; 836 reg = <0>; 837 interrupt-parent = <&tlmm>; 838 interrupts = <122 IRQ_TYPE_LEVEL_LOW>; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&ec_ap_int_l>; 841 spi-max-frequency = <3000000>; 842 843 cros_ec_pwm: pwm { 844 compatible = "google,cros-ec-pwm"; 845 #pwm-cells = <1>; 846 }; 847 848 i2c_tunnel: i2c-tunnel { 849 compatible = "google,cros-ec-i2c-tunnel"; 850 google,remote-bus = <0>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 }; 854 }; 855}; 856 857#include <arm/cros-ec-keyboard.dtsi> 858#include <arm/cros-ec-sbs.dtsi> 859 860&uart6 { 861 status = "okay"; 862 863 bluetooth: wcn3990-bt { 864 compatible = "qcom,wcn3990-bt"; 865 vddio-supply = <&src_pp1800_s4a>; 866 vddxo-supply = <&pp1800_l7a_wcn3990>; 867 vddrf-supply = <&src_pp1300_l17a>; 868 vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; 869 max-speed = <3200000>; 870 }; 871}; 872 873&uart9 { 874 status = "okay"; 875}; 876 877&ufs_mem_hc { 878 status = "okay"; 879 880 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 881 882 vcc-supply = <&src_pp2950_l20a>; 883 vcc-max-microamp = <600000>; 884}; 885 886&ufs_mem_phy { 887 status = "okay"; 888 889 vdda-phy-supply = <&vdda_ufs1_core>; 890 vdda-pll-supply = <&vdda_ufs1_1p2>; 891}; 892 893&usb_1 { 894 status = "okay"; 895 896 /* We'll use this as USB 2.0 only */ 897 qcom,select-utmi-as-pipe-clk; 898}; 899 900&usb_1_dwc3 { 901 /* 902 * The hardware design intends this port to be hooked up in peripheral 903 * mode, so we'll hardcode it here. Some details: 904 * - SDM845 expects only a single Type C connector so it has only one 905 * native Type C port but cheza has two Type C connectors. 906 * - The only source of DP is the single native Type C port. 907 * - On cheza we want to be able to hook DP up to _either_ of the 908 * two Type C connectors and want to be able to achieve 4 lanes of DP. 909 * - When you configure a Type C port for 4 lanes of DP you lose USB3. 910 * - In order to make everything work, the native Type C port is always 911 * configured as 4-lanes DP so it's always available. 912 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then 913 * sent to the two Type C connectors. 914 * - The extra USB2 lines from the native Type C port are always 915 * setup as "peripheral" so that we can mux them over to one connector 916 * or the other if someone needs the connector configured as a gadget 917 * (but they only get USB2 speeds). 918 * 919 * All the hardware muxes would allow us to hook things up in different 920 * ways to some potential benefit for static configurations (you could 921 * achieve extra USB2 bandwidth by using two different ports for the 922 * two connectors or possibly even get USB3 peripheral mode), but in 923 * each case you end up forcing to disconnect/reconnect an in-use 924 * USB session in some cases depending on what you hotplug into the 925 * other connector. Thus hardcoding this as peripheral makes sense. 926 */ 927 dr_mode = "peripheral"; 928 929 /* 930 * We always need the high speed pins as 4-lanes DP in case someone 931 * hotplugs a DP peripheral. Thus limit this port to a max of high 932 * speed. 933 */ 934 maximum-speed = "high-speed"; 935 936 /* 937 * We don't need the usb3-phy since we run in highspeed mode always, so 938 * re-define these properties removing the superspeed USB PHY reference. 939 */ 940 phys = <&usb_1_hsphy>; 941 phy-names = "usb2-phy"; 942}; 943 944&usb_1_hsphy { 945 status = "okay"; 946 947 vdd-supply = <&vdda_usb1_ss_core>; 948 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 949 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 950 951 qcom,imp-res-offset-value = <8>; 952 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 953 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 954 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 955}; 956 957&usb_2 { 958 status = "okay"; 959}; 960 961&usb_2_dwc3 { 962 /* We have this hooked up to a hub and we always use in host mode */ 963 dr_mode = "host"; 964}; 965 966&usb_2_hsphy { 967 status = "okay"; 968 969 vdd-supply = <&vdda_usb2_ss_core>; 970 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 971 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 972 973 qcom,imp-res-offset-value = <8>; 974 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; 975}; 976 977&usb_2_qmpphy { 978 status = "okay"; 979 980 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 981 vdda-pll-supply = <&vdda_usb2_ss_core>; 982}; 983 984&wifi { 985 status = "okay"; 986 987 vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; 988 vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; 989 vdd-1.3-rfa-supply = <&src_pp1300_l17a>; 990 vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; 991}; 992 993/* PINCTRL - additions to nodes defined in sdm845.dtsi */ 994 995&qspi_cs0 { 996 pinconf { 997 pins = "gpio90"; 998 bias-disable; 999 }; 1000}; 1001 1002&qspi_clk { 1003 pinconf { 1004 pins = "gpio95"; 1005 bias-disable; 1006 }; 1007}; 1008 1009&qspi_data01 { 1010 pinconf { 1011 pins = "gpio91", "gpio92"; 1012 1013 /* High-Z when no transfers; nice to park the lines */ 1014 bias-pull-up; 1015 }; 1016}; 1017 1018&qup_i2c3_default { 1019 pinconf { 1020 pins = "gpio41", "gpio42"; 1021 drive-strength = <2>; 1022 1023 /* Has external pullup */ 1024 bias-disable; 1025 }; 1026}; 1027 1028&qup_i2c11_default { 1029 pinconf { 1030 pins = "gpio31", "gpio32"; 1031 drive-strength = <2>; 1032 1033 /* Has external pullup */ 1034 bias-disable; 1035 }; 1036}; 1037 1038&qup_i2c12_default { 1039 pinconf { 1040 pins = "gpio49", "gpio50"; 1041 drive-strength = <2>; 1042 1043 /* Has external pullup */ 1044 bias-disable; 1045 }; 1046}; 1047 1048&qup_i2c14_default { 1049 pinconf { 1050 pins = "gpio33", "gpio34"; 1051 drive-strength = <2>; 1052 1053 /* Has external pullup */ 1054 bias-disable; 1055 }; 1056}; 1057 1058&qup_spi0_default { 1059 pinconf { 1060 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1061 drive-strength = <2>; 1062 bias-disable; 1063 }; 1064}; 1065 1066&qup_spi5_default { 1067 pinconf { 1068 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1069 drive-strength = <2>; 1070 bias-disable; 1071 }; 1072}; 1073 1074&qup_spi10_default { 1075 pinconf { 1076 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1077 drive-strength = <2>; 1078 bias-disable; 1079 }; 1080}; 1081 1082&qup_uart6_default { 1083 /* Change pinmux to all 4 pins since CTS and RTS are connected */ 1084 pinmux { 1085 pins = "gpio45", "gpio46", 1086 "gpio47", "gpio48"; 1087 }; 1088 1089 pinconf-cts { 1090 /* 1091 * Configure a pull-down on 45 (CTS) to match the pull of 1092 * the Bluetooth module. 1093 */ 1094 pins = "gpio45"; 1095 bias-pull-down; 1096 }; 1097 1098 pinconf-rts-tx { 1099 /* We'll drive 46 (RTS) and 47 (TX), so no pull */ 1100 pins = "gpio46", "gpio47"; 1101 drive-strength = <2>; 1102 bias-disable; 1103 }; 1104 1105 pinconf-rx { 1106 /* 1107 * Configure a pull-up on 48 (RX). This is needed to avoid 1108 * garbage data when the TX pin of the Bluetooth module is 1109 * in tri-state (module powered off or not driving the 1110 * signal yet). 1111 */ 1112 pins = "gpio48"; 1113 bias-pull-up; 1114 }; 1115}; 1116 1117&qup_uart9_default { 1118 pinconf-tx { 1119 pins = "gpio4"; 1120 drive-strength = <2>; 1121 bias-disable; 1122 }; 1123 1124 pinconf-rx { 1125 pins = "gpio5"; 1126 drive-strength = <2>; 1127 bias-pull-up; 1128 }; 1129}; 1130 1131/* PINCTRL - board-specific pinctrl */ 1132&pm8005_gpio { 1133 gpio-line-names = "", 1134 "", 1135 "SLB", 1136 ""; 1137}; 1138 1139&pm8998_adc { 1140 adc-chan@4d { 1141 reg = <ADC5_AMUX_THM1_100K_PU>; 1142 label = "sdm_temp"; 1143 }; 1144 1145 adc-chan@4e { 1146 reg = <ADC5_AMUX_THM2_100K_PU>; 1147 label = "quiet_temp"; 1148 }; 1149 1150 adc-chan@4f { 1151 reg = <ADC5_AMUX_THM3_100K_PU>; 1152 label = "lte_temp_1"; 1153 }; 1154 1155 adc-chan@50 { 1156 reg = <ADC5_AMUX_THM4_100K_PU>; 1157 label = "lte_temp_2"; 1158 }; 1159 1160 adc-chan@51 { 1161 reg = <ADC5_AMUX_THM5_100K_PU>; 1162 label = "charger_temp"; 1163 }; 1164}; 1165 1166&pm8998_gpio { 1167 gpio-line-names = "", 1168 "", 1169 "SW_CTRL", 1170 "", 1171 "", 1172 "", 1173 "", 1174 "", 1175 "", 1176 "", 1177 "", 1178 "", 1179 "", 1180 "", 1181 "", 1182 "", 1183 "", 1184 "", 1185 "", 1186 "", 1187 "", 1188 "CFG_OPT1", 1189 "WCSS_PWR_REQ", 1190 "", 1191 "CFG_OPT2", 1192 "SLB"; 1193}; 1194 1195&tlmm { 1196 /* 1197 * pinctrl settings for pins that have no real owners. 1198 */ 1199 pinctrl-names = "default", "sleep"; 1200 pinctrl-0 = <&bios_flash_wp_r_l>, 1201 <&ap_suspend_l_deassert>; 1202 1203 pinctrl-1 = <&bios_flash_wp_r_l>, 1204 <&ap_suspend_l_assert>; 1205 1206 /* 1207 * Hogs prevent usermode from changing the value. A GPIO can be both 1208 * here and in the pinctrl section. 1209 */ 1210 ap-suspend-l-hog { 1211 gpio-hog; 1212 gpios = <126 GPIO_ACTIVE_LOW>; 1213 output-low; 1214 }; 1215 1216 ap_edp_bklten: ap-edp-bklten { 1217 pinmux { 1218 pins = "gpio37"; 1219 function = "gpio"; 1220 }; 1221 1222 pinconf { 1223 pins = "gpio37"; 1224 drive-strength = <2>; 1225 bias-disable; 1226 }; 1227 }; 1228 1229 bios_flash_wp_r_l: bios-flash-wp-r-l { 1230 pinmux { 1231 pins = "gpio128"; 1232 function = "gpio"; 1233 input-enable; 1234 }; 1235 1236 pinconf { 1237 pins = "gpio128"; 1238 bias-disable; 1239 }; 1240 }; 1241 1242 ec_ap_int_l: ec-ap-int-l { 1243 pinmux { 1244 pins = "gpio122"; 1245 function = "gpio"; 1246 input-enable; 1247 }; 1248 1249 pinconf { 1250 pins = "gpio122"; 1251 bias-pull-up; 1252 }; 1253 }; 1254 1255 edp_brij_en: edp-brij-en { 1256 pinmux { 1257 pins = "gpio102"; 1258 function = "gpio"; 1259 }; 1260 1261 pinconf { 1262 pins = "gpio102"; 1263 drive-strength = <2>; 1264 bias-disable; 1265 }; 1266 }; 1267 1268 edp_brij_irq: edp-brij-irq { 1269 pinmux { 1270 pins = "gpio10"; 1271 function = "gpio"; 1272 }; 1273 1274 pinconf { 1275 pins = "gpio10"; 1276 drive-strength = <2>; 1277 bias-pull-down; 1278 }; 1279 }; 1280 1281 en_pp3300_dx_edp: en-pp3300-dx-edp { 1282 pinmux { 1283 pins = "gpio43"; 1284 function = "gpio"; 1285 }; 1286 1287 pinconf { 1288 pins = "gpio43"; 1289 drive-strength = <2>; 1290 bias-disable; 1291 }; 1292 }; 1293 1294 h1_ap_int_odl: h1-ap-int-odl { 1295 pinmux { 1296 pins = "gpio129"; 1297 function = "gpio"; 1298 input-enable; 1299 }; 1300 1301 pinconf { 1302 pins = "gpio129"; 1303 bias-pull-up; 1304 }; 1305 }; 1306 1307 pen_eject_odl: pen-eject-odl { 1308 pinmux { 1309 pins = "gpio119"; 1310 function = "gpio"; 1311 bias-pull-up; 1312 }; 1313 }; 1314 1315 pen_irq_l: pen-irq-l { 1316 pinmux { 1317 pins = "gpio24"; 1318 function = "gpio"; 1319 }; 1320 1321 pinconf { 1322 pins = "gpio24"; 1323 1324 /* Has external pullup */ 1325 bias-disable; 1326 }; 1327 }; 1328 1329 pen_pdct_l: pen-pdct-l { 1330 pinmux { 1331 pins = "gpio63"; 1332 function = "gpio"; 1333 }; 1334 1335 pinconf { 1336 pins = "gpio63"; 1337 1338 /* Has external pullup */ 1339 bias-disable; 1340 }; 1341 }; 1342 1343 pen_rst_l: pen-rst-l { 1344 pinmux { 1345 pins = "gpio23"; 1346 function = "gpio"; 1347 }; 1348 1349 pinconf { 1350 pins = "gpio23"; 1351 bias-disable; 1352 drive-strength = <2>; 1353 1354 /* 1355 * The pen driver doesn't currently support 1356 * driving this reset line. By specifying 1357 * output-high here we're relying on the fact 1358 * that this pin has a default pulldown at boot 1359 * (which makes sure the pen was in reset if it 1360 * was powered) and then we set it high here to 1361 * take it out of reset. Better would be if the 1362 * pen driver could control this and we could 1363 * remove "output-high" here. 1364 */ 1365 output-high; 1366 }; 1367 }; 1368 1369 sdc2_clk: sdc2-clk { 1370 pinconf { 1371 pins = "sdc2_clk"; 1372 bias-disable; 1373 1374 /* 1375 * It seems that mmc_test reports errors if drive 1376 * strength is not 16. 1377 */ 1378 drive-strength = <16>; 1379 }; 1380 }; 1381 1382 sdc2_cmd: sdc2-cmd { 1383 pinconf { 1384 pins = "sdc2_cmd"; 1385 bias-pull-up; 1386 drive-strength = <16>; 1387 }; 1388 }; 1389 1390 sdc2_data: sdc2-data { 1391 pinconf { 1392 pins = "sdc2_data"; 1393 bias-pull-up; 1394 drive-strength = <16>; 1395 }; 1396 }; 1397 1398 sd_cd_odl: sd-cd-odl { 1399 pinmux { 1400 pins = "gpio44"; 1401 function = "gpio"; 1402 }; 1403 1404 pinconf { 1405 pins = "gpio44"; 1406 bias-pull-up; 1407 }; 1408 }; 1409 1410 ts_int_l: ts-int-l { 1411 pinmux { 1412 pins = "gpio125"; 1413 function = "gpio"; 1414 }; 1415 1416 pinconf { 1417 pins = "gpio125"; 1418 bias-pull-up; 1419 }; 1420 }; 1421 1422 ts_reset_l: ts-reset-l { 1423 pinmux { 1424 pins = "gpio118"; 1425 function = "gpio"; 1426 }; 1427 1428 pinconf { 1429 pins = "gpio118"; 1430 bias-disable; 1431 drive-strength = <2>; 1432 }; 1433 }; 1434 1435 ap_suspend_l_assert: ap_suspend_l_assert { 1436 config { 1437 pins = "gpio126"; 1438 function = "gpio"; 1439 bias-no-pull; 1440 drive-strength = <2>; 1441 output-low; 1442 }; 1443 }; 1444 1445 ap_suspend_l_deassert: ap_suspend_l_deassert { 1446 config { 1447 pins = "gpio126"; 1448 function = "gpio"; 1449 bias-no-pull; 1450 drive-strength = <2>; 1451 output-high; 1452 }; 1453 }; 1454}; 1455 1456&venus { 1457 status = "okay"; 1458 1459 video-firmware { 1460 iommus = <&apps_smmu 0x10b2 0x0>; 1461 }; 1462}; 1463