1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/phy/phy-qcom-qmp.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/interconnect/qcom,sm8450.h> 17#include <dt-bindings/soc/qcom,gpr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <76800000>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32000>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 CPU0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo780"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 next-level-cache = <&L2_0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 #cooling-cells = <2>; 58 clocks = <&cpufreq_hw 0>; 59 L2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 cache-unified; 68 }; 69 }; 70 }; 71 72 CPU1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "qcom,kryo780"; 75 reg = <0x0 0x100>; 76 enable-method = "psci"; 77 next-level-cache = <&L2_100>; 78 power-domains = <&CPU_PD1>; 79 power-domain-names = "psci"; 80 qcom,freq-domain = <&cpufreq_hw 0>; 81 #cooling-cells = <2>; 82 clocks = <&cpufreq_hw 0>; 83 L2_100: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 next-level-cache = <&L3_0>; 88 }; 89 }; 90 91 CPU2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo780"; 94 reg = <0x0 0x200>; 95 enable-method = "psci"; 96 next-level-cache = <&L2_200>; 97 power-domains = <&CPU_PD2>; 98 power-domain-names = "psci"; 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 #cooling-cells = <2>; 101 clocks = <&cpufreq_hw 0>; 102 L2_200: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-unified; 106 next-level-cache = <&L3_0>; 107 }; 108 }; 109 110 CPU3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo780"; 113 reg = <0x0 0x300>; 114 enable-method = "psci"; 115 next-level-cache = <&L2_300>; 116 power-domains = <&CPU_PD3>; 117 power-domain-names = "psci"; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 #cooling-cells = <2>; 120 clocks = <&cpufreq_hw 0>; 121 L2_300: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 cache-unified; 125 next-level-cache = <&L3_0>; 126 }; 127 }; 128 129 CPU4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo780"; 132 reg = <0x0 0x400>; 133 enable-method = "psci"; 134 next-level-cache = <&L2_400>; 135 power-domains = <&CPU_PD4>; 136 power-domain-names = "psci"; 137 qcom,freq-domain = <&cpufreq_hw 1>; 138 #cooling-cells = <2>; 139 clocks = <&cpufreq_hw 1>; 140 L2_400: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo780"; 151 reg = <0x0 0x500>; 152 enable-method = "psci"; 153 next-level-cache = <&L2_500>; 154 power-domains = <&CPU_PD5>; 155 power-domain-names = "psci"; 156 qcom,freq-domain = <&cpufreq_hw 1>; 157 #cooling-cells = <2>; 158 clocks = <&cpufreq_hw 1>; 159 L2_500: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 next-level-cache = <&L3_0>; 164 }; 165 }; 166 167 CPU6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo780"; 170 reg = <0x0 0x600>; 171 enable-method = "psci"; 172 next-level-cache = <&L2_600>; 173 power-domains = <&CPU_PD6>; 174 power-domain-names = "psci"; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 #cooling-cells = <2>; 177 clocks = <&cpufreq_hw 1>; 178 L2_600: l2-cache { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-unified; 182 next-level-cache = <&L3_0>; 183 }; 184 }; 185 186 CPU7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "qcom,kryo780"; 189 reg = <0x0 0x700>; 190 enable-method = "psci"; 191 next-level-cache = <&L2_700>; 192 power-domains = <&CPU_PD7>; 193 power-domain-names = "psci"; 194 qcom,freq-domain = <&cpufreq_hw 2>; 195 #cooling-cells = <2>; 196 clocks = <&cpufreq_hw 2>; 197 L2_700: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&CPU0>; 209 }; 210 211 core1 { 212 cpu = <&CPU1>; 213 }; 214 215 core2 { 216 cpu = <&CPU2>; 217 }; 218 219 core3 { 220 cpu = <&CPU3>; 221 }; 222 223 core4 { 224 cpu = <&CPU4>; 225 }; 226 227 core5 { 228 cpu = <&CPU5>; 229 }; 230 231 core6 { 232 cpu = <&CPU6>; 233 }; 234 235 core7 { 236 cpu = <&CPU7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 245 compatible = "arm,idle-state"; 246 idle-state-name = "silver-rail-power-collapse"; 247 arm,psci-suspend-param = <0x40000004>; 248 entry-latency-us = <800>; 249 exit-latency-us = <750>; 250 min-residency-us = <4090>; 251 local-timer-stop; 252 }; 253 254 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 255 compatible = "arm,idle-state"; 256 idle-state-name = "gold-rail-power-collapse"; 257 arm,psci-suspend-param = <0x40000004>; 258 entry-latency-us = <600>; 259 exit-latency-us = <1550>; 260 min-residency-us = <4791>; 261 local-timer-stop; 262 }; 263 }; 264 265 domain-idle-states { 266 CLUSTER_SLEEP_0: cluster-sleep-0 { 267 compatible = "domain-idle-state"; 268 arm,psci-suspend-param = <0x41000044>; 269 entry-latency-us = <1050>; 270 exit-latency-us = <2500>; 271 min-residency-us = <5309>; 272 }; 273 274 CLUSTER_SLEEP_1: cluster-sleep-1 { 275 compatible = "domain-idle-state"; 276 arm,psci-suspend-param = <0x4100c344>; 277 entry-latency-us = <2700>; 278 exit-latency-us = <3500>; 279 min-residency-us = <13959>; 280 }; 281 }; 282 }; 283 284 firmware { 285 scm: scm { 286 compatible = "qcom,scm-sm8450", "qcom,scm"; 287 qcom,dload-mode = <&tcsr 0x13000>; 288 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 289 #reset-cells = <1>; 290 }; 291 }; 292 293 clk_virt: interconnect-0 { 294 compatible = "qcom,sm8450-clk-virt"; 295 #interconnect-cells = <2>; 296 qcom,bcm-voters = <&apps_bcm_voter>; 297 }; 298 299 mc_virt: interconnect-1 { 300 compatible = "qcom,sm8450-mc-virt"; 301 #interconnect-cells = <2>; 302 qcom,bcm-voters = <&apps_bcm_voter>; 303 }; 304 305 memory@a0000000 { 306 device_type = "memory"; 307 /* We expect the bootloader to fill in the size */ 308 reg = <0x0 0xa0000000 0x0 0x0>; 309 }; 310 311 pmu { 312 compatible = "arm,armv8-pmuv3"; 313 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 316 psci { 317 compatible = "arm,psci-1.0"; 318 method = "smc"; 319 320 CPU_PD0: power-domain-cpu0 { 321 #power-domain-cells = <0>; 322 power-domains = <&CLUSTER_PD>; 323 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 324 }; 325 326 CPU_PD1: power-domain-cpu1 { 327 #power-domain-cells = <0>; 328 power-domains = <&CLUSTER_PD>; 329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 330 }; 331 332 CPU_PD2: power-domain-cpu2 { 333 #power-domain-cells = <0>; 334 power-domains = <&CLUSTER_PD>; 335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 336 }; 337 338 CPU_PD3: power-domain-cpu3 { 339 #power-domain-cells = <0>; 340 power-domains = <&CLUSTER_PD>; 341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 342 }; 343 344 CPU_PD4: power-domain-cpu4 { 345 #power-domain-cells = <0>; 346 power-domains = <&CLUSTER_PD>; 347 domain-idle-states = <&BIG_CPU_SLEEP_0>; 348 }; 349 350 CPU_PD5: power-domain-cpu5 { 351 #power-domain-cells = <0>; 352 power-domains = <&CLUSTER_PD>; 353 domain-idle-states = <&BIG_CPU_SLEEP_0>; 354 }; 355 356 CPU_PD6: power-domain-cpu6 { 357 #power-domain-cells = <0>; 358 power-domains = <&CLUSTER_PD>; 359 domain-idle-states = <&BIG_CPU_SLEEP_0>; 360 }; 361 362 CPU_PD7: power-domain-cpu7 { 363 #power-domain-cells = <0>; 364 power-domains = <&CLUSTER_PD>; 365 domain-idle-states = <&BIG_CPU_SLEEP_0>; 366 }; 367 368 CLUSTER_PD: power-domain-cpu-cluster0 { 369 #power-domain-cells = <0>; 370 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 371 }; 372 }; 373 374 qup_opp_table_100mhz: opp-table-qup { 375 compatible = "operating-points-v2"; 376 377 opp-50000000 { 378 opp-hz = /bits/ 64 <50000000>; 379 required-opps = <&rpmhpd_opp_min_svs>; 380 }; 381 382 opp-75000000 { 383 opp-hz = /bits/ 64 <75000000>; 384 required-opps = <&rpmhpd_opp_low_svs>; 385 }; 386 387 opp-100000000 { 388 opp-hz = /bits/ 64 <100000000>; 389 required-opps = <&rpmhpd_opp_svs>; 390 }; 391 }; 392 393 reserved_memory: reserved-memory { 394 #address-cells = <2>; 395 #size-cells = <2>; 396 ranges; 397 398 hyp_mem: memory@80000000 { 399 reg = <0x0 0x80000000 0x0 0x600000>; 400 no-map; 401 }; 402 403 xbl_dt_log_mem: memory@80600000 { 404 reg = <0x0 0x80600000 0x0 0x40000>; 405 no-map; 406 }; 407 408 xbl_ramdump_mem: memory@80640000 { 409 reg = <0x0 0x80640000 0x0 0x180000>; 410 no-map; 411 }; 412 413 xbl_sc_mem: memory@807c0000 { 414 reg = <0x0 0x807c0000 0x0 0x40000>; 415 no-map; 416 }; 417 418 aop_image_mem: memory@80800000 { 419 reg = <0x0 0x80800000 0x0 0x60000>; 420 no-map; 421 }; 422 423 aop_cmd_db_mem: memory@80860000 { 424 compatible = "qcom,cmd-db"; 425 reg = <0x0 0x80860000 0x0 0x20000>; 426 no-map; 427 }; 428 429 aop_config_mem: memory@80880000 { 430 reg = <0x0 0x80880000 0x0 0x20000>; 431 no-map; 432 }; 433 434 tme_crash_dump_mem: memory@808a0000 { 435 reg = <0x0 0x808a0000 0x0 0x40000>; 436 no-map; 437 }; 438 439 tme_log_mem: memory@808e0000 { 440 reg = <0x0 0x808e0000 0x0 0x4000>; 441 no-map; 442 }; 443 444 uefi_log_mem: memory@808e4000 { 445 reg = <0x0 0x808e4000 0x0 0x10000>; 446 no-map; 447 }; 448 449 /* secdata region can be reused by apps */ 450 smem: memory@80900000 { 451 compatible = "qcom,smem"; 452 reg = <0x0 0x80900000 0x0 0x200000>; 453 hwlocks = <&tcsr_mutex 3>; 454 no-map; 455 }; 456 457 cpucp_fw_mem: memory@80b00000 { 458 reg = <0x0 0x80b00000 0x0 0x100000>; 459 no-map; 460 }; 461 462 cdsp_secure_heap: memory@80c00000 { 463 reg = <0x0 0x80c00000 0x0 0x4600000>; 464 no-map; 465 }; 466 467 video_mem: memory@85700000 { 468 reg = <0x0 0x85700000 0x0 0x700000>; 469 no-map; 470 }; 471 472 adsp_mem: memory@85e00000 { 473 reg = <0x0 0x85e00000 0x0 0x2100000>; 474 no-map; 475 }; 476 477 slpi_mem: memory@88000000 { 478 reg = <0x0 0x88000000 0x0 0x1900000>; 479 no-map; 480 }; 481 482 cdsp_mem: memory@89900000 { 483 reg = <0x0 0x89900000 0x0 0x2000000>; 484 no-map; 485 }; 486 487 ipa_fw_mem: memory@8b900000 { 488 reg = <0x0 0x8b900000 0x0 0x10000>; 489 no-map; 490 }; 491 492 ipa_gsi_mem: memory@8b910000 { 493 reg = <0x0 0x8b910000 0x0 0xa000>; 494 no-map; 495 }; 496 497 gpu_micro_code_mem: memory@8b91a000 { 498 reg = <0x0 0x8b91a000 0x0 0x2000>; 499 no-map; 500 }; 501 502 spss_region_mem: memory@8ba00000 { 503 reg = <0x0 0x8ba00000 0x0 0x180000>; 504 no-map; 505 }; 506 507 /* First part of the "SPU secure shared memory" region */ 508 spu_tz_shared_mem: memory@8bb80000 { 509 reg = <0x0 0x8bb80000 0x0 0x60000>; 510 no-map; 511 }; 512 513 /* Second part of the "SPU secure shared memory" region */ 514 spu_modem_shared_mem: memory@8bbe0000 { 515 reg = <0x0 0x8bbe0000 0x0 0x20000>; 516 no-map; 517 }; 518 519 mpss_mem: memory@8bc00000 { 520 reg = <0x0 0x8bc00000 0x0 0x13200000>; 521 no-map; 522 }; 523 524 cvp_mem: memory@9ee00000 { 525 reg = <0x0 0x9ee00000 0x0 0x700000>; 526 no-map; 527 }; 528 529 camera_mem: memory@9f500000 { 530 reg = <0x0 0x9f500000 0x0 0x800000>; 531 no-map; 532 }; 533 534 rmtfs_mem: memory@9fd00000 { 535 compatible = "qcom,rmtfs-mem"; 536 reg = <0x0 0x9fd00000 0x0 0x280000>; 537 no-map; 538 539 qcom,client-id = <1>; 540 qcom,vmid = <15>; 541 }; 542 543 xbl_sc_mem2: memory@a6e00000 { 544 reg = <0x0 0xa6e00000 0x0 0x40000>; 545 no-map; 546 }; 547 548 global_sync_mem: memory@a6f00000 { 549 reg = <0x0 0xa6f00000 0x0 0x100000>; 550 no-map; 551 }; 552 553 /* uefi region can be reused by APPS */ 554 555 /* Linux kernel image is loaded at 0xa0000000 */ 556 557 oem_vm_mem: memory@bb000000 { 558 reg = <0x0 0xbb000000 0x0 0x5000000>; 559 no-map; 560 }; 561 562 mte_mem: memory@c0000000 { 563 reg = <0x0 0xc0000000 0x0 0x20000000>; 564 no-map; 565 }; 566 567 qheebsp_reserved_mem: memory@e0000000 { 568 reg = <0x0 0xe0000000 0x0 0x600000>; 569 no-map; 570 }; 571 572 cpusys_vm_mem: memory@e0600000 { 573 reg = <0x0 0xe0600000 0x0 0x400000>; 574 no-map; 575 }; 576 577 hyp_reserved_mem: memory@e0a00000 { 578 reg = <0x0 0xe0a00000 0x0 0x100000>; 579 no-map; 580 }; 581 582 trust_ui_vm_mem: memory@e0b00000 { 583 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 584 no-map; 585 }; 586 587 trust_ui_vm_qrtr: memory@e55f3000 { 588 reg = <0x0 0xe55f3000 0x0 0x9000>; 589 no-map; 590 }; 591 592 trust_ui_vm_vblk0_ring: memory@e55fc000 { 593 reg = <0x0 0xe55fc000 0x0 0x4000>; 594 no-map; 595 }; 596 597 trust_ui_vm_swiotlb: memory@e5600000 { 598 reg = <0x0 0xe5600000 0x0 0x100000>; 599 no-map; 600 }; 601 602 tz_stat_mem: memory@e8800000 { 603 reg = <0x0 0xe8800000 0x0 0x100000>; 604 no-map; 605 }; 606 607 tags_mem: memory@e8900000 { 608 reg = <0x0 0xe8900000 0x0 0x1200000>; 609 no-map; 610 }; 611 612 qtee_mem: memory@e9b00000 { 613 reg = <0x0 0xe9b00000 0x0 0x500000>; 614 no-map; 615 }; 616 617 trusted_apps_mem: memory@ea000000 { 618 reg = <0x0 0xea000000 0x0 0x3900000>; 619 no-map; 620 }; 621 622 trusted_apps_ext_mem: memory@ed900000 { 623 reg = <0x0 0xed900000 0x0 0x3b00000>; 624 no-map; 625 }; 626 }; 627 628 smp2p-adsp { 629 compatible = "qcom,smp2p"; 630 qcom,smem = <443>, <429>; 631 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 632 IPCC_MPROC_SIGNAL_SMP2P 633 IRQ_TYPE_EDGE_RISING>; 634 mboxes = <&ipcc IPCC_CLIENT_LPASS 635 IPCC_MPROC_SIGNAL_SMP2P>; 636 637 qcom,local-pid = <0>; 638 qcom,remote-pid = <2>; 639 640 smp2p_adsp_out: master-kernel { 641 qcom,entry-name = "master-kernel"; 642 #qcom,smem-state-cells = <1>; 643 }; 644 645 smp2p_adsp_in: slave-kernel { 646 qcom,entry-name = "slave-kernel"; 647 interrupt-controller; 648 #interrupt-cells = <2>; 649 }; 650 }; 651 652 smp2p-cdsp { 653 compatible = "qcom,smp2p"; 654 qcom,smem = <94>, <432>; 655 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 656 IPCC_MPROC_SIGNAL_SMP2P 657 IRQ_TYPE_EDGE_RISING>; 658 mboxes = <&ipcc IPCC_CLIENT_CDSP 659 IPCC_MPROC_SIGNAL_SMP2P>; 660 661 qcom,local-pid = <0>; 662 qcom,remote-pid = <5>; 663 664 smp2p_cdsp_out: master-kernel { 665 qcom,entry-name = "master-kernel"; 666 #qcom,smem-state-cells = <1>; 667 }; 668 669 smp2p_cdsp_in: slave-kernel { 670 qcom,entry-name = "slave-kernel"; 671 interrupt-controller; 672 #interrupt-cells = <2>; 673 }; 674 }; 675 676 smp2p-modem { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <435>, <428>; 679 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 680 IPCC_MPROC_SIGNAL_SMP2P 681 IRQ_TYPE_EDGE_RISING>; 682 mboxes = <&ipcc IPCC_CLIENT_MPSS 683 IPCC_MPROC_SIGNAL_SMP2P>; 684 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <1>; 687 688 smp2p_modem_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 smp2p_modem_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 699 ipa_smp2p_out: ipa-ap-to-modem { 700 qcom,entry-name = "ipa"; 701 #qcom,smem-state-cells = <1>; 702 }; 703 704 ipa_smp2p_in: ipa-modem-to-ap { 705 qcom,entry-name = "ipa"; 706 interrupt-controller; 707 #interrupt-cells = <2>; 708 }; 709 }; 710 711 smp2p-slpi { 712 compatible = "qcom,smp2p"; 713 qcom,smem = <481>, <430>; 714 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 715 IPCC_MPROC_SIGNAL_SMP2P 716 IRQ_TYPE_EDGE_RISING>; 717 mboxes = <&ipcc IPCC_CLIENT_SLPI 718 IPCC_MPROC_SIGNAL_SMP2P>; 719 720 qcom,local-pid = <0>; 721 qcom,remote-pid = <3>; 722 723 smp2p_slpi_out: master-kernel { 724 qcom,entry-name = "master-kernel"; 725 #qcom,smem-state-cells = <1>; 726 }; 727 728 smp2p_slpi_in: slave-kernel { 729 qcom,entry-name = "slave-kernel"; 730 interrupt-controller; 731 #interrupt-cells = <2>; 732 }; 733 }; 734 735 soc: soc@0 { 736 #address-cells = <2>; 737 #size-cells = <2>; 738 ranges = <0 0 0 0 0x10 0>; 739 dma-ranges = <0 0 0 0 0x10 0>; 740 compatible = "simple-bus"; 741 742 gcc: clock-controller@100000 { 743 compatible = "qcom,gcc-sm8450"; 744 reg = <0x0 0x00100000 0x0 0x1f4200>; 745 #clock-cells = <1>; 746 #reset-cells = <1>; 747 #power-domain-cells = <1>; 748 clocks = <&rpmhcc RPMH_CXO_CLK>, 749 <&sleep_clk>, 750 <&pcie0_lane>, 751 <&pcie1_lane>, 752 <0>, 753 <&ufs_mem_phy_lanes 0>, 754 <&ufs_mem_phy_lanes 1>, 755 <&ufs_mem_phy_lanes 2>, 756 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 757 clock-names = "bi_tcxo", 758 "sleep_clk", 759 "pcie_0_pipe_clk", 760 "pcie_1_pipe_clk", 761 "pcie_1_phy_aux_clk", 762 "ufs_phy_rx_symbol_0_clk", 763 "ufs_phy_rx_symbol_1_clk", 764 "ufs_phy_tx_symbol_0_clk", 765 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 766 }; 767 768 gpi_dma2: dma-controller@800000 { 769 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 770 #dma-cells = <3>; 771 reg = <0 0x00800000 0 0x60000>; 772 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 784 dma-channels = <12>; 785 dma-channel-mask = <0x7e>; 786 iommus = <&apps_smmu 0x496 0x0>; 787 status = "disabled"; 788 }; 789 790 qupv3_id_2: geniqup@8c0000 { 791 compatible = "qcom,geni-se-qup"; 792 reg = <0x0 0x008c0000 0x0 0x2000>; 793 clock-names = "m-ahb", "s-ahb"; 794 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 795 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 796 iommus = <&apps_smmu 0x483 0x0>; 797 #address-cells = <2>; 798 #size-cells = <2>; 799 ranges; 800 status = "disabled"; 801 802 i2c15: i2c@880000 { 803 compatible = "qcom,geni-i2c"; 804 reg = <0x0 0x00880000 0x0 0x4000>; 805 clock-names = "se"; 806 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 807 pinctrl-names = "default"; 808 pinctrl-0 = <&qup_i2c15_data_clk>; 809 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 813 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 814 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 815 interconnect-names = "qup-core", "qup-config", "qup-memory"; 816 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 817 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 818 dma-names = "tx", "rx"; 819 status = "disabled"; 820 }; 821 822 spi15: spi@880000 { 823 compatible = "qcom,geni-spi"; 824 reg = <0x0 0x00880000 0x0 0x4000>; 825 clock-names = "se"; 826 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 827 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 830 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 831 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 832 interconnect-names = "qup-core", "qup-config"; 833 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 834 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 835 dma-names = "tx", "rx"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 i2c16: i2c@884000 { 842 compatible = "qcom,geni-i2c"; 843 reg = <0x0 0x00884000 0x0 0x4000>; 844 clock-names = "se"; 845 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&qup_i2c16_data_clk>; 848 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 852 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 853 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 854 interconnect-names = "qup-core", "qup-config", "qup-memory"; 855 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 856 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 857 dma-names = "tx", "rx"; 858 status = "disabled"; 859 }; 860 861 spi16: spi@884000 { 862 compatible = "qcom,geni-spi"; 863 reg = <0x0 0x00884000 0x0 0x4000>; 864 clock-names = "se"; 865 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 866 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 869 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 870 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 871 interconnect-names = "qup-core", "qup-config"; 872 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 873 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 874 dma-names = "tx", "rx"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 status = "disabled"; 878 }; 879 880 i2c17: i2c@888000 { 881 compatible = "qcom,geni-i2c"; 882 reg = <0x0 0x00888000 0x0 0x4000>; 883 clock-names = "se"; 884 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&qup_i2c17_data_clk>; 887 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 891 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 892 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 893 interconnect-names = "qup-core", "qup-config", "qup-memory"; 894 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 895 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 896 dma-names = "tx", "rx"; 897 status = "disabled"; 898 }; 899 900 spi17: spi@888000 { 901 compatible = "qcom,geni-spi"; 902 reg = <0x0 0x00888000 0x0 0x4000>; 903 clock-names = "se"; 904 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 905 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 908 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 909 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 910 interconnect-names = "qup-core", "qup-config"; 911 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 912 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 913 dma-names = "tx", "rx"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 i2c18: i2c@88c000 { 920 compatible = "qcom,geni-i2c"; 921 reg = <0x0 0x0088c000 0x0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&qup_i2c18_data_clk>; 926 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 930 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 931 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 932 interconnect-names = "qup-core", "qup-config", "qup-memory"; 933 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 934 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 935 dma-names = "tx", "rx"; 936 status = "disabled"; 937 }; 938 939 spi18: spi@88c000 { 940 compatible = "qcom,geni-spi"; 941 reg = <0 0x0088c000 0 0x4000>; 942 clock-names = "se"; 943 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 944 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 948 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 949 interconnect-names = "qup-core", "qup-config"; 950 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 951 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 952 dma-names = "tx", "rx"; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 status = "disabled"; 956 }; 957 958 i2c19: i2c@890000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0x0 0x00890000 0x0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c19_data_clk>; 965 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 969 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 970 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 971 interconnect-names = "qup-core", "qup-config", "qup-memory"; 972 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 973 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 974 dma-names = "tx", "rx"; 975 status = "disabled"; 976 }; 977 978 spi19: spi@890000 { 979 compatible = "qcom,geni-spi"; 980 reg = <0 0x00890000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 983 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 987 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 988 interconnect-names = "qup-core", "qup-config"; 989 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 990 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 991 dma-names = "tx", "rx"; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 status = "disabled"; 995 }; 996 997 i2c20: i2c@894000 { 998 compatible = "qcom,geni-i2c"; 999 reg = <0x0 0x00894000 0x0 0x4000>; 1000 clock-names = "se"; 1001 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_i2c20_data_clk>; 1004 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1008 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1009 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1010 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1011 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1012 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1013 dma-names = "tx", "rx"; 1014 status = "disabled"; 1015 }; 1016 1017 uart20: serial@894000 { 1018 compatible = "qcom,geni-uart"; 1019 reg = <0 0x00894000 0 0x4000>; 1020 clock-names = "se"; 1021 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&qup_uart20_default>; 1024 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1025 status = "disabled"; 1026 }; 1027 1028 spi20: spi@894000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0 0x00894000 0 0x4000>; 1031 clock-names = "se"; 1032 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1033 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1036 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1037 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1038 interconnect-names = "qup-core", "qup-config"; 1039 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1040 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1041 dma-names = "tx", "rx"; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 i2c21: i2c@898000 { 1048 compatible = "qcom,geni-i2c"; 1049 reg = <0x0 0x00898000 0x0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_i2c21_data_clk>; 1054 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1058 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1059 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1060 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1061 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1062 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1063 dma-names = "tx", "rx"; 1064 status = "disabled"; 1065 }; 1066 1067 spi21: spi@898000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0 0x00898000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1072 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1075 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1076 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1077 interconnect-names = "qup-core", "qup-config"; 1078 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1079 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1080 dma-names = "tx", "rx"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 status = "disabled"; 1084 }; 1085 }; 1086 1087 gpi_dma0: dma-controller@900000 { 1088 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1089 #dma-cells = <3>; 1090 reg = <0 0x00900000 0 0x60000>; 1091 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1103 dma-channels = <12>; 1104 dma-channel-mask = <0x7e>; 1105 iommus = <&apps_smmu 0x5b6 0x0>; 1106 status = "disabled"; 1107 }; 1108 1109 qupv3_id_0: geniqup@9c0000 { 1110 compatible = "qcom,geni-se-qup"; 1111 reg = <0x0 0x009c0000 0x0 0x2000>; 1112 clock-names = "m-ahb", "s-ahb"; 1113 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1114 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1115 iommus = <&apps_smmu 0x5a3 0x0>; 1116 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1117 interconnect-names = "qup-core"; 1118 #address-cells = <2>; 1119 #size-cells = <2>; 1120 ranges; 1121 status = "disabled"; 1122 1123 i2c0: i2c@980000 { 1124 compatible = "qcom,geni-i2c"; 1125 reg = <0x0 0x00980000 0x0 0x4000>; 1126 clock-names = "se"; 1127 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1128 pinctrl-names = "default"; 1129 pinctrl-0 = <&qup_i2c0_data_clk>; 1130 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1134 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1135 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1136 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1137 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1138 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1139 dma-names = "tx", "rx"; 1140 status = "disabled"; 1141 }; 1142 1143 spi0: spi@980000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0x0 0x00980000 0x0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1148 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1151 power-domains = <&rpmhpd SM8450_CX>; 1152 operating-points-v2 = <&qup_opp_table_100mhz>; 1153 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1154 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1155 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1156 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1157 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1158 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1159 dma-names = "tx", "rx"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 i2c1: i2c@984000 { 1166 compatible = "qcom,geni-i2c"; 1167 reg = <0x0 0x00984000 0x0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&qup_i2c1_data_clk>; 1172 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1176 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1177 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1178 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1179 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1180 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1181 dma-names = "tx", "rx"; 1182 status = "disabled"; 1183 }; 1184 1185 spi1: spi@984000 { 1186 compatible = "qcom,geni-spi"; 1187 reg = <0x0 0x00984000 0x0 0x4000>; 1188 clock-names = "se"; 1189 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1190 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1191 pinctrl-names = "default"; 1192 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1194 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1195 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1196 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1197 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1198 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1199 dma-names = "tx", "rx"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 i2c2: i2c@988000 { 1206 compatible = "qcom,geni-i2c"; 1207 reg = <0x0 0x00988000 0x0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_i2c2_data_clk>; 1212 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1216 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1217 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1218 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1219 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1220 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1221 dma-names = "tx", "rx"; 1222 status = "disabled"; 1223 }; 1224 1225 spi2: spi@988000 { 1226 compatible = "qcom,geni-spi"; 1227 reg = <0x0 0x00988000 0x0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1230 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1233 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1234 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1235 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1236 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1237 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1238 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1239 dma-names = "tx", "rx"; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 1246 i2c3: i2c@98c000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0x0 0x0098c000 0x0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c3_data_clk>; 1253 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1257 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1258 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1259 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1260 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1261 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1262 dma-names = "tx", "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 spi3: spi@98c000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0x0 0x0098c000 0x0 0x4000>; 1269 clock-names = "se"; 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1271 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1275 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1276 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1277 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1278 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1279 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1280 dma-names = "tx", "rx"; 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 status = "disabled"; 1284 }; 1285 1286 i2c4: i2c@990000 { 1287 compatible = "qcom,geni-i2c"; 1288 reg = <0x0 0x00990000 0x0 0x4000>; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_i2c4_data_clk>; 1293 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1297 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1298 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1299 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1300 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1301 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1302 dma-names = "tx", "rx"; 1303 status = "disabled"; 1304 }; 1305 1306 spi4: spi@990000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0x0 0x00990000 0x0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1311 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1312 pinctrl-names = "default"; 1313 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1314 power-domains = <&rpmhpd SM8450_CX>; 1315 operating-points-v2 = <&qup_opp_table_100mhz>; 1316 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1317 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1318 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1319 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1320 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1321 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1322 dma-names = "tx", "rx"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 i2c5: i2c@994000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0x0 0x00994000 0x0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_i2c5_data_clk>; 1335 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1339 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1340 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1341 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1342 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1343 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1344 dma-names = "tx", "rx"; 1345 status = "disabled"; 1346 }; 1347 1348 spi5: spi@994000 { 1349 compatible = "qcom,geni-spi"; 1350 reg = <0x0 0x00994000 0x0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1353 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1356 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1357 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1358 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1359 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1360 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1361 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1362 dma-names = "tx", "rx"; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 status = "disabled"; 1366 }; 1367 1368 1369 i2c6: i2c@998000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0x0 0x00998000 0x0 0x4000>; 1372 clock-names = "se"; 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&qup_i2c6_data_clk>; 1376 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1380 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1381 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1382 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1383 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1384 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1385 dma-names = "tx", "rx"; 1386 status = "disabled"; 1387 }; 1388 1389 spi6: spi@998000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0x0 0x00998000 0x0 0x4000>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1394 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1395 pinctrl-names = "default"; 1396 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1397 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1398 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1399 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1400 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1401 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1402 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1403 dma-names = "tx", "rx"; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 status = "disabled"; 1407 }; 1408 1409 uart7: serial@99c000 { 1410 compatible = "qcom,geni-debug-uart"; 1411 reg = <0 0x0099c000 0 0x4000>; 1412 clock-names = "se"; 1413 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1416 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1417 status = "disabled"; 1418 }; 1419 }; 1420 1421 gpi_dma1: dma-controller@a00000 { 1422 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1423 #dma-cells = <3>; 1424 reg = <0 0x00a00000 0 0x60000>; 1425 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1437 dma-channels = <12>; 1438 dma-channel-mask = <0x7e>; 1439 iommus = <&apps_smmu 0x56 0x0>; 1440 status = "disabled"; 1441 }; 1442 1443 qupv3_id_1: geniqup@ac0000 { 1444 compatible = "qcom,geni-se-qup"; 1445 reg = <0x0 0x00ac0000 0x0 0x6000>; 1446 clock-names = "m-ahb", "s-ahb"; 1447 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1448 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1449 iommus = <&apps_smmu 0x43 0x0>; 1450 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1451 interconnect-names = "qup-core"; 1452 #address-cells = <2>; 1453 #size-cells = <2>; 1454 ranges; 1455 status = "disabled"; 1456 1457 i2c8: i2c@a80000 { 1458 compatible = "qcom,geni-i2c"; 1459 reg = <0x0 0x00a80000 0x0 0x4000>; 1460 clock-names = "se"; 1461 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_i2c8_data_clk>; 1464 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1468 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1469 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1470 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1471 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1472 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1473 dma-names = "tx", "rx"; 1474 status = "disabled"; 1475 }; 1476 1477 spi8: spi@a80000 { 1478 compatible = "qcom,geni-spi"; 1479 reg = <0x0 0x00a80000 0x0 0x4000>; 1480 clock-names = "se"; 1481 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1483 pinctrl-names = "default"; 1484 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1490 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1491 dma-names = "tx", "rx"; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 status = "disabled"; 1495 }; 1496 1497 i2c9: i2c@a84000 { 1498 compatible = "qcom,geni-i2c"; 1499 reg = <0x0 0x00a84000 0x0 0x4000>; 1500 clock-names = "se"; 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_i2c9_data_clk>; 1504 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1508 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1509 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1510 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1511 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1512 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1513 dma-names = "tx", "rx"; 1514 status = "disabled"; 1515 }; 1516 1517 spi9: spi@a84000 { 1518 compatible = "qcom,geni-spi"; 1519 reg = <0x0 0x00a84000 0x0 0x4000>; 1520 clock-names = "se"; 1521 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1523 pinctrl-names = "default"; 1524 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1528 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1530 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1531 dma-names = "tx", "rx"; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 i2c10: i2c@a88000 { 1538 compatible = "qcom,geni-i2c"; 1539 reg = <0x0 0x00a88000 0x0 0x4000>; 1540 clock-names = "se"; 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1542 pinctrl-names = "default"; 1543 pinctrl-0 = <&qup_i2c10_data_clk>; 1544 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1548 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1549 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1550 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1551 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1552 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1553 dma-names = "tx", "rx"; 1554 status = "disabled"; 1555 }; 1556 1557 spi10: spi@a88000 { 1558 compatible = "qcom,geni-spi"; 1559 reg = <0x0 0x00a88000 0x0 0x4000>; 1560 clock-names = "se"; 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1568 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1570 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1571 dma-names = "tx", "rx"; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 i2c11: i2c@a8c000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0x0 0x00a8c000 0x0 0x4000>; 1580 clock-names = "se"; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_i2c11_data_clk>; 1584 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1588 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1589 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1590 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1591 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1592 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1593 dma-names = "tx", "rx"; 1594 status = "disabled"; 1595 }; 1596 1597 spi11: spi@a8c000 { 1598 compatible = "qcom,geni-spi"; 1599 reg = <0x0 0x00a8c000 0x0 0x4000>; 1600 clock-names = "se"; 1601 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1603 pinctrl-names = "default"; 1604 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1608 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1610 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1611 dma-names = "tx", "rx"; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 status = "disabled"; 1615 }; 1616 1617 i2c12: i2c@a90000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0x0 0x00a90000 0x0 0x4000>; 1620 clock-names = "se"; 1621 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1622 pinctrl-names = "default"; 1623 pinctrl-0 = <&qup_i2c12_data_clk>; 1624 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1628 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1629 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1630 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1631 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1632 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1633 dma-names = "tx", "rx"; 1634 status = "disabled"; 1635 }; 1636 1637 spi12: spi@a90000 { 1638 compatible = "qcom,geni-spi"; 1639 reg = <0x0 0x00a90000 0x0 0x4000>; 1640 clock-names = "se"; 1641 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1643 pinctrl-names = "default"; 1644 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1648 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1650 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1651 dma-names = "tx", "rx"; 1652 #address-cells = <1>; 1653 #size-cells = <0>; 1654 status = "disabled"; 1655 }; 1656 1657 i2c13: i2c@a94000 { 1658 compatible = "qcom,geni-i2c"; 1659 reg = <0 0x00a94000 0 0x4000>; 1660 clock-names = "se"; 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1662 pinctrl-names = "default"; 1663 pinctrl-0 = <&qup_i2c13_data_clk>; 1664 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1666 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1667 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1668 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1669 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1670 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1671 dma-names = "tx", "rx"; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 status = "disabled"; 1675 }; 1676 1677 spi13: spi@a94000 { 1678 compatible = "qcom,geni-spi"; 1679 reg = <0x0 0x00a94000 0x0 0x4000>; 1680 clock-names = "se"; 1681 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1683 pinctrl-names = "default"; 1684 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1686 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1687 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1688 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1689 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1690 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1691 dma-names = "tx", "rx"; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 status = "disabled"; 1695 }; 1696 1697 i2c14: i2c@a98000 { 1698 compatible = "qcom,geni-i2c"; 1699 reg = <0 0x00a98000 0 0x4000>; 1700 clock-names = "se"; 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1702 pinctrl-names = "default"; 1703 pinctrl-0 = <&qup_i2c14_data_clk>; 1704 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1705 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1706 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1707 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1708 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1709 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1710 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1711 dma-names = "tx", "rx"; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 status = "disabled"; 1715 }; 1716 1717 spi14: spi@a98000 { 1718 compatible = "qcom,geni-spi"; 1719 reg = <0x0 0x00a98000 0x0 0x4000>; 1720 clock-names = "se"; 1721 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1723 pinctrl-names = "default"; 1724 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1725 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1726 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1727 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1728 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1729 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1730 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1731 dma-names = "tx", "rx"; 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 status = "disabled"; 1735 }; 1736 }; 1737 1738 pcie0: pci@1c00000 { 1739 compatible = "qcom,pcie-sm8450-pcie0"; 1740 reg = <0 0x01c00000 0 0x3000>, 1741 <0 0x60000000 0 0xf1d>, 1742 <0 0x60000f20 0 0xa8>, 1743 <0 0x60001000 0 0x1000>, 1744 <0 0x60100000 0 0x100000>; 1745 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1746 device_type = "pci"; 1747 linux,pci-domain = <0>; 1748 bus-range = <0x00 0xff>; 1749 num-lanes = <1>; 1750 1751 #address-cells = <3>; 1752 #size-cells = <2>; 1753 1754 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1755 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1756 1757 /* 1758 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1759 * Hence, the IDs are swapped. 1760 */ 1761 msi-map = <0x0 &gic_its 0x5981 0x1>, 1762 <0x100 &gic_its 0x5980 0x1>; 1763 msi-map-mask = <0xff00>; 1764 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1765 interrupt-names = "msi"; 1766 #interrupt-cells = <1>; 1767 interrupt-map-mask = <0 0 0 0x7>; 1768 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1769 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1770 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1771 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1772 1773 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1774 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1775 <&pcie0_lane>, 1776 <&rpmhcc RPMH_CXO_CLK>, 1777 <&gcc GCC_PCIE_0_AUX_CLK>, 1778 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1779 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1780 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1781 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1782 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1783 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1784 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1785 clock-names = "pipe", 1786 "pipe_mux", 1787 "phy_pipe", 1788 "ref", 1789 "aux", 1790 "cfg", 1791 "bus_master", 1792 "bus_slave", 1793 "slave_q2a", 1794 "ddrss_sf_tbu", 1795 "aggre0", 1796 "aggre1"; 1797 1798 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1799 <0x100 &apps_smmu 0x1c01 0x1>; 1800 1801 resets = <&gcc GCC_PCIE_0_BCR>; 1802 reset-names = "pci"; 1803 1804 power-domains = <&gcc PCIE_0_GDSC>; 1805 1806 phys = <&pcie0_lane>; 1807 phy-names = "pciephy"; 1808 1809 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1810 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1811 1812 pinctrl-names = "default"; 1813 pinctrl-0 = <&pcie0_default_state>; 1814 1815 status = "disabled"; 1816 }; 1817 1818 pcie0_phy: phy@1c06000 { 1819 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1820 reg = <0 0x01c06000 0 0x200>; 1821 #address-cells = <2>; 1822 #size-cells = <2>; 1823 ranges; 1824 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1825 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1826 <&gcc GCC_PCIE_0_CLKREF_EN>, 1827 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1828 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1829 1830 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1831 reset-names = "phy"; 1832 1833 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1834 assigned-clock-rates = <100000000>; 1835 1836 status = "disabled"; 1837 1838 pcie0_lane: phy@1c06200 { 1839 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1840 <0 0x01c07000 0 0x200>, /* rx */ 1841 <0 0x01c06200 0 0x200>, /* pcs */ 1842 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1843 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1844 clock-names = "pipe0"; 1845 1846 #clock-cells = <0>; 1847 #phy-cells = <0>; 1848 clock-output-names = "pcie_0_pipe_clk"; 1849 }; 1850 }; 1851 1852 pcie1: pci@1c08000 { 1853 compatible = "qcom,pcie-sm8450-pcie1"; 1854 reg = <0 0x01c08000 0 0x3000>, 1855 <0 0x40000000 0 0xf1d>, 1856 <0 0x40000f20 0 0xa8>, 1857 <0 0x40001000 0 0x1000>, 1858 <0 0x40100000 0 0x100000>; 1859 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1860 device_type = "pci"; 1861 linux,pci-domain = <1>; 1862 bus-range = <0x00 0xff>; 1863 num-lanes = <2>; 1864 1865 #address-cells = <3>; 1866 #size-cells = <2>; 1867 1868 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1869 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1870 1871 /* 1872 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1873 * Hence, the IDs are swapped. 1874 */ 1875 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1876 <0x100 &gic_its 0x5a00 0x1>; 1877 msi-map-mask = <0xff00>; 1878 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1879 interrupt-names = "msi"; 1880 #interrupt-cells = <1>; 1881 interrupt-map-mask = <0 0 0 0x7>; 1882 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1883 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1884 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1885 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1886 1887 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1888 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1889 <&pcie1_lane>, 1890 <&rpmhcc RPMH_CXO_CLK>, 1891 <&gcc GCC_PCIE_1_AUX_CLK>, 1892 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1893 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1894 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1895 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1896 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1897 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1898 clock-names = "pipe", 1899 "pipe_mux", 1900 "phy_pipe", 1901 "ref", 1902 "aux", 1903 "cfg", 1904 "bus_master", 1905 "bus_slave", 1906 "slave_q2a", 1907 "ddrss_sf_tbu", 1908 "aggre1"; 1909 1910 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1911 <0x100 &apps_smmu 0x1c81 0x1>; 1912 1913 resets = <&gcc GCC_PCIE_1_BCR>; 1914 reset-names = "pci"; 1915 1916 power-domains = <&gcc PCIE_1_GDSC>; 1917 1918 phys = <&pcie1_lane>; 1919 phy-names = "pciephy"; 1920 1921 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1922 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1923 1924 pinctrl-names = "default"; 1925 pinctrl-0 = <&pcie1_default_state>; 1926 1927 status = "disabled"; 1928 }; 1929 1930 pcie1_phy: phy@1c0f000 { 1931 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1932 reg = <0 0x01c0f000 0 0x200>; 1933 #address-cells = <2>; 1934 #size-cells = <2>; 1935 ranges; 1936 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1937 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1938 <&gcc GCC_PCIE_1_CLKREF_EN>, 1939 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1940 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1941 1942 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1943 reset-names = "phy"; 1944 1945 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1946 assigned-clock-rates = <100000000>; 1947 1948 status = "disabled"; 1949 1950 pcie1_lane: phy@1c0e000 { 1951 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1952 <0 0x01c0e200 0 0x300>, /* rx */ 1953 <0 0x01c0f200 0 0x200>, /* pcs */ 1954 <0 0x01c0e800 0 0x200>, /* tx */ 1955 <0 0x01c0ea00 0 0x300>, /* rx */ 1956 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1957 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1958 clock-names = "pipe0"; 1959 1960 #clock-cells = <0>; 1961 #phy-cells = <0>; 1962 clock-output-names = "pcie_1_pipe_clk"; 1963 }; 1964 }; 1965 1966 config_noc: interconnect@1500000 { 1967 compatible = "qcom,sm8450-config-noc"; 1968 reg = <0 0x01500000 0 0x1c000>; 1969 #interconnect-cells = <2>; 1970 qcom,bcm-voters = <&apps_bcm_voter>; 1971 }; 1972 1973 system_noc: interconnect@1680000 { 1974 compatible = "qcom,sm8450-system-noc"; 1975 reg = <0 0x01680000 0 0x1e200>; 1976 #interconnect-cells = <2>; 1977 qcom,bcm-voters = <&apps_bcm_voter>; 1978 }; 1979 1980 pcie_noc: interconnect@16c0000 { 1981 compatible = "qcom,sm8450-pcie-anoc"; 1982 reg = <0 0x016c0000 0 0xe280>; 1983 #interconnect-cells = <2>; 1984 qcom,bcm-voters = <&apps_bcm_voter>; 1985 }; 1986 1987 aggre1_noc: interconnect@16e0000 { 1988 compatible = "qcom,sm8450-aggre1-noc"; 1989 reg = <0 0x016e0000 0 0x1c080>; 1990 #interconnect-cells = <2>; 1991 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1992 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1993 qcom,bcm-voters = <&apps_bcm_voter>; 1994 }; 1995 1996 aggre2_noc: interconnect@1700000 { 1997 compatible = "qcom,sm8450-aggre2-noc"; 1998 reg = <0 0x01700000 0 0x31080>; 1999 #interconnect-cells = <2>; 2000 qcom,bcm-voters = <&apps_bcm_voter>; 2001 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2002 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2003 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2004 <&rpmhcc RPMH_IPA_CLK>; 2005 }; 2006 2007 mmss_noc: interconnect@1740000 { 2008 compatible = "qcom,sm8450-mmss-noc"; 2009 reg = <0 0x01740000 0 0x1f080>; 2010 #interconnect-cells = <2>; 2011 qcom,bcm-voters = <&apps_bcm_voter>; 2012 }; 2013 2014 tcsr_mutex: hwlock@1f40000 { 2015 compatible = "qcom,tcsr-mutex"; 2016 reg = <0x0 0x01f40000 0x0 0x40000>; 2017 #hwlock-cells = <1>; 2018 }; 2019 2020 tcsr: syscon@1fc0000 { 2021 compatible = "qcom,sm8450-tcsr", "syscon"; 2022 reg = <0x0 0x1fc0000 0x0 0x30000>; 2023 }; 2024 2025 usb_1_hsphy: phy@88e3000 { 2026 compatible = "qcom,sm8450-usb-hs-phy", 2027 "qcom,usb-snps-hs-7nm-phy"; 2028 reg = <0 0x088e3000 0 0x400>; 2029 status = "disabled"; 2030 #phy-cells = <0>; 2031 2032 clocks = <&rpmhcc RPMH_CXO_CLK>; 2033 clock-names = "ref"; 2034 2035 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2036 }; 2037 2038 usb_1_qmpphy: phy@88e8000 { 2039 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2040 reg = <0 0x088e8000 0 0x3000>; 2041 2042 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2043 <&rpmhcc RPMH_CXO_CLK>, 2044 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2045 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2046 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2047 2048 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2049 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2050 reset-names = "phy", "common"; 2051 2052 #clock-cells = <1>; 2053 #phy-cells = <1>; 2054 2055 status = "disabled"; 2056 }; 2057 2058 remoteproc_slpi: remoteproc@2400000 { 2059 compatible = "qcom,sm8450-slpi-pas"; 2060 reg = <0 0x02400000 0 0x4000>; 2061 2062 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2063 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2064 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2065 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2066 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2067 interrupt-names = "wdog", "fatal", "ready", 2068 "handover", "stop-ack"; 2069 2070 clocks = <&rpmhcc RPMH_CXO_CLK>; 2071 clock-names = "xo"; 2072 2073 power-domains = <&rpmhpd SM8450_LCX>, 2074 <&rpmhpd SM8450_LMX>; 2075 power-domain-names = "lcx", "lmx"; 2076 2077 memory-region = <&slpi_mem>; 2078 2079 qcom,qmp = <&aoss_qmp>; 2080 2081 qcom,smem-states = <&smp2p_slpi_out 0>; 2082 qcom,smem-state-names = "stop"; 2083 2084 status = "disabled"; 2085 2086 glink-edge { 2087 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2088 IPCC_MPROC_SIGNAL_GLINK_QMP 2089 IRQ_TYPE_EDGE_RISING>; 2090 mboxes = <&ipcc IPCC_CLIENT_SLPI 2091 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2092 2093 label = "slpi"; 2094 qcom,remote-pid = <3>; 2095 2096 fastrpc { 2097 compatible = "qcom,fastrpc"; 2098 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2099 label = "sdsp"; 2100 #address-cells = <1>; 2101 #size-cells = <0>; 2102 2103 compute-cb@1 { 2104 compatible = "qcom,fastrpc-compute-cb"; 2105 reg = <1>; 2106 iommus = <&apps_smmu 0x0541 0x0>; 2107 }; 2108 2109 compute-cb@2 { 2110 compatible = "qcom,fastrpc-compute-cb"; 2111 reg = <2>; 2112 iommus = <&apps_smmu 0x0542 0x0>; 2113 }; 2114 2115 compute-cb@3 { 2116 compatible = "qcom,fastrpc-compute-cb"; 2117 reg = <3>; 2118 iommus = <&apps_smmu 0x0543 0x0>; 2119 /* note: shared-cb = <4> in downstream */ 2120 }; 2121 }; 2122 }; 2123 }; 2124 2125 wsa2macro: codec@31e0000 { 2126 compatible = "qcom,sm8450-lpass-wsa-macro"; 2127 reg = <0 0x031e0000 0 0x1000>; 2128 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2129 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2130 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2131 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2132 <&vamacro>; 2133 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2134 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2135 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2136 assigned-clock-rates = <19200000>, <19200000>; 2137 2138 #clock-cells = <0>; 2139 clock-output-names = "wsa2-mclk"; 2140 pinctrl-names = "default"; 2141 pinctrl-0 = <&wsa2_swr_active>; 2142 #sound-dai-cells = <1>; 2143 }; 2144 2145 swr4: soundwire-controller@31f0000 { 2146 compatible = "qcom,soundwire-v1.7.0"; 2147 reg = <0 0x031f0000 0 0x2000>; 2148 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2149 clocks = <&wsa2macro>; 2150 clock-names = "iface"; 2151 label = "WSA2"; 2152 2153 qcom,din-ports = <2>; 2154 qcom,dout-ports = <6>; 2155 2156 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2157 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2158 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2159 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2160 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2161 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2162 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2163 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2164 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2165 2166 #address-cells = <2>; 2167 #size-cells = <0>; 2168 #sound-dai-cells = <1>; 2169 status = "disabled"; 2170 }; 2171 2172 rxmacro: codec@3200000 { 2173 compatible = "qcom,sm8450-lpass-rx-macro"; 2174 reg = <0 0x03200000 0 0x1000>; 2175 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2176 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2177 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2178 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2179 <&vamacro>; 2180 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2181 2182 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2183 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2184 assigned-clock-rates = <19200000>, <19200000>; 2185 2186 #clock-cells = <0>; 2187 clock-output-names = "mclk"; 2188 pinctrl-names = "default"; 2189 pinctrl-0 = <&rx_swr_active>; 2190 #sound-dai-cells = <1>; 2191 }; 2192 2193 swr1: soundwire-controller@3210000 { 2194 compatible = "qcom,soundwire-v1.7.0"; 2195 reg = <0 0x03210000 0 0x2000>; 2196 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2197 clocks = <&rxmacro>; 2198 clock-names = "iface"; 2199 label = "RX"; 2200 qcom,din-ports = <0>; 2201 qcom,dout-ports = <5>; 2202 2203 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2204 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2205 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2206 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2207 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2208 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2209 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2210 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2211 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2212 2213 #address-cells = <2>; 2214 #size-cells = <0>; 2215 #sound-dai-cells = <1>; 2216 status = "disabled"; 2217 }; 2218 2219 txmacro: codec@3220000 { 2220 compatible = "qcom,sm8450-lpass-tx-macro"; 2221 reg = <0 0x03220000 0 0x1000>; 2222 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2223 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2224 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2225 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2226 <&vamacro>; 2227 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2228 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2229 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2230 assigned-clock-rates = <19200000>, <19200000>; 2231 2232 #clock-cells = <0>; 2233 clock-output-names = "mclk"; 2234 pinctrl-names = "default"; 2235 pinctrl-0 = <&tx_swr_active>; 2236 #sound-dai-cells = <1>; 2237 }; 2238 2239 wsamacro: codec@3240000 { 2240 compatible = "qcom,sm8450-lpass-wsa-macro"; 2241 reg = <0 0x03240000 0 0x1000>; 2242 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2243 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2244 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2245 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2246 <&vamacro>; 2247 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2248 2249 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2250 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2251 assigned-clock-rates = <19200000>, <19200000>; 2252 2253 #clock-cells = <0>; 2254 clock-output-names = "mclk"; 2255 pinctrl-names = "default"; 2256 pinctrl-0 = <&wsa_swr_active>; 2257 #sound-dai-cells = <1>; 2258 }; 2259 2260 swr0: soundwire-controller@3250000 { 2261 compatible = "qcom,soundwire-v1.7.0"; 2262 reg = <0 0x03250000 0 0x2000>; 2263 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2264 clocks = <&wsamacro>; 2265 clock-names = "iface"; 2266 label = "WSA"; 2267 2268 qcom,din-ports = <2>; 2269 qcom,dout-ports = <6>; 2270 2271 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2272 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2273 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2274 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2275 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2276 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2277 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2278 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2279 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2280 2281 #address-cells = <2>; 2282 #size-cells = <0>; 2283 #sound-dai-cells = <1>; 2284 status = "disabled"; 2285 }; 2286 2287 swr2: soundwire-controller@33b0000 { 2288 compatible = "qcom,soundwire-v1.7.0"; 2289 reg = <0 0x033b0000 0 0x2000>; 2290 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2292 interrupt-names = "core", "wakeup"; 2293 2294 clocks = <&vamacro>; 2295 clock-names = "iface"; 2296 label = "TX"; 2297 2298 qcom,din-ports = <4>; 2299 qcom,dout-ports = <0>; 2300 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2301 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2302 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2303 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2304 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2305 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2306 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2307 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2308 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2309 2310 #address-cells = <2>; 2311 #size-cells = <0>; 2312 #sound-dai-cells = <1>; 2313 status = "disabled"; 2314 }; 2315 2316 vamacro: codec@33f0000 { 2317 compatible = "qcom,sm8450-lpass-va-macro"; 2318 reg = <0 0x033f0000 0 0x1000>; 2319 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2320 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2321 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2322 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2323 clock-names = "mclk", "macro", "dcodec", "npl"; 2324 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2325 assigned-clock-rates = <19200000>; 2326 2327 #clock-cells = <0>; 2328 clock-output-names = "fsgen"; 2329 #sound-dai-cells = <1>; 2330 status = "disabled"; 2331 }; 2332 2333 remoteproc_adsp: remoteproc@30000000 { 2334 compatible = "qcom,sm8450-adsp-pas"; 2335 reg = <0 0x30000000 0 0x100>; 2336 2337 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2338 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2339 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2340 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2341 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2342 interrupt-names = "wdog", "fatal", "ready", 2343 "handover", "stop-ack"; 2344 2345 clocks = <&rpmhcc RPMH_CXO_CLK>; 2346 clock-names = "xo"; 2347 2348 power-domains = <&rpmhpd SM8450_LCX>, 2349 <&rpmhpd SM8450_LMX>; 2350 power-domain-names = "lcx", "lmx"; 2351 2352 memory-region = <&adsp_mem>; 2353 2354 qcom,qmp = <&aoss_qmp>; 2355 2356 qcom,smem-states = <&smp2p_adsp_out 0>; 2357 qcom,smem-state-names = "stop"; 2358 2359 status = "disabled"; 2360 2361 remoteproc_adsp_glink: glink-edge { 2362 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2363 IPCC_MPROC_SIGNAL_GLINK_QMP 2364 IRQ_TYPE_EDGE_RISING>; 2365 mboxes = <&ipcc IPCC_CLIENT_LPASS 2366 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2367 2368 label = "lpass"; 2369 qcom,remote-pid = <2>; 2370 2371 gpr { 2372 compatible = "qcom,gpr"; 2373 qcom,glink-channels = "adsp_apps"; 2374 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2375 qcom,intents = <512 20>; 2376 #address-cells = <1>; 2377 #size-cells = <0>; 2378 2379 q6apm: service@1 { 2380 compatible = "qcom,q6apm"; 2381 reg = <GPR_APM_MODULE_IID>; 2382 #sound-dai-cells = <0>; 2383 qcom,protection-domain = "avs/audio", 2384 "msm/adsp/audio_pd"; 2385 2386 q6apmdai: dais { 2387 compatible = "qcom,q6apm-dais"; 2388 iommus = <&apps_smmu 0x1801 0x0>; 2389 }; 2390 2391 q6apmbedai: bedais { 2392 compatible = "qcom,q6apm-lpass-dais"; 2393 #sound-dai-cells = <1>; 2394 }; 2395 }; 2396 2397 q6prm: service@2 { 2398 compatible = "qcom,q6prm"; 2399 reg = <GPR_PRM_MODULE_IID>; 2400 qcom,protection-domain = "avs/audio", 2401 "msm/adsp/audio_pd"; 2402 2403 q6prmcc: clock-controller { 2404 compatible = "qcom,q6prm-lpass-clocks"; 2405 #clock-cells = <2>; 2406 }; 2407 }; 2408 }; 2409 2410 fastrpc { 2411 compatible = "qcom,fastrpc"; 2412 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2413 label = "adsp"; 2414 #address-cells = <1>; 2415 #size-cells = <0>; 2416 2417 compute-cb@3 { 2418 compatible = "qcom,fastrpc-compute-cb"; 2419 reg = <3>; 2420 iommus = <&apps_smmu 0x1803 0x0>; 2421 }; 2422 2423 compute-cb@4 { 2424 compatible = "qcom,fastrpc-compute-cb"; 2425 reg = <4>; 2426 iommus = <&apps_smmu 0x1804 0x0>; 2427 }; 2428 2429 compute-cb@5 { 2430 compatible = "qcom,fastrpc-compute-cb"; 2431 reg = <5>; 2432 iommus = <&apps_smmu 0x1805 0x0>; 2433 }; 2434 }; 2435 }; 2436 }; 2437 2438 remoteproc_cdsp: remoteproc@32300000 { 2439 compatible = "qcom,sm8450-cdsp-pas"; 2440 reg = <0 0x32300000 0 0x1400000>; 2441 2442 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2443 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2444 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2445 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2446 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2447 interrupt-names = "wdog", "fatal", "ready", 2448 "handover", "stop-ack"; 2449 2450 clocks = <&rpmhcc RPMH_CXO_CLK>; 2451 clock-names = "xo"; 2452 2453 power-domains = <&rpmhpd SM8450_CX>, 2454 <&rpmhpd SM8450_MXC>; 2455 power-domain-names = "cx", "mxc"; 2456 2457 memory-region = <&cdsp_mem>; 2458 2459 qcom,qmp = <&aoss_qmp>; 2460 2461 qcom,smem-states = <&smp2p_cdsp_out 0>; 2462 qcom,smem-state-names = "stop"; 2463 2464 status = "disabled"; 2465 2466 glink-edge { 2467 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2468 IPCC_MPROC_SIGNAL_GLINK_QMP 2469 IRQ_TYPE_EDGE_RISING>; 2470 mboxes = <&ipcc IPCC_CLIENT_CDSP 2471 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2472 2473 label = "cdsp"; 2474 qcom,remote-pid = <5>; 2475 2476 fastrpc { 2477 compatible = "qcom,fastrpc"; 2478 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2479 label = "cdsp"; 2480 #address-cells = <1>; 2481 #size-cells = <0>; 2482 2483 compute-cb@1 { 2484 compatible = "qcom,fastrpc-compute-cb"; 2485 reg = <1>; 2486 iommus = <&apps_smmu 0x2161 0x0400>, 2487 <&apps_smmu 0x1021 0x1420>; 2488 }; 2489 2490 compute-cb@2 { 2491 compatible = "qcom,fastrpc-compute-cb"; 2492 reg = <2>; 2493 iommus = <&apps_smmu 0x2162 0x0400>, 2494 <&apps_smmu 0x1022 0x1420>; 2495 }; 2496 2497 compute-cb@3 { 2498 compatible = "qcom,fastrpc-compute-cb"; 2499 reg = <3>; 2500 iommus = <&apps_smmu 0x2163 0x0400>, 2501 <&apps_smmu 0x1023 0x1420>; 2502 }; 2503 2504 compute-cb@4 { 2505 compatible = "qcom,fastrpc-compute-cb"; 2506 reg = <4>; 2507 iommus = <&apps_smmu 0x2164 0x0400>, 2508 <&apps_smmu 0x1024 0x1420>; 2509 }; 2510 2511 compute-cb@5 { 2512 compatible = "qcom,fastrpc-compute-cb"; 2513 reg = <5>; 2514 iommus = <&apps_smmu 0x2165 0x0400>, 2515 <&apps_smmu 0x1025 0x1420>; 2516 }; 2517 2518 compute-cb@6 { 2519 compatible = "qcom,fastrpc-compute-cb"; 2520 reg = <6>; 2521 iommus = <&apps_smmu 0x2166 0x0400>, 2522 <&apps_smmu 0x1026 0x1420>; 2523 }; 2524 2525 compute-cb@7 { 2526 compatible = "qcom,fastrpc-compute-cb"; 2527 reg = <7>; 2528 iommus = <&apps_smmu 0x2167 0x0400>, 2529 <&apps_smmu 0x1027 0x1420>; 2530 }; 2531 2532 compute-cb@8 { 2533 compatible = "qcom,fastrpc-compute-cb"; 2534 reg = <8>; 2535 iommus = <&apps_smmu 0x2168 0x0400>, 2536 <&apps_smmu 0x1028 0x1420>; 2537 }; 2538 2539 /* note: secure cb9 in downstream */ 2540 }; 2541 }; 2542 }; 2543 2544 remoteproc_mpss: remoteproc@4080000 { 2545 compatible = "qcom,sm8450-mpss-pas"; 2546 reg = <0x0 0x04080000 0x0 0x4040>; 2547 2548 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2549 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2550 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2551 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2552 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2553 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2554 interrupt-names = "wdog", "fatal", "ready", "handover", 2555 "stop-ack", "shutdown-ack"; 2556 2557 clocks = <&rpmhcc RPMH_CXO_CLK>; 2558 clock-names = "xo"; 2559 2560 power-domains = <&rpmhpd SM8450_CX>, 2561 <&rpmhpd SM8450_MSS>; 2562 power-domain-names = "cx", "mss"; 2563 2564 memory-region = <&mpss_mem>; 2565 2566 qcom,qmp = <&aoss_qmp>; 2567 2568 qcom,smem-states = <&smp2p_modem_out 0>; 2569 qcom,smem-state-names = "stop"; 2570 2571 status = "disabled"; 2572 2573 glink-edge { 2574 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2575 IPCC_MPROC_SIGNAL_GLINK_QMP 2576 IRQ_TYPE_EDGE_RISING>; 2577 mboxes = <&ipcc IPCC_CLIENT_MPSS 2578 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2579 label = "modem"; 2580 qcom,remote-pid = <1>; 2581 }; 2582 }; 2583 2584 cci0: cci@ac15000 { 2585 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2586 reg = <0 0x0ac15000 0 0x1000>; 2587 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2588 power-domains = <&camcc TITAN_TOP_GDSC>; 2589 2590 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2591 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2592 <&camcc CAM_CC_CPAS_AHB_CLK>, 2593 <&camcc CAM_CC_CCI_0_CLK>, 2594 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2595 clock-names = "camnoc_axi", 2596 "slow_ahb_src", 2597 "cpas_ahb", 2598 "cci", 2599 "cci_src"; 2600 pinctrl-0 = <&cci0_default &cci1_default>; 2601 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2602 pinctrl-names = "default", "sleep"; 2603 2604 status = "disabled"; 2605 #address-cells = <1>; 2606 #size-cells = <0>; 2607 2608 cci0_i2c0: i2c-bus@0 { 2609 reg = <0>; 2610 clock-frequency = <1000000>; 2611 #address-cells = <1>; 2612 #size-cells = <0>; 2613 }; 2614 2615 cci0_i2c1: i2c-bus@1 { 2616 reg = <1>; 2617 clock-frequency = <1000000>; 2618 #address-cells = <1>; 2619 #size-cells = <0>; 2620 }; 2621 }; 2622 2623 cci1: cci@ac16000 { 2624 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2625 reg = <0 0x0ac16000 0 0x1000>; 2626 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2627 power-domains = <&camcc TITAN_TOP_GDSC>; 2628 2629 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2630 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2631 <&camcc CAM_CC_CPAS_AHB_CLK>, 2632 <&camcc CAM_CC_CCI_1_CLK>, 2633 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2634 clock-names = "camnoc_axi", 2635 "slow_ahb_src", 2636 "cpas_ahb", 2637 "cci", 2638 "cci_src"; 2639 pinctrl-0 = <&cci2_default &cci3_default>; 2640 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2641 pinctrl-names = "default", "sleep"; 2642 2643 status = "disabled"; 2644 #address-cells = <1>; 2645 #size-cells = <0>; 2646 2647 cci1_i2c0: i2c-bus@0 { 2648 reg = <0>; 2649 clock-frequency = <1000000>; 2650 #address-cells = <1>; 2651 #size-cells = <0>; 2652 }; 2653 2654 cci1_i2c1: i2c-bus@1 { 2655 reg = <1>; 2656 clock-frequency = <1000000>; 2657 #address-cells = <1>; 2658 #size-cells = <0>; 2659 }; 2660 }; 2661 2662 camcc: clock-controller@ade0000 { 2663 compatible = "qcom,sm8450-camcc"; 2664 reg = <0 0x0ade0000 0 0x20000>; 2665 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2666 <&rpmhcc RPMH_CXO_CLK>, 2667 <&rpmhcc RPMH_CXO_CLK_A>, 2668 <&sleep_clk>; 2669 power-domains = <&rpmhpd SM8450_MMCX>; 2670 required-opps = <&rpmhpd_opp_low_svs>; 2671 #clock-cells = <1>; 2672 #reset-cells = <1>; 2673 #power-domain-cells = <1>; 2674 status = "disabled"; 2675 }; 2676 2677 mdss: display-subsystem@ae00000 { 2678 compatible = "qcom,sm8450-mdss"; 2679 reg = <0 0x0ae00000 0 0x1000>; 2680 reg-names = "mdss"; 2681 2682 /* same path used twice */ 2683 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2684 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; 2685 interconnect-names = "mdp0-mem", "mdp1-mem"; 2686 2687 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2688 2689 power-domains = <&dispcc MDSS_GDSC>; 2690 2691 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2692 <&gcc GCC_DISP_HF_AXI_CLK>, 2693 <&gcc GCC_DISP_SF_AXI_CLK>, 2694 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2695 2696 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2697 interrupt-controller; 2698 #interrupt-cells = <1>; 2699 2700 iommus = <&apps_smmu 0x2800 0x402>; 2701 2702 #address-cells = <2>; 2703 #size-cells = <2>; 2704 ranges; 2705 2706 status = "disabled"; 2707 2708 mdss_mdp: display-controller@ae01000 { 2709 compatible = "qcom,sm8450-dpu"; 2710 reg = <0 0x0ae01000 0 0x8f000>, 2711 <0 0x0aeb0000 0 0x2008>; 2712 reg-names = "mdp", "vbif"; 2713 2714 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2715 <&gcc GCC_DISP_SF_AXI_CLK>, 2716 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2717 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2718 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2719 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2720 clock-names = "bus", 2721 "nrt_bus", 2722 "iface", 2723 "lut", 2724 "core", 2725 "vsync"; 2726 2727 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2728 assigned-clock-rates = <19200000>; 2729 2730 operating-points-v2 = <&mdp_opp_table>; 2731 power-domains = <&rpmhpd SM8450_MMCX>; 2732 2733 interrupt-parent = <&mdss>; 2734 interrupts = <0>; 2735 2736 ports { 2737 #address-cells = <1>; 2738 #size-cells = <0>; 2739 2740 port@0 { 2741 reg = <0>; 2742 dpu_intf1_out: endpoint { 2743 remote-endpoint = <&mdss_dsi0_in>; 2744 }; 2745 }; 2746 2747 port@1 { 2748 reg = <1>; 2749 dpu_intf2_out: endpoint { 2750 remote-endpoint = <&mdss_dsi1_in>; 2751 }; 2752 }; 2753 2754 port@2 { 2755 reg = <2>; 2756 dpu_intf0_out: endpoint { 2757 remote-endpoint = <&mdss_dp0_in>; 2758 }; 2759 }; 2760 }; 2761 2762 mdp_opp_table: opp-table { 2763 compatible = "operating-points-v2"; 2764 2765 opp-172000000 { 2766 opp-hz = /bits/ 64 <172000000>; 2767 required-opps = <&rpmhpd_opp_low_svs_d1>; 2768 }; 2769 2770 opp-200000000 { 2771 opp-hz = /bits/ 64 <200000000>; 2772 required-opps = <&rpmhpd_opp_low_svs>; 2773 }; 2774 2775 opp-325000000 { 2776 opp-hz = /bits/ 64 <325000000>; 2777 required-opps = <&rpmhpd_opp_svs>; 2778 }; 2779 2780 opp-375000000 { 2781 opp-hz = /bits/ 64 <375000000>; 2782 required-opps = <&rpmhpd_opp_svs_l1>; 2783 }; 2784 2785 opp-500000000 { 2786 opp-hz = /bits/ 64 <500000000>; 2787 required-opps = <&rpmhpd_opp_nom>; 2788 }; 2789 }; 2790 }; 2791 2792 mdss_dp0: displayport-controller@ae90000 { 2793 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 2794 reg = <0 0xae90000 0 0x200>, 2795 <0 0xae90200 0 0x200>, 2796 <0 0xae90400 0 0xc00>, 2797 <0 0xae91000 0 0x400>, 2798 <0 0xae91400 0 0x400>; 2799 interrupt-parent = <&mdss>; 2800 interrupts = <12>; 2801 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2802 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2803 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2804 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2805 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2806 clock-names = "core_iface", 2807 "core_aux", 2808 "ctrl_link", 2809 "ctrl_link_iface", 2810 "stream_pixel"; 2811 2812 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2813 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2814 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2815 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2816 2817 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2818 phy-names = "dp"; 2819 2820 #sound-dai-cells = <0>; 2821 2822 operating-points-v2 = <&dp_opp_table>; 2823 power-domains = <&rpmhpd SM8450_MMCX>; 2824 2825 status = "disabled"; 2826 2827 ports { 2828 #address-cells = <1>; 2829 #size-cells = <0>; 2830 2831 port@0 { 2832 reg = <0>; 2833 mdss_dp0_in: endpoint { 2834 remote-endpoint = <&dpu_intf0_out>; 2835 }; 2836 }; 2837 }; 2838 2839 dp_opp_table: opp-table { 2840 compatible = "operating-points-v2"; 2841 2842 opp-160000000 { 2843 opp-hz = /bits/ 64 <160000000>; 2844 required-opps = <&rpmhpd_opp_low_svs>; 2845 }; 2846 2847 opp-270000000 { 2848 opp-hz = /bits/ 64 <270000000>; 2849 required-opps = <&rpmhpd_opp_svs>; 2850 }; 2851 2852 opp-540000000 { 2853 opp-hz = /bits/ 64 <540000000>; 2854 required-opps = <&rpmhpd_opp_svs_l1>; 2855 }; 2856 2857 opp-810000000 { 2858 opp-hz = /bits/ 64 <810000000>; 2859 required-opps = <&rpmhpd_opp_nom>; 2860 }; 2861 }; 2862 }; 2863 2864 mdss_dsi0: dsi@ae94000 { 2865 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2866 reg = <0 0x0ae94000 0 0x400>; 2867 reg-names = "dsi_ctrl"; 2868 2869 interrupt-parent = <&mdss>; 2870 interrupts = <4>; 2871 2872 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2873 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2874 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2875 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2876 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2877 <&gcc GCC_DISP_HF_AXI_CLK>; 2878 clock-names = "byte", 2879 "byte_intf", 2880 "pixel", 2881 "core", 2882 "iface", 2883 "bus"; 2884 2885 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2886 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2887 2888 operating-points-v2 = <&mdss_dsi_opp_table>; 2889 power-domains = <&rpmhpd SM8450_MMCX>; 2890 2891 phys = <&mdss_dsi0_phy>; 2892 phy-names = "dsi"; 2893 2894 #address-cells = <1>; 2895 #size-cells = <0>; 2896 2897 status = "disabled"; 2898 2899 ports { 2900 #address-cells = <1>; 2901 #size-cells = <0>; 2902 2903 port@0 { 2904 reg = <0>; 2905 mdss_dsi0_in: endpoint { 2906 remote-endpoint = <&dpu_intf1_out>; 2907 }; 2908 }; 2909 2910 port@1 { 2911 reg = <1>; 2912 mdss_dsi0_out: endpoint { 2913 }; 2914 }; 2915 }; 2916 2917 mdss_dsi_opp_table: opp-table { 2918 compatible = "operating-points-v2"; 2919 2920 opp-187500000 { 2921 opp-hz = /bits/ 64 <187500000>; 2922 required-opps = <&rpmhpd_opp_low_svs>; 2923 }; 2924 2925 opp-300000000 { 2926 opp-hz = /bits/ 64 <300000000>; 2927 required-opps = <&rpmhpd_opp_svs>; 2928 }; 2929 2930 opp-358000000 { 2931 opp-hz = /bits/ 64 <358000000>; 2932 required-opps = <&rpmhpd_opp_svs_l1>; 2933 }; 2934 }; 2935 }; 2936 2937 mdss_dsi0_phy: phy@ae94400 { 2938 compatible = "qcom,sm8450-dsi-phy-5nm"; 2939 reg = <0 0x0ae94400 0 0x200>, 2940 <0 0x0ae94600 0 0x280>, 2941 <0 0x0ae94900 0 0x260>; 2942 reg-names = "dsi_phy", 2943 "dsi_phy_lane", 2944 "dsi_pll"; 2945 2946 #clock-cells = <1>; 2947 #phy-cells = <0>; 2948 2949 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2950 <&rpmhcc RPMH_CXO_CLK>; 2951 clock-names = "iface", "ref"; 2952 2953 status = "disabled"; 2954 }; 2955 2956 mdss_dsi1: dsi@ae96000 { 2957 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2958 reg = <0 0x0ae96000 0 0x400>; 2959 reg-names = "dsi_ctrl"; 2960 2961 interrupt-parent = <&mdss>; 2962 interrupts = <5>; 2963 2964 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2965 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2966 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2967 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2968 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2969 <&gcc GCC_DISP_HF_AXI_CLK>; 2970 clock-names = "byte", 2971 "byte_intf", 2972 "pixel", 2973 "core", 2974 "iface", 2975 "bus"; 2976 2977 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2978 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2979 2980 operating-points-v2 = <&mdss_dsi_opp_table>; 2981 power-domains = <&rpmhpd SM8450_MMCX>; 2982 2983 phys = <&mdss_dsi1_phy>; 2984 phy-names = "dsi"; 2985 2986 #address-cells = <1>; 2987 #size-cells = <0>; 2988 2989 status = "disabled"; 2990 2991 ports { 2992 #address-cells = <1>; 2993 #size-cells = <0>; 2994 2995 port@0 { 2996 reg = <0>; 2997 mdss_dsi1_in: endpoint { 2998 remote-endpoint = <&dpu_intf2_out>; 2999 }; 3000 }; 3001 3002 port@1 { 3003 reg = <1>; 3004 mdss_dsi1_out: endpoint { 3005 }; 3006 }; 3007 }; 3008 }; 3009 3010 mdss_dsi1_phy: phy@ae96400 { 3011 compatible = "qcom,sm8450-dsi-phy-5nm"; 3012 reg = <0 0x0ae96400 0 0x200>, 3013 <0 0x0ae96600 0 0x280>, 3014 <0 0x0ae96900 0 0x260>; 3015 reg-names = "dsi_phy", 3016 "dsi_phy_lane", 3017 "dsi_pll"; 3018 3019 #clock-cells = <1>; 3020 #phy-cells = <0>; 3021 3022 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3023 <&rpmhcc RPMH_CXO_CLK>; 3024 clock-names = "iface", "ref"; 3025 3026 status = "disabled"; 3027 }; 3028 }; 3029 3030 dispcc: clock-controller@af00000 { 3031 compatible = "qcom,sm8450-dispcc"; 3032 reg = <0 0x0af00000 0 0x20000>; 3033 clocks = <&rpmhcc RPMH_CXO_CLK>, 3034 <&rpmhcc RPMH_CXO_CLK_A>, 3035 <&gcc GCC_DISP_AHB_CLK>, 3036 <&sleep_clk>, 3037 <&mdss_dsi0_phy 0>, 3038 <&mdss_dsi0_phy 1>, 3039 <&mdss_dsi1_phy 0>, 3040 <&mdss_dsi1_phy 1>, 3041 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3042 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3043 <0>, /* dp1 */ 3044 <0>, 3045 <0>, /* dp2 */ 3046 <0>, 3047 <0>, /* dp3 */ 3048 <0>; 3049 power-domains = <&rpmhpd SM8450_MMCX>; 3050 required-opps = <&rpmhpd_opp_low_svs>; 3051 #clock-cells = <1>; 3052 #reset-cells = <1>; 3053 #power-domain-cells = <1>; 3054 status = "disabled"; 3055 }; 3056 3057 pdc: interrupt-controller@b220000 { 3058 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3059 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3060 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3061 <94 609 31>, <125 63 1>, <126 716 12>; 3062 #interrupt-cells = <2>; 3063 interrupt-parent = <&intc>; 3064 interrupt-controller; 3065 }; 3066 3067 tsens0: thermal-sensor@c263000 { 3068 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3069 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3070 <0 0x0c222000 0 0x1000>; /* SROT */ 3071 #qcom,sensors = <16>; 3072 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3074 interrupt-names = "uplow", "critical"; 3075 #thermal-sensor-cells = <1>; 3076 }; 3077 3078 tsens1: thermal-sensor@c265000 { 3079 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3080 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3081 <0 0x0c223000 0 0x1000>; /* SROT */ 3082 #qcom,sensors = <16>; 3083 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3085 interrupt-names = "uplow", "critical"; 3086 #thermal-sensor-cells = <1>; 3087 }; 3088 3089 aoss_qmp: power-management@c300000 { 3090 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3091 reg = <0 0x0c300000 0 0x400>; 3092 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3093 IRQ_TYPE_EDGE_RISING>; 3094 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3095 3096 #clock-cells = <0>; 3097 }; 3098 3099 spmi_bus: spmi@c400000 { 3100 compatible = "qcom,spmi-pmic-arb"; 3101 reg = <0 0x0c400000 0 0x00003000>, 3102 <0 0x0c500000 0 0x00400000>, 3103 <0 0x0c440000 0 0x00080000>, 3104 <0 0x0c4c0000 0 0x00010000>, 3105 <0 0x0c42d000 0 0x00010000>; 3106 reg-names = "core", 3107 "chnls", 3108 "obsrvr", 3109 "intr", 3110 "cnfg"; 3111 interrupt-names = "periph_irq"; 3112 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3113 qcom,ee = <0>; 3114 qcom,channel = <0>; 3115 interrupt-controller; 3116 #interrupt-cells = <4>; 3117 #address-cells = <2>; 3118 #size-cells = <0>; 3119 }; 3120 3121 ipcc: mailbox@ed18000 { 3122 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3123 reg = <0 0x0ed18000 0 0x1000>; 3124 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3125 interrupt-controller; 3126 #interrupt-cells = <3>; 3127 #mbox-cells = <2>; 3128 }; 3129 3130 tlmm: pinctrl@f100000 { 3131 compatible = "qcom,sm8450-tlmm"; 3132 reg = <0 0x0f100000 0 0x300000>; 3133 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3134 gpio-controller; 3135 #gpio-cells = <2>; 3136 interrupt-controller; 3137 #interrupt-cells = <2>; 3138 gpio-ranges = <&tlmm 0 0 211>; 3139 wakeup-parent = <&pdc>; 3140 3141 sdc2_default_state: sdc2-default-state { 3142 clk-pins { 3143 pins = "sdc2_clk"; 3144 drive-strength = <16>; 3145 bias-disable; 3146 }; 3147 3148 cmd-pins { 3149 pins = "sdc2_cmd"; 3150 drive-strength = <16>; 3151 bias-pull-up; 3152 }; 3153 3154 data-pins { 3155 pins = "sdc2_data"; 3156 drive-strength = <16>; 3157 bias-pull-up; 3158 }; 3159 }; 3160 3161 sdc2_sleep_state: sdc2-sleep-state { 3162 clk-pins { 3163 pins = "sdc2_clk"; 3164 drive-strength = <2>; 3165 bias-disable; 3166 }; 3167 3168 cmd-pins { 3169 pins = "sdc2_cmd"; 3170 drive-strength = <2>; 3171 bias-pull-up; 3172 }; 3173 3174 data-pins { 3175 pins = "sdc2_data"; 3176 drive-strength = <2>; 3177 bias-pull-up; 3178 }; 3179 }; 3180 3181 cci0_default: cci0-default-state { 3182 /* SDA, SCL */ 3183 pins = "gpio110", "gpio111"; 3184 function = "cci_i2c"; 3185 drive-strength = <2>; 3186 bias-pull-up; 3187 }; 3188 3189 cci0_sleep: cci0-sleep-state { 3190 /* SDA, SCL */ 3191 pins = "gpio110", "gpio111"; 3192 function = "cci_i2c"; 3193 drive-strength = <2>; 3194 bias-pull-down; 3195 }; 3196 3197 cci1_default: cci1-default-state { 3198 /* SDA, SCL */ 3199 pins = "gpio112", "gpio113"; 3200 function = "cci_i2c"; 3201 drive-strength = <2>; 3202 bias-pull-up; 3203 }; 3204 3205 cci1_sleep: cci1-sleep-state { 3206 /* SDA, SCL */ 3207 pins = "gpio112", "gpio113"; 3208 function = "cci_i2c"; 3209 drive-strength = <2>; 3210 bias-pull-down; 3211 }; 3212 3213 cci2_default: cci2-default-state { 3214 /* SDA, SCL */ 3215 pins = "gpio114", "gpio115"; 3216 function = "cci_i2c"; 3217 drive-strength = <2>; 3218 bias-pull-up; 3219 }; 3220 3221 cci2_sleep: cci2-sleep-state { 3222 /* SDA, SCL */ 3223 pins = "gpio114", "gpio115"; 3224 function = "cci_i2c"; 3225 drive-strength = <2>; 3226 bias-pull-down; 3227 }; 3228 3229 cci3_default: cci3-default-state { 3230 /* SDA, SCL */ 3231 pins = "gpio208", "gpio209"; 3232 function = "cci_i2c"; 3233 drive-strength = <2>; 3234 bias-pull-up; 3235 }; 3236 3237 cci3_sleep: cci3-sleep-state { 3238 /* SDA, SCL */ 3239 pins = "gpio208", "gpio209"; 3240 function = "cci_i2c"; 3241 drive-strength = <2>; 3242 bias-pull-down; 3243 }; 3244 3245 pcie0_default_state: pcie0-default-state { 3246 perst-pins { 3247 pins = "gpio94"; 3248 function = "gpio"; 3249 drive-strength = <2>; 3250 bias-pull-down; 3251 }; 3252 3253 clkreq-pins { 3254 pins = "gpio95"; 3255 function = "pcie0_clkreqn"; 3256 drive-strength = <2>; 3257 bias-pull-up; 3258 }; 3259 3260 wake-pins { 3261 pins = "gpio96"; 3262 function = "gpio"; 3263 drive-strength = <2>; 3264 bias-pull-up; 3265 }; 3266 }; 3267 3268 pcie1_default_state: pcie1-default-state { 3269 perst-pins { 3270 pins = "gpio97"; 3271 function = "gpio"; 3272 drive-strength = <2>; 3273 bias-pull-down; 3274 }; 3275 3276 clkreq-pins { 3277 pins = "gpio98"; 3278 function = "pcie1_clkreqn"; 3279 drive-strength = <2>; 3280 bias-pull-up; 3281 }; 3282 3283 wake-pins { 3284 pins = "gpio99"; 3285 function = "gpio"; 3286 drive-strength = <2>; 3287 bias-pull-up; 3288 }; 3289 }; 3290 3291 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3292 pins = "gpio0", "gpio1"; 3293 function = "qup0"; 3294 }; 3295 3296 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3297 pins = "gpio4", "gpio5"; 3298 function = "qup1"; 3299 }; 3300 3301 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3302 pins = "gpio8", "gpio9"; 3303 function = "qup2"; 3304 }; 3305 3306 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3307 pins = "gpio12", "gpio13"; 3308 function = "qup3"; 3309 }; 3310 3311 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3312 pins = "gpio16", "gpio17"; 3313 function = "qup4"; 3314 }; 3315 3316 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3317 pins = "gpio206", "gpio207"; 3318 function = "qup5"; 3319 }; 3320 3321 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3322 pins = "gpio20", "gpio21"; 3323 function = "qup6"; 3324 }; 3325 3326 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3327 pins = "gpio28", "gpio29"; 3328 function = "qup8"; 3329 }; 3330 3331 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3332 pins = "gpio32", "gpio33"; 3333 function = "qup9"; 3334 }; 3335 3336 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3337 pins = "gpio36", "gpio37"; 3338 function = "qup10"; 3339 }; 3340 3341 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3342 pins = "gpio40", "gpio41"; 3343 function = "qup11"; 3344 }; 3345 3346 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3347 pins = "gpio44", "gpio45"; 3348 function = "qup12"; 3349 }; 3350 3351 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3352 pins = "gpio48", "gpio49"; 3353 function = "qup13"; 3354 drive-strength = <2>; 3355 bias-pull-up; 3356 }; 3357 3358 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3359 pins = "gpio52", "gpio53"; 3360 function = "qup14"; 3361 drive-strength = <2>; 3362 bias-pull-up; 3363 }; 3364 3365 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3366 pins = "gpio56", "gpio57"; 3367 function = "qup15"; 3368 }; 3369 3370 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3371 pins = "gpio60", "gpio61"; 3372 function = "qup16"; 3373 }; 3374 3375 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3376 pins = "gpio64", "gpio65"; 3377 function = "qup17"; 3378 }; 3379 3380 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3381 pins = "gpio68", "gpio69"; 3382 function = "qup18"; 3383 }; 3384 3385 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3386 pins = "gpio72", "gpio73"; 3387 function = "qup19"; 3388 }; 3389 3390 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3391 pins = "gpio76", "gpio77"; 3392 function = "qup20"; 3393 }; 3394 3395 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3396 pins = "gpio80", "gpio81"; 3397 function = "qup21"; 3398 }; 3399 3400 qup_spi0_cs: qup-spi0-cs-state { 3401 pins = "gpio3"; 3402 function = "qup0"; 3403 }; 3404 3405 qup_spi0_data_clk: qup-spi0-data-clk-state { 3406 pins = "gpio0", "gpio1", "gpio2"; 3407 function = "qup0"; 3408 }; 3409 3410 qup_spi1_cs: qup-spi1-cs-state { 3411 pins = "gpio7"; 3412 function = "qup1"; 3413 }; 3414 3415 qup_spi1_data_clk: qup-spi1-data-clk-state { 3416 pins = "gpio4", "gpio5", "gpio6"; 3417 function = "qup1"; 3418 }; 3419 3420 qup_spi2_cs: qup-spi2-cs-state { 3421 pins = "gpio11"; 3422 function = "qup2"; 3423 }; 3424 3425 qup_spi2_data_clk: qup-spi2-data-clk-state { 3426 pins = "gpio8", "gpio9", "gpio10"; 3427 function = "qup2"; 3428 }; 3429 3430 qup_spi3_cs: qup-spi3-cs-state { 3431 pins = "gpio15"; 3432 function = "qup3"; 3433 }; 3434 3435 qup_spi3_data_clk: qup-spi3-data-clk-state { 3436 pins = "gpio12", "gpio13", "gpio14"; 3437 function = "qup3"; 3438 }; 3439 3440 qup_spi4_cs: qup-spi4-cs-state { 3441 pins = "gpio19"; 3442 function = "qup4"; 3443 drive-strength = <6>; 3444 bias-disable; 3445 }; 3446 3447 qup_spi4_data_clk: qup-spi4-data-clk-state { 3448 pins = "gpio16", "gpio17", "gpio18"; 3449 function = "qup4"; 3450 }; 3451 3452 qup_spi5_cs: qup-spi5-cs-state { 3453 pins = "gpio85"; 3454 function = "qup5"; 3455 }; 3456 3457 qup_spi5_data_clk: qup-spi5-data-clk-state { 3458 pins = "gpio206", "gpio207", "gpio84"; 3459 function = "qup5"; 3460 }; 3461 3462 qup_spi6_cs: qup-spi6-cs-state { 3463 pins = "gpio23"; 3464 function = "qup6"; 3465 }; 3466 3467 qup_spi6_data_clk: qup-spi6-data-clk-state { 3468 pins = "gpio20", "gpio21", "gpio22"; 3469 function = "qup6"; 3470 }; 3471 3472 qup_spi8_cs: qup-spi8-cs-state { 3473 pins = "gpio31"; 3474 function = "qup8"; 3475 }; 3476 3477 qup_spi8_data_clk: qup-spi8-data-clk-state { 3478 pins = "gpio28", "gpio29", "gpio30"; 3479 function = "qup8"; 3480 }; 3481 3482 qup_spi9_cs: qup-spi9-cs-state { 3483 pins = "gpio35"; 3484 function = "qup9"; 3485 }; 3486 3487 qup_spi9_data_clk: qup-spi9-data-clk-state { 3488 pins = "gpio32", "gpio33", "gpio34"; 3489 function = "qup9"; 3490 }; 3491 3492 qup_spi10_cs: qup-spi10-cs-state { 3493 pins = "gpio39"; 3494 function = "qup10"; 3495 }; 3496 3497 qup_spi10_data_clk: qup-spi10-data-clk-state { 3498 pins = "gpio36", "gpio37", "gpio38"; 3499 function = "qup10"; 3500 }; 3501 3502 qup_spi11_cs: qup-spi11-cs-state { 3503 pins = "gpio43"; 3504 function = "qup11"; 3505 }; 3506 3507 qup_spi11_data_clk: qup-spi11-data-clk-state { 3508 pins = "gpio40", "gpio41", "gpio42"; 3509 function = "qup11"; 3510 }; 3511 3512 qup_spi12_cs: qup-spi12-cs-state { 3513 pins = "gpio47"; 3514 function = "qup12"; 3515 }; 3516 3517 qup_spi12_data_clk: qup-spi12-data-clk-state { 3518 pins = "gpio44", "gpio45", "gpio46"; 3519 function = "qup12"; 3520 }; 3521 3522 qup_spi13_cs: qup-spi13-cs-state { 3523 pins = "gpio51"; 3524 function = "qup13"; 3525 }; 3526 3527 qup_spi13_data_clk: qup-spi13-data-clk-state { 3528 pins = "gpio48", "gpio49", "gpio50"; 3529 function = "qup13"; 3530 }; 3531 3532 qup_spi14_cs: qup-spi14-cs-state { 3533 pins = "gpio55"; 3534 function = "qup14"; 3535 }; 3536 3537 qup_spi14_data_clk: qup-spi14-data-clk-state { 3538 pins = "gpio52", "gpio53", "gpio54"; 3539 function = "qup14"; 3540 }; 3541 3542 qup_spi15_cs: qup-spi15-cs-state { 3543 pins = "gpio59"; 3544 function = "qup15"; 3545 }; 3546 3547 qup_spi15_data_clk: qup-spi15-data-clk-state { 3548 pins = "gpio56", "gpio57", "gpio58"; 3549 function = "qup15"; 3550 }; 3551 3552 qup_spi16_cs: qup-spi16-cs-state { 3553 pins = "gpio63"; 3554 function = "qup16"; 3555 }; 3556 3557 qup_spi16_data_clk: qup-spi16-data-clk-state { 3558 pins = "gpio60", "gpio61", "gpio62"; 3559 function = "qup16"; 3560 }; 3561 3562 qup_spi17_cs: qup-spi17-cs-state { 3563 pins = "gpio67"; 3564 function = "qup17"; 3565 }; 3566 3567 qup_spi17_data_clk: qup-spi17-data-clk-state { 3568 pins = "gpio64", "gpio65", "gpio66"; 3569 function = "qup17"; 3570 }; 3571 3572 qup_spi18_cs: qup-spi18-cs-state { 3573 pins = "gpio71"; 3574 function = "qup18"; 3575 drive-strength = <6>; 3576 bias-disable; 3577 }; 3578 3579 qup_spi18_data_clk: qup-spi18-data-clk-state { 3580 pins = "gpio68", "gpio69", "gpio70"; 3581 function = "qup18"; 3582 drive-strength = <6>; 3583 bias-disable; 3584 }; 3585 3586 qup_spi19_cs: qup-spi19-cs-state { 3587 pins = "gpio75"; 3588 function = "qup19"; 3589 drive-strength = <6>; 3590 bias-disable; 3591 }; 3592 3593 qup_spi19_data_clk: qup-spi19-data-clk-state { 3594 pins = "gpio72", "gpio73", "gpio74"; 3595 function = "qup19"; 3596 drive-strength = <6>; 3597 bias-disable; 3598 }; 3599 3600 qup_spi20_cs: qup-spi20-cs-state { 3601 pins = "gpio79"; 3602 function = "qup20"; 3603 }; 3604 3605 qup_spi20_data_clk: qup-spi20-data-clk-state { 3606 pins = "gpio76", "gpio77", "gpio78"; 3607 function = "qup20"; 3608 }; 3609 3610 qup_spi21_cs: qup-spi21-cs-state { 3611 pins = "gpio83"; 3612 function = "qup21"; 3613 }; 3614 3615 qup_spi21_data_clk: qup-spi21-data-clk-state { 3616 pins = "gpio80", "gpio81", "gpio82"; 3617 function = "qup21"; 3618 }; 3619 3620 qup_uart7_rx: qup-uart7-rx-state { 3621 pins = "gpio26"; 3622 function = "qup7"; 3623 drive-strength = <2>; 3624 bias-disable; 3625 }; 3626 3627 qup_uart7_tx: qup-uart7-tx-state { 3628 pins = "gpio27"; 3629 function = "qup7"; 3630 drive-strength = <2>; 3631 bias-disable; 3632 }; 3633 3634 qup_uart20_default: qup-uart20-default-state { 3635 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3636 function = "qup20"; 3637 }; 3638 }; 3639 3640 lpass_tlmm: pinctrl@3440000 { 3641 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3642 reg = <0 0x03440000 0x0 0x20000>, 3643 <0 0x034d0000 0x0 0x10000>; 3644 gpio-controller; 3645 #gpio-cells = <2>; 3646 gpio-ranges = <&lpass_tlmm 0 0 23>; 3647 3648 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3649 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3650 clock-names = "core", "audio"; 3651 3652 tx_swr_active: tx-swr-active-state { 3653 clk-pins { 3654 pins = "gpio0"; 3655 function = "swr_tx_clk"; 3656 drive-strength = <2>; 3657 slew-rate = <1>; 3658 bias-disable; 3659 }; 3660 3661 data-pins { 3662 pins = "gpio1", "gpio2", "gpio14"; 3663 function = "swr_tx_data"; 3664 drive-strength = <2>; 3665 slew-rate = <1>; 3666 bias-bus-hold; 3667 }; 3668 }; 3669 3670 rx_swr_active: rx-swr-active-state { 3671 clk-pins { 3672 pins = "gpio3"; 3673 function = "swr_rx_clk"; 3674 drive-strength = <2>; 3675 slew-rate = <1>; 3676 bias-disable; 3677 }; 3678 3679 data-pins { 3680 pins = "gpio4", "gpio5"; 3681 function = "swr_rx_data"; 3682 drive-strength = <2>; 3683 slew-rate = <1>; 3684 bias-bus-hold; 3685 }; 3686 }; 3687 3688 dmic01_default: dmic01-default-state { 3689 clk-pins { 3690 pins = "gpio6"; 3691 function = "dmic1_clk"; 3692 drive-strength = <8>; 3693 output-high; 3694 }; 3695 3696 data-pins { 3697 pins = "gpio7"; 3698 function = "dmic1_data"; 3699 drive-strength = <8>; 3700 }; 3701 }; 3702 3703 dmic02_default: dmic02-default-state { 3704 clk-pins { 3705 pins = "gpio8"; 3706 function = "dmic2_clk"; 3707 drive-strength = <8>; 3708 output-high; 3709 }; 3710 3711 data-pins { 3712 pins = "gpio9"; 3713 function = "dmic2_data"; 3714 drive-strength = <8>; 3715 }; 3716 }; 3717 3718 wsa_swr_active: wsa-swr-active-state { 3719 clk-pins { 3720 pins = "gpio10"; 3721 function = "wsa_swr_clk"; 3722 drive-strength = <2>; 3723 slew-rate = <1>; 3724 bias-disable; 3725 }; 3726 3727 data-pins { 3728 pins = "gpio11"; 3729 function = "wsa_swr_data"; 3730 drive-strength = <2>; 3731 slew-rate = <1>; 3732 bias-bus-hold; 3733 }; 3734 }; 3735 3736 wsa2_swr_active: wsa2-swr-active-state { 3737 clk-pins { 3738 pins = "gpio15"; 3739 function = "wsa2_swr_clk"; 3740 drive-strength = <2>; 3741 slew-rate = <1>; 3742 bias-disable; 3743 }; 3744 3745 data-pins { 3746 pins = "gpio16"; 3747 function = "wsa2_swr_data"; 3748 drive-strength = <2>; 3749 slew-rate = <1>; 3750 bias-bus-hold; 3751 }; 3752 }; 3753 }; 3754 3755 sram@146aa000 { 3756 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 3757 reg = <0 0x146aa000 0 0x1000>; 3758 ranges = <0 0 0x146aa000 0x1000>; 3759 3760 #address-cells = <1>; 3761 #size-cells = <1>; 3762 3763 pil-reloc@94c { 3764 compatible = "qcom,pil-reloc-info"; 3765 reg = <0x94c 0xc8>; 3766 }; 3767 }; 3768 3769 apps_smmu: iommu@15000000 { 3770 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3771 reg = <0 0x15000000 0 0x100000>; 3772 #iommu-cells = <2>; 3773 #global-interrupts = <1>; 3774 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3871 }; 3872 3873 intc: interrupt-controller@17100000 { 3874 compatible = "arm,gic-v3"; 3875 #interrupt-cells = <3>; 3876 interrupt-controller; 3877 #redistributor-regions = <1>; 3878 redistributor-stride = <0x0 0x40000>; 3879 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3880 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3881 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3882 #address-cells = <2>; 3883 #size-cells = <2>; 3884 ranges; 3885 3886 gic_its: msi-controller@17140000 { 3887 compatible = "arm,gic-v3-its"; 3888 reg = <0x0 0x17140000 0x0 0x20000>; 3889 msi-controller; 3890 #msi-cells = <1>; 3891 }; 3892 }; 3893 3894 timer@17420000 { 3895 compatible = "arm,armv7-timer-mem"; 3896 #address-cells = <1>; 3897 #size-cells = <1>; 3898 ranges = <0 0 0 0x20000000>; 3899 reg = <0x0 0x17420000 0x0 0x1000>; 3900 clock-frequency = <19200000>; 3901 3902 frame@17421000 { 3903 frame-number = <0>; 3904 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3906 reg = <0x17421000 0x1000>, 3907 <0x17422000 0x1000>; 3908 }; 3909 3910 frame@17423000 { 3911 frame-number = <1>; 3912 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3913 reg = <0x17423000 0x1000>; 3914 status = "disabled"; 3915 }; 3916 3917 frame@17425000 { 3918 frame-number = <2>; 3919 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3920 reg = <0x17425000 0x1000>; 3921 status = "disabled"; 3922 }; 3923 3924 frame@17427000 { 3925 frame-number = <3>; 3926 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3927 reg = <0x17427000 0x1000>; 3928 status = "disabled"; 3929 }; 3930 3931 frame@17429000 { 3932 frame-number = <4>; 3933 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3934 reg = <0x17429000 0x1000>; 3935 status = "disabled"; 3936 }; 3937 3938 frame@1742b000 { 3939 frame-number = <5>; 3940 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3941 reg = <0x1742b000 0x1000>; 3942 status = "disabled"; 3943 }; 3944 3945 frame@1742d000 { 3946 frame-number = <6>; 3947 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3948 reg = <0x1742d000 0x1000>; 3949 status = "disabled"; 3950 }; 3951 }; 3952 3953 apps_rsc: rsc@17a00000 { 3954 label = "apps_rsc"; 3955 compatible = "qcom,rpmh-rsc"; 3956 reg = <0x0 0x17a00000 0x0 0x10000>, 3957 <0x0 0x17a10000 0x0 0x10000>, 3958 <0x0 0x17a20000 0x0 0x10000>, 3959 <0x0 0x17a30000 0x0 0x10000>; 3960 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3961 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3964 qcom,tcs-offset = <0xd00>; 3965 qcom,drv-id = <2>; 3966 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3967 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3968 power-domains = <&CLUSTER_PD>; 3969 3970 apps_bcm_voter: bcm-voter { 3971 compatible = "qcom,bcm-voter"; 3972 }; 3973 3974 rpmhcc: clock-controller { 3975 compatible = "qcom,sm8450-rpmh-clk"; 3976 #clock-cells = <1>; 3977 clock-names = "xo"; 3978 clocks = <&xo_board>; 3979 }; 3980 3981 rpmhpd: power-controller { 3982 compatible = "qcom,sm8450-rpmhpd"; 3983 #power-domain-cells = <1>; 3984 operating-points-v2 = <&rpmhpd_opp_table>; 3985 3986 rpmhpd_opp_table: opp-table { 3987 compatible = "operating-points-v2"; 3988 3989 rpmhpd_opp_ret: opp1 { 3990 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3991 }; 3992 3993 rpmhpd_opp_min_svs: opp2 { 3994 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3995 }; 3996 3997 rpmhpd_opp_low_svs_d1: opp3 { 3998 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3999 }; 4000 4001 rpmhpd_opp_low_svs: opp4 { 4002 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4003 }; 4004 4005 rpmhpd_opp_svs: opp5 { 4006 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4007 }; 4008 4009 rpmhpd_opp_svs_l1: opp6 { 4010 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4011 }; 4012 4013 rpmhpd_opp_nom: opp7 { 4014 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4015 }; 4016 4017 rpmhpd_opp_nom_l1: opp8 { 4018 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4019 }; 4020 4021 rpmhpd_opp_nom_l2: opp9 { 4022 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4023 }; 4024 4025 rpmhpd_opp_turbo: opp10 { 4026 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4027 }; 4028 4029 rpmhpd_opp_turbo_l1: opp11 { 4030 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4031 }; 4032 }; 4033 }; 4034 }; 4035 4036 cpufreq_hw: cpufreq@17d91000 { 4037 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4038 reg = <0 0x17d91000 0 0x1000>, 4039 <0 0x17d92000 0 0x1000>, 4040 <0 0x17d93000 0 0x1000>; 4041 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4042 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4043 clock-names = "xo", "alternate"; 4044 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4047 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4048 #freq-domain-cells = <1>; 4049 #clock-cells = <1>; 4050 }; 4051 4052 gem_noc: interconnect@19100000 { 4053 compatible = "qcom,sm8450-gem-noc"; 4054 reg = <0 0x19100000 0 0xbb800>; 4055 #interconnect-cells = <2>; 4056 qcom,bcm-voters = <&apps_bcm_voter>; 4057 }; 4058 4059 system-cache-controller@19200000 { 4060 compatible = "qcom,sm8450-llcc"; 4061 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4062 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4063 <0 0x19a00000 0 0x80000>; 4064 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4065 "llcc3_base", "llcc_broadcast_base"; 4066 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4067 }; 4068 4069 ufs_mem_hc: ufshc@1d84000 { 4070 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4071 "jedec,ufs-2.0"; 4072 reg = <0 0x01d84000 0 0x3000>, 4073 <0 0x01d88000 0 0x8000>; 4074 reg-names = "std", "ice"; 4075 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4076 phys = <&ufs_mem_phy_lanes>; 4077 phy-names = "ufsphy"; 4078 lanes-per-direction = <2>; 4079 #reset-cells = <1>; 4080 resets = <&gcc GCC_UFS_PHY_BCR>; 4081 reset-names = "rst"; 4082 4083 power-domains = <&gcc UFS_PHY_GDSC>; 4084 4085 iommus = <&apps_smmu 0xe0 0x0>; 4086 dma-coherent; 4087 4088 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4089 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4090 interconnect-names = "ufs-ddr", "cpu-ufs"; 4091 clock-names = 4092 "core_clk", 4093 "bus_aggr_clk", 4094 "iface_clk", 4095 "core_clk_unipro", 4096 "ref_clk", 4097 "tx_lane0_sync_clk", 4098 "rx_lane0_sync_clk", 4099 "rx_lane1_sync_clk", 4100 "ice_core_clk"; 4101 clocks = 4102 <&gcc GCC_UFS_PHY_AXI_CLK>, 4103 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4104 <&gcc GCC_UFS_PHY_AHB_CLK>, 4105 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4106 <&rpmhcc RPMH_CXO_CLK>, 4107 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4108 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4109 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 4110 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4111 freq-table-hz = 4112 <75000000 300000000>, 4113 <0 0>, 4114 <0 0>, 4115 <75000000 300000000>, 4116 <75000000 300000000>, 4117 <0 0>, 4118 <0 0>, 4119 <0 0>, 4120 <75000000 300000000>; 4121 status = "disabled"; 4122 }; 4123 4124 ufs_mem_phy: phy@1d87000 { 4125 compatible = "qcom,sm8450-qmp-ufs-phy"; 4126 reg = <0 0x01d87000 0 0x1c4>; 4127 #address-cells = <2>; 4128 #size-cells = <2>; 4129 ranges; 4130 clock-names = "ref", "ref_aux", "qref"; 4131 clocks = <&rpmhcc RPMH_CXO_CLK>, 4132 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4133 <&gcc GCC_UFS_0_CLKREF_EN>; 4134 4135 resets = <&ufs_mem_hc 0>; 4136 reset-names = "ufsphy"; 4137 status = "disabled"; 4138 4139 ufs_mem_phy_lanes: phy@1d87400 { 4140 reg = <0 0x01d87400 0 0x188>, 4141 <0 0x01d87600 0 0x200>, 4142 <0 0x01d87c00 0 0x200>, 4143 <0 0x01d87800 0 0x188>, 4144 <0 0x01d87a00 0 0x200>; 4145 #clock-cells = <1>; 4146 #phy-cells = <0>; 4147 }; 4148 }; 4149 4150 sdhc_2: mmc@8804000 { 4151 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4152 reg = <0 0x08804000 0 0x1000>; 4153 4154 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4156 interrupt-names = "hc_irq", "pwr_irq"; 4157 4158 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4159 <&gcc GCC_SDCC2_APPS_CLK>, 4160 <&rpmhcc RPMH_CXO_CLK>; 4161 clock-names = "iface", "core", "xo"; 4162 resets = <&gcc GCC_SDCC2_BCR>; 4163 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4165 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4166 iommus = <&apps_smmu 0x4a0 0x0>; 4167 power-domains = <&rpmhpd SM8450_CX>; 4168 operating-points-v2 = <&sdhc2_opp_table>; 4169 bus-width = <4>; 4170 dma-coherent; 4171 4172 /* Forbid SDR104/SDR50 - broken hw! */ 4173 sdhci-caps-mask = <0x3 0x0>; 4174 4175 status = "disabled"; 4176 4177 sdhc2_opp_table: opp-table { 4178 compatible = "operating-points-v2"; 4179 4180 opp-100000000 { 4181 opp-hz = /bits/ 64 <100000000>; 4182 required-opps = <&rpmhpd_opp_low_svs>; 4183 }; 4184 4185 opp-202000000 { 4186 opp-hz = /bits/ 64 <202000000>; 4187 required-opps = <&rpmhpd_opp_svs_l1>; 4188 }; 4189 }; 4190 }; 4191 4192 usb_1: usb@a6f8800 { 4193 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4194 reg = <0 0x0a6f8800 0 0x400>; 4195 status = "disabled"; 4196 #address-cells = <2>; 4197 #size-cells = <2>; 4198 ranges; 4199 4200 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4201 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4202 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4203 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4204 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4205 <&gcc GCC_USB3_0_CLKREF_EN>; 4206 clock-names = "cfg_noc", 4207 "core", 4208 "iface", 4209 "sleep", 4210 "mock_utmi", 4211 "xo"; 4212 4213 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4214 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4215 assigned-clock-rates = <19200000>, <200000000>; 4216 4217 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4218 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4219 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4220 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4221 interrupt-names = "hs_phy_irq", 4222 "ss_phy_irq", 4223 "dm_hs_phy_irq", 4224 "dp_hs_phy_irq"; 4225 4226 power-domains = <&gcc USB30_PRIM_GDSC>; 4227 4228 resets = <&gcc GCC_USB30_PRIM_BCR>; 4229 4230 usb_1_dwc3: usb@a600000 { 4231 compatible = "snps,dwc3"; 4232 reg = <0 0x0a600000 0 0xcd00>; 4233 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4234 iommus = <&apps_smmu 0x0 0x0>; 4235 snps,dis_u2_susphy_quirk; 4236 snps,dis_enblslpm_quirk; 4237 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4238 phy-names = "usb2-phy", "usb3-phy"; 4239 4240 ports { 4241 #address-cells = <1>; 4242 #size-cells = <0>; 4243 4244 port@0 { 4245 reg = <0>; 4246 4247 usb_1_dwc3_hs: endpoint { 4248 }; 4249 }; 4250 4251 port@1 { 4252 reg = <1>; 4253 4254 usb_1_dwc3_ss: endpoint { 4255 }; 4256 }; 4257 }; 4258 }; 4259 }; 4260 4261 nsp_noc: interconnect@320c0000 { 4262 compatible = "qcom,sm8450-nsp-noc"; 4263 reg = <0 0x320c0000 0 0x10000>; 4264 #interconnect-cells = <2>; 4265 qcom,bcm-voters = <&apps_bcm_voter>; 4266 }; 4267 4268 lpass_ag_noc: interconnect@3c40000 { 4269 compatible = "qcom,sm8450-lpass-ag-noc"; 4270 reg = <0 0x03c40000 0 0x17200>; 4271 #interconnect-cells = <2>; 4272 qcom,bcm-voters = <&apps_bcm_voter>; 4273 }; 4274 }; 4275 4276 sound: sound { 4277 }; 4278 4279 thermal-zones { 4280 aoss0-thermal { 4281 polling-delay-passive = <0>; 4282 polling-delay = <0>; 4283 thermal-sensors = <&tsens0 0>; 4284 4285 trips { 4286 thermal-engine-config { 4287 temperature = <125000>; 4288 hysteresis = <1000>; 4289 type = "passive"; 4290 }; 4291 4292 reset-mon-cfg { 4293 temperature = <115000>; 4294 hysteresis = <5000>; 4295 type = "passive"; 4296 }; 4297 }; 4298 }; 4299 4300 cpuss0-thermal { 4301 polling-delay-passive = <0>; 4302 polling-delay = <0>; 4303 thermal-sensors = <&tsens0 1>; 4304 4305 trips { 4306 thermal-engine-config { 4307 temperature = <125000>; 4308 hysteresis = <1000>; 4309 type = "passive"; 4310 }; 4311 4312 reset-mon-cfg { 4313 temperature = <115000>; 4314 hysteresis = <5000>; 4315 type = "passive"; 4316 }; 4317 }; 4318 }; 4319 4320 cpuss1-thermal { 4321 polling-delay-passive = <0>; 4322 polling-delay = <0>; 4323 thermal-sensors = <&tsens0 2>; 4324 4325 trips { 4326 thermal-engine-config { 4327 temperature = <125000>; 4328 hysteresis = <1000>; 4329 type = "passive"; 4330 }; 4331 4332 reset-mon-cfg { 4333 temperature = <115000>; 4334 hysteresis = <5000>; 4335 type = "passive"; 4336 }; 4337 }; 4338 }; 4339 4340 cpuss3-thermal { 4341 polling-delay-passive = <0>; 4342 polling-delay = <0>; 4343 thermal-sensors = <&tsens0 3>; 4344 4345 trips { 4346 thermal-engine-config { 4347 temperature = <125000>; 4348 hysteresis = <1000>; 4349 type = "passive"; 4350 }; 4351 4352 reset-mon-cfg { 4353 temperature = <115000>; 4354 hysteresis = <5000>; 4355 type = "passive"; 4356 }; 4357 }; 4358 }; 4359 4360 cpuss4-thermal { 4361 polling-delay-passive = <0>; 4362 polling-delay = <0>; 4363 thermal-sensors = <&tsens0 4>; 4364 4365 trips { 4366 thermal-engine-config { 4367 temperature = <125000>; 4368 hysteresis = <1000>; 4369 type = "passive"; 4370 }; 4371 4372 reset-mon-cfg { 4373 temperature = <115000>; 4374 hysteresis = <5000>; 4375 type = "passive"; 4376 }; 4377 }; 4378 }; 4379 4380 cpu4-top-thermal { 4381 polling-delay-passive = <0>; 4382 polling-delay = <0>; 4383 thermal-sensors = <&tsens0 5>; 4384 4385 trips { 4386 cpu4_top_alert0: trip-point0 { 4387 temperature = <90000>; 4388 hysteresis = <2000>; 4389 type = "passive"; 4390 }; 4391 4392 cpu4_top_alert1: trip-point1 { 4393 temperature = <95000>; 4394 hysteresis = <2000>; 4395 type = "passive"; 4396 }; 4397 4398 cpu4_top_crit: cpu-crit { 4399 temperature = <110000>; 4400 hysteresis = <1000>; 4401 type = "critical"; 4402 }; 4403 }; 4404 }; 4405 4406 cpu4-bottom-thermal { 4407 polling-delay-passive = <0>; 4408 polling-delay = <0>; 4409 thermal-sensors = <&tsens0 6>; 4410 4411 trips { 4412 cpu4_bottom_alert0: trip-point0 { 4413 temperature = <90000>; 4414 hysteresis = <2000>; 4415 type = "passive"; 4416 }; 4417 4418 cpu4_bottom_alert1: trip-point1 { 4419 temperature = <95000>; 4420 hysteresis = <2000>; 4421 type = "passive"; 4422 }; 4423 4424 cpu4_bottom_crit: cpu-crit { 4425 temperature = <110000>; 4426 hysteresis = <1000>; 4427 type = "critical"; 4428 }; 4429 }; 4430 }; 4431 4432 cpu5-top-thermal { 4433 polling-delay-passive = <0>; 4434 polling-delay = <0>; 4435 thermal-sensors = <&tsens0 7>; 4436 4437 trips { 4438 cpu5_top_alert0: trip-point0 { 4439 temperature = <90000>; 4440 hysteresis = <2000>; 4441 type = "passive"; 4442 }; 4443 4444 cpu5_top_alert1: trip-point1 { 4445 temperature = <95000>; 4446 hysteresis = <2000>; 4447 type = "passive"; 4448 }; 4449 4450 cpu5_top_crit: cpu-crit { 4451 temperature = <110000>; 4452 hysteresis = <1000>; 4453 type = "critical"; 4454 }; 4455 }; 4456 }; 4457 4458 cpu5-bottom-thermal { 4459 polling-delay-passive = <0>; 4460 polling-delay = <0>; 4461 thermal-sensors = <&tsens0 8>; 4462 4463 trips { 4464 cpu5_bottom_alert0: trip-point0 { 4465 temperature = <90000>; 4466 hysteresis = <2000>; 4467 type = "passive"; 4468 }; 4469 4470 cpu5_bottom_alert1: trip-point1 { 4471 temperature = <95000>; 4472 hysteresis = <2000>; 4473 type = "passive"; 4474 }; 4475 4476 cpu5_bottom_crit: cpu-crit { 4477 temperature = <110000>; 4478 hysteresis = <1000>; 4479 type = "critical"; 4480 }; 4481 }; 4482 }; 4483 4484 cpu6-top-thermal { 4485 polling-delay-passive = <0>; 4486 polling-delay = <0>; 4487 thermal-sensors = <&tsens0 9>; 4488 4489 trips { 4490 cpu6_top_alert0: trip-point0 { 4491 temperature = <90000>; 4492 hysteresis = <2000>; 4493 type = "passive"; 4494 }; 4495 4496 cpu6_top_alert1: trip-point1 { 4497 temperature = <95000>; 4498 hysteresis = <2000>; 4499 type = "passive"; 4500 }; 4501 4502 cpu6_top_crit: cpu-crit { 4503 temperature = <110000>; 4504 hysteresis = <1000>; 4505 type = "critical"; 4506 }; 4507 }; 4508 }; 4509 4510 cpu6-bottom-thermal { 4511 polling-delay-passive = <0>; 4512 polling-delay = <0>; 4513 thermal-sensors = <&tsens0 10>; 4514 4515 trips { 4516 cpu6_bottom_alert0: trip-point0 { 4517 temperature = <90000>; 4518 hysteresis = <2000>; 4519 type = "passive"; 4520 }; 4521 4522 cpu6_bottom_alert1: trip-point1 { 4523 temperature = <95000>; 4524 hysteresis = <2000>; 4525 type = "passive"; 4526 }; 4527 4528 cpu6_bottom_crit: cpu-crit { 4529 temperature = <110000>; 4530 hysteresis = <1000>; 4531 type = "critical"; 4532 }; 4533 }; 4534 }; 4535 4536 cpu7-top-thermal { 4537 polling-delay-passive = <0>; 4538 polling-delay = <0>; 4539 thermal-sensors = <&tsens0 11>; 4540 4541 trips { 4542 cpu7_top_alert0: trip-point0 { 4543 temperature = <90000>; 4544 hysteresis = <2000>; 4545 type = "passive"; 4546 }; 4547 4548 cpu7_top_alert1: trip-point1 { 4549 temperature = <95000>; 4550 hysteresis = <2000>; 4551 type = "passive"; 4552 }; 4553 4554 cpu7_top_crit: cpu-crit { 4555 temperature = <110000>; 4556 hysteresis = <1000>; 4557 type = "critical"; 4558 }; 4559 }; 4560 }; 4561 4562 cpu7-middle-thermal { 4563 polling-delay-passive = <0>; 4564 polling-delay = <0>; 4565 thermal-sensors = <&tsens0 12>; 4566 4567 trips { 4568 cpu7_middle_alert0: trip-point0 { 4569 temperature = <90000>; 4570 hysteresis = <2000>; 4571 type = "passive"; 4572 }; 4573 4574 cpu7_middle_alert1: trip-point1 { 4575 temperature = <95000>; 4576 hysteresis = <2000>; 4577 type = "passive"; 4578 }; 4579 4580 cpu7_middle_crit: cpu-crit { 4581 temperature = <110000>; 4582 hysteresis = <1000>; 4583 type = "critical"; 4584 }; 4585 }; 4586 }; 4587 4588 cpu7-bottom-thermal { 4589 polling-delay-passive = <0>; 4590 polling-delay = <0>; 4591 thermal-sensors = <&tsens0 13>; 4592 4593 trips { 4594 cpu7_bottom_alert0: trip-point0 { 4595 temperature = <90000>; 4596 hysteresis = <2000>; 4597 type = "passive"; 4598 }; 4599 4600 cpu7_bottom_alert1: trip-point1 { 4601 temperature = <95000>; 4602 hysteresis = <2000>; 4603 type = "passive"; 4604 }; 4605 4606 cpu7_bottom_crit: cpu-crit { 4607 temperature = <110000>; 4608 hysteresis = <1000>; 4609 type = "critical"; 4610 }; 4611 }; 4612 }; 4613 4614 gpu-top-thermal { 4615 polling-delay-passive = <10>; 4616 polling-delay = <0>; 4617 thermal-sensors = <&tsens0 14>; 4618 4619 trips { 4620 thermal-engine-config { 4621 temperature = <125000>; 4622 hysteresis = <1000>; 4623 type = "passive"; 4624 }; 4625 4626 thermal-hal-config { 4627 temperature = <125000>; 4628 hysteresis = <1000>; 4629 type = "passive"; 4630 }; 4631 4632 reset-mon-cfg { 4633 temperature = <115000>; 4634 hysteresis = <5000>; 4635 type = "passive"; 4636 }; 4637 4638 gpu0_tj_cfg: tj-cfg { 4639 temperature = <95000>; 4640 hysteresis = <5000>; 4641 type = "passive"; 4642 }; 4643 }; 4644 }; 4645 4646 gpu-bottom-thermal { 4647 polling-delay-passive = <10>; 4648 polling-delay = <0>; 4649 thermal-sensors = <&tsens0 15>; 4650 4651 trips { 4652 thermal-engine-config { 4653 temperature = <125000>; 4654 hysteresis = <1000>; 4655 type = "passive"; 4656 }; 4657 4658 thermal-hal-config { 4659 temperature = <125000>; 4660 hysteresis = <1000>; 4661 type = "passive"; 4662 }; 4663 4664 reset-mon-cfg { 4665 temperature = <115000>; 4666 hysteresis = <5000>; 4667 type = "passive"; 4668 }; 4669 4670 gpu1_tj_cfg: tj-cfg { 4671 temperature = <95000>; 4672 hysteresis = <5000>; 4673 type = "passive"; 4674 }; 4675 }; 4676 }; 4677 4678 aoss1-thermal { 4679 polling-delay-passive = <0>; 4680 polling-delay = <0>; 4681 thermal-sensors = <&tsens1 0>; 4682 4683 trips { 4684 thermal-engine-config { 4685 temperature = <125000>; 4686 hysteresis = <1000>; 4687 type = "passive"; 4688 }; 4689 4690 reset-mon-cfg { 4691 temperature = <115000>; 4692 hysteresis = <5000>; 4693 type = "passive"; 4694 }; 4695 }; 4696 }; 4697 4698 cpu0-thermal { 4699 polling-delay-passive = <0>; 4700 polling-delay = <0>; 4701 thermal-sensors = <&tsens1 1>; 4702 4703 trips { 4704 cpu0_alert0: trip-point0 { 4705 temperature = <90000>; 4706 hysteresis = <2000>; 4707 type = "passive"; 4708 }; 4709 4710 cpu0_alert1: trip-point1 { 4711 temperature = <95000>; 4712 hysteresis = <2000>; 4713 type = "passive"; 4714 }; 4715 4716 cpu0_crit: cpu-crit { 4717 temperature = <110000>; 4718 hysteresis = <1000>; 4719 type = "critical"; 4720 }; 4721 }; 4722 }; 4723 4724 cpu1-thermal { 4725 polling-delay-passive = <0>; 4726 polling-delay = <0>; 4727 thermal-sensors = <&tsens1 2>; 4728 4729 trips { 4730 cpu1_alert0: trip-point0 { 4731 temperature = <90000>; 4732 hysteresis = <2000>; 4733 type = "passive"; 4734 }; 4735 4736 cpu1_alert1: trip-point1 { 4737 temperature = <95000>; 4738 hysteresis = <2000>; 4739 type = "passive"; 4740 }; 4741 4742 cpu1_crit: cpu-crit { 4743 temperature = <110000>; 4744 hysteresis = <1000>; 4745 type = "critical"; 4746 }; 4747 }; 4748 }; 4749 4750 cpu2-thermal { 4751 polling-delay-passive = <0>; 4752 polling-delay = <0>; 4753 thermal-sensors = <&tsens1 3>; 4754 4755 trips { 4756 cpu2_alert0: trip-point0 { 4757 temperature = <90000>; 4758 hysteresis = <2000>; 4759 type = "passive"; 4760 }; 4761 4762 cpu2_alert1: trip-point1 { 4763 temperature = <95000>; 4764 hysteresis = <2000>; 4765 type = "passive"; 4766 }; 4767 4768 cpu2_crit: cpu-crit { 4769 temperature = <110000>; 4770 hysteresis = <1000>; 4771 type = "critical"; 4772 }; 4773 }; 4774 }; 4775 4776 cpu3-thermal { 4777 polling-delay-passive = <0>; 4778 polling-delay = <0>; 4779 thermal-sensors = <&tsens1 4>; 4780 4781 trips { 4782 cpu3_alert0: trip-point0 { 4783 temperature = <90000>; 4784 hysteresis = <2000>; 4785 type = "passive"; 4786 }; 4787 4788 cpu3_alert1: trip-point1 { 4789 temperature = <95000>; 4790 hysteresis = <2000>; 4791 type = "passive"; 4792 }; 4793 4794 cpu3_crit: cpu-crit { 4795 temperature = <110000>; 4796 hysteresis = <1000>; 4797 type = "critical"; 4798 }; 4799 }; 4800 }; 4801 4802 cdsp0-thermal { 4803 polling-delay-passive = <10>; 4804 polling-delay = <0>; 4805 thermal-sensors = <&tsens1 5>; 4806 4807 trips { 4808 thermal-engine-config { 4809 temperature = <125000>; 4810 hysteresis = <1000>; 4811 type = "passive"; 4812 }; 4813 4814 thermal-hal-config { 4815 temperature = <125000>; 4816 hysteresis = <1000>; 4817 type = "passive"; 4818 }; 4819 4820 reset-mon-cfg { 4821 temperature = <115000>; 4822 hysteresis = <5000>; 4823 type = "passive"; 4824 }; 4825 4826 cdsp_0_config: junction-config { 4827 temperature = <95000>; 4828 hysteresis = <5000>; 4829 type = "passive"; 4830 }; 4831 }; 4832 }; 4833 4834 cdsp1-thermal { 4835 polling-delay-passive = <10>; 4836 polling-delay = <0>; 4837 thermal-sensors = <&tsens1 6>; 4838 4839 trips { 4840 thermal-engine-config { 4841 temperature = <125000>; 4842 hysteresis = <1000>; 4843 type = "passive"; 4844 }; 4845 4846 thermal-hal-config { 4847 temperature = <125000>; 4848 hysteresis = <1000>; 4849 type = "passive"; 4850 }; 4851 4852 reset-mon-cfg { 4853 temperature = <115000>; 4854 hysteresis = <5000>; 4855 type = "passive"; 4856 }; 4857 4858 cdsp_1_config: junction-config { 4859 temperature = <95000>; 4860 hysteresis = <5000>; 4861 type = "passive"; 4862 }; 4863 }; 4864 }; 4865 4866 cdsp2-thermal { 4867 polling-delay-passive = <10>; 4868 polling-delay = <0>; 4869 thermal-sensors = <&tsens1 7>; 4870 4871 trips { 4872 thermal-engine-config { 4873 temperature = <125000>; 4874 hysteresis = <1000>; 4875 type = "passive"; 4876 }; 4877 4878 thermal-hal-config { 4879 temperature = <125000>; 4880 hysteresis = <1000>; 4881 type = "passive"; 4882 }; 4883 4884 reset-mon-cfg { 4885 temperature = <115000>; 4886 hysteresis = <5000>; 4887 type = "passive"; 4888 }; 4889 4890 cdsp_2_config: junction-config { 4891 temperature = <95000>; 4892 hysteresis = <5000>; 4893 type = "passive"; 4894 }; 4895 }; 4896 }; 4897 4898 video-thermal { 4899 polling-delay-passive = <0>; 4900 polling-delay = <0>; 4901 thermal-sensors = <&tsens1 8>; 4902 4903 trips { 4904 thermal-engine-config { 4905 temperature = <125000>; 4906 hysteresis = <1000>; 4907 type = "passive"; 4908 }; 4909 4910 reset-mon-cfg { 4911 temperature = <115000>; 4912 hysteresis = <5000>; 4913 type = "passive"; 4914 }; 4915 }; 4916 }; 4917 4918 mem-thermal { 4919 polling-delay-passive = <10>; 4920 polling-delay = <0>; 4921 thermal-sensors = <&tsens1 9>; 4922 4923 trips { 4924 thermal-engine-config { 4925 temperature = <125000>; 4926 hysteresis = <1000>; 4927 type = "passive"; 4928 }; 4929 4930 ddr_config0: ddr0-config { 4931 temperature = <90000>; 4932 hysteresis = <5000>; 4933 type = "passive"; 4934 }; 4935 4936 reset-mon-cfg { 4937 temperature = <115000>; 4938 hysteresis = <5000>; 4939 type = "passive"; 4940 }; 4941 }; 4942 }; 4943 4944 modem0-thermal { 4945 polling-delay-passive = <0>; 4946 polling-delay = <0>; 4947 thermal-sensors = <&tsens1 10>; 4948 4949 trips { 4950 thermal-engine-config { 4951 temperature = <125000>; 4952 hysteresis = <1000>; 4953 type = "passive"; 4954 }; 4955 4956 mdmss0_config0: mdmss0-config0 { 4957 temperature = <102000>; 4958 hysteresis = <3000>; 4959 type = "passive"; 4960 }; 4961 4962 mdmss0_config1: mdmss0-config1 { 4963 temperature = <105000>; 4964 hysteresis = <3000>; 4965 type = "passive"; 4966 }; 4967 4968 reset-mon-cfg { 4969 temperature = <115000>; 4970 hysteresis = <5000>; 4971 type = "passive"; 4972 }; 4973 }; 4974 }; 4975 4976 modem1-thermal { 4977 polling-delay-passive = <0>; 4978 polling-delay = <0>; 4979 thermal-sensors = <&tsens1 11>; 4980 4981 trips { 4982 thermal-engine-config { 4983 temperature = <125000>; 4984 hysteresis = <1000>; 4985 type = "passive"; 4986 }; 4987 4988 mdmss1_config0: mdmss1-config0 { 4989 temperature = <102000>; 4990 hysteresis = <3000>; 4991 type = "passive"; 4992 }; 4993 4994 mdmss1_config1: mdmss1-config1 { 4995 temperature = <105000>; 4996 hysteresis = <3000>; 4997 type = "passive"; 4998 }; 4999 5000 reset-mon-cfg { 5001 temperature = <115000>; 5002 hysteresis = <5000>; 5003 type = "passive"; 5004 }; 5005 }; 5006 }; 5007 5008 modem2-thermal { 5009 polling-delay-passive = <0>; 5010 polling-delay = <0>; 5011 thermal-sensors = <&tsens1 12>; 5012 5013 trips { 5014 thermal-engine-config { 5015 temperature = <125000>; 5016 hysteresis = <1000>; 5017 type = "passive"; 5018 }; 5019 5020 mdmss2_config0: mdmss2-config0 { 5021 temperature = <102000>; 5022 hysteresis = <3000>; 5023 type = "passive"; 5024 }; 5025 5026 mdmss2_config1: mdmss2-config1 { 5027 temperature = <105000>; 5028 hysteresis = <3000>; 5029 type = "passive"; 5030 }; 5031 5032 reset-mon-cfg { 5033 temperature = <115000>; 5034 hysteresis = <5000>; 5035 type = "passive"; 5036 }; 5037 }; 5038 }; 5039 5040 modem3-thermal { 5041 polling-delay-passive = <0>; 5042 polling-delay = <0>; 5043 thermal-sensors = <&tsens1 13>; 5044 5045 trips { 5046 thermal-engine-config { 5047 temperature = <125000>; 5048 hysteresis = <1000>; 5049 type = "passive"; 5050 }; 5051 5052 mdmss3_config0: mdmss3-config0 { 5053 temperature = <102000>; 5054 hysteresis = <3000>; 5055 type = "passive"; 5056 }; 5057 5058 mdmss3_config1: mdmss3-config1 { 5059 temperature = <105000>; 5060 hysteresis = <3000>; 5061 type = "passive"; 5062 }; 5063 5064 reset-mon-cfg { 5065 temperature = <115000>; 5066 hysteresis = <5000>; 5067 type = "passive"; 5068 }; 5069 }; 5070 }; 5071 5072 camera0-thermal { 5073 polling-delay-passive = <0>; 5074 polling-delay = <0>; 5075 thermal-sensors = <&tsens1 14>; 5076 5077 trips { 5078 thermal-engine-config { 5079 temperature = <125000>; 5080 hysteresis = <1000>; 5081 type = "passive"; 5082 }; 5083 5084 reset-mon-cfg { 5085 temperature = <115000>; 5086 hysteresis = <5000>; 5087 type = "passive"; 5088 }; 5089 }; 5090 }; 5091 5092 camera1-thermal { 5093 polling-delay-passive = <0>; 5094 polling-delay = <0>; 5095 thermal-sensors = <&tsens1 15>; 5096 5097 trips { 5098 thermal-engine-config { 5099 temperature = <125000>; 5100 hysteresis = <1000>; 5101 type = "passive"; 5102 }; 5103 5104 reset-mon-cfg { 5105 temperature = <115000>; 5106 hysteresis = <5000>; 5107 type = "passive"; 5108 }; 5109 }; 5110 }; 5111 }; 5112 5113 timer { 5114 compatible = "arm,armv8-timer"; 5115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5119 clock-frequency = <19200000>; 5120 }; 5121}; 5122