1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 *
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a774c0-sysc.h>
11
12/ {
13	compatible = "renesas,r8a774c0";
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	/*
18	 * The external audio clocks are configured as 0 Hz fixed frequency
19	 * clocks by default.
20	 * Boards that provide audio clocks should override them.
21	 */
22	audio_clk_a: audio_clk_a {
23		compatible = "fixed-clock";
24		#clock-cells = <0>;
25		clock-frequency = <0>;
26	};
27
28	audio_clk_b: audio_clk_b {
29		compatible = "fixed-clock";
30		#clock-cells = <0>;
31		clock-frequency = <0>;
32	};
33
34	audio_clk_c: audio_clk_c {
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <0>;
38	};
39
40	/* External CAN clock - to be overridden by boards that provide it */
41	can_clk: can {
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <0>;
45	};
46
47	cluster1_opp: opp_table10 {
48		compatible = "operating-points-v2";
49		opp-shared;
50		opp-800000000 {
51			opp-hz = /bits/ 64 <800000000>;
52			opp-microvolt = <820000>;
53			clock-latency-ns = <300000>;
54		};
55		opp-1000000000 {
56			opp-hz = /bits/ 64 <1000000000>;
57			opp-microvolt = <820000>;
58			clock-latency-ns = <300000>;
59		};
60		opp-1200000000 {
61			opp-hz = /bits/ 64 <1200000000>;
62			opp-microvolt = <820000>;
63			clock-latency-ns = <300000>;
64			opp-suspend;
65		};
66	};
67
68	cpus {
69		#address-cells = <1>;
70		#size-cells = <0>;
71
72		a53_0: cpu@0 {
73			compatible = "arm,cortex-a53";
74			reg = <0>;
75			device_type = "cpu";
76			#cooling-cells = <2>;
77			power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
78			next-level-cache = <&L2_CA53>;
79			enable-method = "psci";
80			dynamic-power-coefficient = <277>;
81			clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
82			operating-points-v2 = <&cluster1_opp>;
83		};
84
85		a53_1: cpu@1 {
86			compatible = "arm,cortex-a53";
87			reg = <1>;
88			device_type = "cpu";
89			power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
90			next-level-cache = <&L2_CA53>;
91			enable-method = "psci";
92			clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
93			operating-points-v2 = <&cluster1_opp>;
94		};
95
96		L2_CA53: cache-controller-0 {
97			compatible = "cache";
98			power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
99			cache-unified;
100			cache-level = <2>;
101		};
102	};
103
104	extal_clk: extal {
105		compatible = "fixed-clock";
106		#clock-cells = <0>;
107		/* This value must be overridden by the board */
108		clock-frequency = <0>;
109	};
110
111	/* External PCIe clock - can be overridden by the board */
112	pcie_bus_clk: pcie_bus {
113		compatible = "fixed-clock";
114		#clock-cells = <0>;
115		clock-frequency = <0>;
116	};
117
118	pmu_a53 {
119		compatible = "arm,cortex-a53-pmu";
120		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
121				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
122		interrupt-affinity = <&a53_0>, <&a53_1>;
123	};
124
125	psci {
126		compatible = "arm,psci-1.0", "arm,psci-0.2";
127		method = "smc";
128	};
129
130	/* External SCIF clock - to be overridden by boards that provide it */
131	scif_clk: scif {
132		compatible = "fixed-clock";
133		#clock-cells = <0>;
134		clock-frequency = <0>;
135	};
136
137	soc: soc {
138		compatible = "simple-bus";
139		interrupt-parent = <&gic>;
140		#address-cells = <2>;
141		#size-cells = <2>;
142		ranges;
143
144		rwdt: watchdog@e6020000 {
145			compatible = "renesas,r8a774c0-wdt",
146				     "renesas,rcar-gen3-wdt";
147			reg = <0 0xe6020000 0 0x0c>;
148			clocks = <&cpg CPG_MOD 402>;
149			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
150			resets = <&cpg 402>;
151			status = "disabled";
152		};
153
154		gpio0: gpio@e6050000 {
155			compatible = "renesas,gpio-r8a774c0",
156				     "renesas,rcar-gen3-gpio";
157			reg = <0 0xe6050000 0 0x50>;
158			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
159			#gpio-cells = <2>;
160			gpio-controller;
161			gpio-ranges = <&pfc 0 0 18>;
162			#interrupt-cells = <2>;
163			interrupt-controller;
164			clocks = <&cpg CPG_MOD 912>;
165			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
166			resets = <&cpg 912>;
167		};
168
169		gpio1: gpio@e6051000 {
170			compatible = "renesas,gpio-r8a774c0",
171				     "renesas,rcar-gen3-gpio";
172			reg = <0 0xe6051000 0 0x50>;
173			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
174			#gpio-cells = <2>;
175			gpio-controller;
176			gpio-ranges = <&pfc 0 32 23>;
177			#interrupt-cells = <2>;
178			interrupt-controller;
179			clocks = <&cpg CPG_MOD 911>;
180			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
181			resets = <&cpg 911>;
182		};
183
184		gpio2: gpio@e6052000 {
185			compatible = "renesas,gpio-r8a774c0",
186				     "renesas,rcar-gen3-gpio";
187			reg = <0 0xe6052000 0 0x50>;
188			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
189			#gpio-cells = <2>;
190			gpio-controller;
191			gpio-ranges = <&pfc 0 64 26>;
192			#interrupt-cells = <2>;
193			interrupt-controller;
194			clocks = <&cpg CPG_MOD 910>;
195			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
196			resets = <&cpg 910>;
197		};
198
199		gpio3: gpio@e6053000 {
200			compatible = "renesas,gpio-r8a774c0",
201				     "renesas,rcar-gen3-gpio";
202			reg = <0 0xe6053000 0 0x50>;
203			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
204			#gpio-cells = <2>;
205			gpio-controller;
206			gpio-ranges = <&pfc 0 96 16>;
207			#interrupt-cells = <2>;
208			interrupt-controller;
209			clocks = <&cpg CPG_MOD 909>;
210			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
211			resets = <&cpg 909>;
212		};
213
214		gpio4: gpio@e6054000 {
215			compatible = "renesas,gpio-r8a774c0",
216				     "renesas,rcar-gen3-gpio";
217			reg = <0 0xe6054000 0 0x50>;
218			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
219			#gpio-cells = <2>;
220			gpio-controller;
221			gpio-ranges = <&pfc 0 128 11>;
222			#interrupt-cells = <2>;
223			interrupt-controller;
224			clocks = <&cpg CPG_MOD 908>;
225			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
226			resets = <&cpg 908>;
227		};
228
229		gpio5: gpio@e6055000 {
230			compatible = "renesas,gpio-r8a774c0",
231				     "renesas,rcar-gen3-gpio";
232			reg = <0 0xe6055000 0 0x50>;
233			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
234			#gpio-cells = <2>;
235			gpio-controller;
236			gpio-ranges = <&pfc 0 160 20>;
237			#interrupt-cells = <2>;
238			interrupt-controller;
239			clocks = <&cpg CPG_MOD 907>;
240			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
241			resets = <&cpg 907>;
242		};
243
244		gpio6: gpio@e6055400 {
245			compatible = "renesas,gpio-r8a774c0",
246				     "renesas,rcar-gen3-gpio";
247			reg = <0 0xe6055400 0 0x50>;
248			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
249			#gpio-cells = <2>;
250			gpio-controller;
251			gpio-ranges = <&pfc 0 192 18>;
252			#interrupt-cells = <2>;
253			interrupt-controller;
254			clocks = <&cpg CPG_MOD 906>;
255			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
256			resets = <&cpg 906>;
257		};
258
259		pfc: pinctrl@e6060000 {
260			compatible = "renesas,pfc-r8a774c0";
261			reg = <0 0xe6060000 0 0x508>;
262		};
263
264		cmt0: timer@e60f0000 {
265			compatible = "renesas,r8a774c0-cmt0",
266				     "renesas,rcar-gen3-cmt0";
267			reg = <0 0xe60f0000 0 0x1004>;
268			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
269				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
270			clocks = <&cpg CPG_MOD 303>;
271			clock-names = "fck";
272			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
273			resets = <&cpg 303>;
274			status = "disabled";
275		};
276
277		cmt1: timer@e6130000 {
278			compatible = "renesas,r8a774c0-cmt1",
279				     "renesas,rcar-gen3-cmt1";
280			reg = <0 0xe6130000 0 0x1004>;
281			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
282				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
283				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
284				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
285				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
286				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
287				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
288				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
289			clocks = <&cpg CPG_MOD 302>;
290			clock-names = "fck";
291			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
292			resets = <&cpg 302>;
293			status = "disabled";
294		};
295
296		cmt2: timer@e6140000 {
297			compatible = "renesas,r8a774c0-cmt1",
298				     "renesas,rcar-gen3-cmt1";
299			reg = <0 0xe6140000 0 0x1004>;
300			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
301				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
302				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
303				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
304				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
305				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
306				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
307				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
308			clocks = <&cpg CPG_MOD 301>;
309			clock-names = "fck";
310			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
311			resets = <&cpg 301>;
312			status = "disabled";
313		};
314
315		cmt3: timer@e6148000 {
316			compatible = "renesas,r8a774c0-cmt1",
317				     "renesas,rcar-gen3-cmt1";
318			reg = <0 0xe6148000 0 0x1004>;
319			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
320				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
321				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
322				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
323				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
324				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
325				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
326				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
327			clocks = <&cpg CPG_MOD 300>;
328			clock-names = "fck";
329			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
330			resets = <&cpg 300>;
331			status = "disabled";
332		};
333
334		cpg: clock-controller@e6150000 {
335			compatible = "renesas,r8a774c0-cpg-mssr";
336			reg = <0 0xe6150000 0 0x1000>;
337			clocks = <&extal_clk>;
338			clock-names = "extal";
339			#clock-cells = <2>;
340			#power-domain-cells = <0>;
341			#reset-cells = <1>;
342		};
343
344		rst: reset-controller@e6160000 {
345			compatible = "renesas,r8a774c0-rst";
346			reg = <0 0xe6160000 0 0x0200>;
347		};
348
349		sysc: system-controller@e6180000 {
350			compatible = "renesas,r8a774c0-sysc";
351			reg = <0 0xe6180000 0 0x0400>;
352			#power-domain-cells = <1>;
353		};
354
355		thermal: thermal@e6190000 {
356			compatible = "renesas,thermal-r8a774c0";
357			reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
358			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
359				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
360				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
361			clocks = <&cpg CPG_MOD 522>;
362			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
363			resets = <&cpg 522>;
364			#thermal-sensor-cells = <0>;
365		};
366
367		intc_ex: interrupt-controller@e61c0000 {
368			compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
369			#interrupt-cells = <2>;
370			interrupt-controller;
371			reg = <0 0xe61c0000 0 0x200>;
372			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
373				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
374				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
375				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
376				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
377				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
378			clocks = <&cpg CPG_MOD 407>;
379			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
380			resets = <&cpg 407>;
381		};
382
383		tmu0: timer@e61e0000 {
384			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
385			reg = <0 0xe61e0000 0 0x30>;
386			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
387				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
388				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
389			clocks = <&cpg CPG_MOD 125>;
390			clock-names = "fck";
391			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
392			resets = <&cpg 125>;
393			status = "disabled";
394		};
395
396		tmu1: timer@e6fc0000 {
397			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
398			reg = <0 0xe6fc0000 0 0x30>;
399			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
400				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
401				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
402			clocks = <&cpg CPG_MOD 124>;
403			clock-names = "fck";
404			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
405			resets = <&cpg 124>;
406			status = "disabled";
407		};
408
409		tmu2: timer@e6fd0000 {
410			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
411			reg = <0 0xe6fd0000 0 0x30>;
412			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
413				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
414				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
415			clocks = <&cpg CPG_MOD 123>;
416			clock-names = "fck";
417			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
418			resets = <&cpg 123>;
419			status = "disabled";
420		};
421
422		tmu3: timer@e6fe0000 {
423			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
424			reg = <0 0xe6fe0000 0 0x30>;
425			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
426				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
427				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
428			clocks = <&cpg CPG_MOD 122>;
429			clock-names = "fck";
430			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
431			resets = <&cpg 122>;
432			status = "disabled";
433		};
434
435		tmu4: timer@ffc00000 {
436			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
437			reg = <0 0xffc00000 0 0x30>;
438			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
439				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
440				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
441			clocks = <&cpg CPG_MOD 121>;
442			clock-names = "fck";
443			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
444			resets = <&cpg 121>;
445			status = "disabled";
446		};
447
448		i2c0: i2c@e6500000 {
449			#address-cells = <1>;
450			#size-cells = <0>;
451			compatible = "renesas,i2c-r8a774c0",
452				     "renesas,rcar-gen3-i2c";
453			reg = <0 0xe6500000 0 0x40>;
454			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
455			clocks = <&cpg CPG_MOD 931>;
456			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
457			resets = <&cpg 931>;
458			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
459			       <&dmac2 0x91>, <&dmac2 0x90>;
460			dma-names = "tx", "rx", "tx", "rx";
461			i2c-scl-internal-delay-ns = <110>;
462			status = "disabled";
463		};
464
465		i2c1: i2c@e6508000 {
466			#address-cells = <1>;
467			#size-cells = <0>;
468			compatible = "renesas,i2c-r8a774c0",
469				     "renesas,rcar-gen3-i2c";
470			reg = <0 0xe6508000 0 0x40>;
471			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
472			clocks = <&cpg CPG_MOD 930>;
473			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
474			resets = <&cpg 930>;
475			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
476			       <&dmac2 0x93>, <&dmac2 0x92>;
477			dma-names = "tx", "rx", "tx", "rx";
478			i2c-scl-internal-delay-ns = <6>;
479			status = "disabled";
480		};
481
482		i2c2: i2c@e6510000 {
483			#address-cells = <1>;
484			#size-cells = <0>;
485			compatible = "renesas,i2c-r8a774c0",
486				     "renesas,rcar-gen3-i2c";
487			reg = <0 0xe6510000 0 0x40>;
488			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
489			clocks = <&cpg CPG_MOD 929>;
490			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
491			resets = <&cpg 929>;
492			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
493			       <&dmac2 0x95>, <&dmac2 0x94>;
494			dma-names = "tx", "rx", "tx", "rx";
495			i2c-scl-internal-delay-ns = <6>;
496			status = "disabled";
497		};
498
499		i2c3: i2c@e66d0000 {
500			#address-cells = <1>;
501			#size-cells = <0>;
502			compatible = "renesas,i2c-r8a774c0",
503				     "renesas,rcar-gen3-i2c";
504			reg = <0 0xe66d0000 0 0x40>;
505			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
506			clocks = <&cpg CPG_MOD 928>;
507			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
508			resets = <&cpg 928>;
509			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
510			dma-names = "tx", "rx";
511			i2c-scl-internal-delay-ns = <110>;
512			status = "disabled";
513		};
514
515		i2c4: i2c@e66d8000 {
516			#address-cells = <1>;
517			#size-cells = <0>;
518			compatible = "renesas,i2c-r8a774c0",
519				     "renesas,rcar-gen3-i2c";
520			reg = <0 0xe66d8000 0 0x40>;
521			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
522			clocks = <&cpg CPG_MOD 927>;
523			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
524			resets = <&cpg 927>;
525			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
526			dma-names = "tx", "rx";
527			i2c-scl-internal-delay-ns = <6>;
528			status = "disabled";
529		};
530
531		i2c5: i2c@e66e0000 {
532			#address-cells = <1>;
533			#size-cells = <0>;
534			compatible = "renesas,i2c-r8a774c0",
535				     "renesas,rcar-gen3-i2c";
536			reg = <0 0xe66e0000 0 0x40>;
537			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
538			clocks = <&cpg CPG_MOD 919>;
539			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
540			resets = <&cpg 919>;
541			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
542			dma-names = "tx", "rx";
543			i2c-scl-internal-delay-ns = <6>;
544			status = "disabled";
545		};
546
547		i2c6: i2c@e66e8000 {
548			#address-cells = <1>;
549			#size-cells = <0>;
550			compatible = "renesas,i2c-r8a774c0",
551				     "renesas,rcar-gen3-i2c";
552			reg = <0 0xe66e8000 0 0x40>;
553			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
554			clocks = <&cpg CPG_MOD 918>;
555			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
556			resets = <&cpg 918>;
557			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
558			dma-names = "tx", "rx";
559			i2c-scl-internal-delay-ns = <6>;
560			status = "disabled";
561		};
562
563		i2c7: i2c@e6690000 {
564			#address-cells = <1>;
565			#size-cells = <0>;
566			compatible = "renesas,i2c-r8a774c0",
567				     "renesas,rcar-gen3-i2c";
568			reg = <0 0xe6690000 0 0x40>;
569			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
570			clocks = <&cpg CPG_MOD 1003>;
571			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
572			resets = <&cpg 1003>;
573			i2c-scl-internal-delay-ns = <6>;
574			status = "disabled";
575		};
576
577		iic_pmic: i2c@e60b0000 {
578			#address-cells = <1>;
579			#size-cells = <0>;
580			compatible = "renesas,iic-r8a774c0",
581				     "renesas,rcar-gen3-iic",
582				     "renesas,rmobile-iic";
583			reg = <0 0xe60b0000 0 0x425>;
584			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
585			clocks = <&cpg CPG_MOD 926>;
586			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
587			resets = <&cpg 926>;
588			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
589			dma-names = "tx", "rx";
590			status = "disabled";
591		};
592
593		hscif0: serial@e6540000 {
594			compatible = "renesas,hscif-r8a774c0",
595				     "renesas,rcar-gen3-hscif",
596				     "renesas,hscif";
597			reg = <0 0xe6540000 0 0x60>;
598			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
599			clocks = <&cpg CPG_MOD 520>,
600				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
601				 <&scif_clk>;
602			clock-names = "fck", "brg_int", "scif_clk";
603			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
604			       <&dmac2 0x31>, <&dmac2 0x30>;
605			dma-names = "tx", "rx", "tx", "rx";
606			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
607			resets = <&cpg 520>;
608			status = "disabled";
609		};
610
611		hscif1: serial@e6550000 {
612			compatible = "renesas,hscif-r8a774c0",
613				     "renesas,rcar-gen3-hscif",
614				     "renesas,hscif";
615			reg = <0 0xe6550000 0 0x60>;
616			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
617			clocks = <&cpg CPG_MOD 519>,
618				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
619				 <&scif_clk>;
620			clock-names = "fck", "brg_int", "scif_clk";
621			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
622			       <&dmac2 0x33>, <&dmac2 0x32>;
623			dma-names = "tx", "rx", "tx", "rx";
624			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
625			resets = <&cpg 519>;
626			status = "disabled";
627		};
628
629		hscif2: serial@e6560000 {
630			compatible = "renesas,hscif-r8a774c0",
631				     "renesas,rcar-gen3-hscif",
632				     "renesas,hscif";
633			reg = <0 0xe6560000 0 0x60>;
634			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
635			clocks = <&cpg CPG_MOD 518>,
636				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
637				 <&scif_clk>;
638			clock-names = "fck", "brg_int", "scif_clk";
639			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
640			       <&dmac2 0x35>, <&dmac2 0x34>;
641			dma-names = "tx", "rx", "tx", "rx";
642			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
643			resets = <&cpg 518>;
644			status = "disabled";
645		};
646
647		hscif3: serial@e66a0000 {
648			compatible = "renesas,hscif-r8a774c0",
649				     "renesas,rcar-gen3-hscif",
650				     "renesas,hscif";
651			reg = <0 0xe66a0000 0 0x60>;
652			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
653			clocks = <&cpg CPG_MOD 517>,
654				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
655				 <&scif_clk>;
656			clock-names = "fck", "brg_int", "scif_clk";
657			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
658			dma-names = "tx", "rx";
659			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
660			resets = <&cpg 517>;
661			status = "disabled";
662		};
663
664		hscif4: serial@e66b0000 {
665			compatible = "renesas,hscif-r8a774c0",
666				     "renesas,rcar-gen3-hscif",
667				     "renesas,hscif";
668			reg = <0 0xe66b0000 0 0x60>;
669			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
670			clocks = <&cpg CPG_MOD 516>,
671				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
672				 <&scif_clk>;
673			clock-names = "fck", "brg_int", "scif_clk";
674			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
675			dma-names = "tx", "rx";
676			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
677			resets = <&cpg 516>;
678			status = "disabled";
679		};
680
681		hsusb: usb@e6590000 {
682			compatible = "renesas,usbhs-r8a774c0",
683				     "renesas,rcar-gen3-usbhs";
684			reg = <0 0xe6590000 0 0x200>;
685			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
686			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
687			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
688			       <&usb_dmac1 0>, <&usb_dmac1 1>;
689			dma-names = "ch0", "ch1", "ch2", "ch3";
690			renesas,buswait = <11>;
691			phys = <&usb2_phy0 3>;
692			phy-names = "usb";
693			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
694			resets = <&cpg 704>, <&cpg 703>;
695			status = "disabled";
696		};
697
698		usb_dmac0: dma-controller@e65a0000 {
699			compatible = "renesas,r8a774c0-usb-dmac",
700				     "renesas,usb-dmac";
701			reg = <0 0xe65a0000 0 0x100>;
702			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
703				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
704			interrupt-names = "ch0", "ch1";
705			clocks = <&cpg CPG_MOD 330>;
706			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
707			resets = <&cpg 330>;
708			#dma-cells = <1>;
709			dma-channels = <2>;
710		};
711
712		usb_dmac1: dma-controller@e65b0000 {
713			compatible = "renesas,r8a774c0-usb-dmac",
714				     "renesas,usb-dmac";
715			reg = <0 0xe65b0000 0 0x100>;
716			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
717				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
718			interrupt-names = "ch0", "ch1";
719			clocks = <&cpg CPG_MOD 331>;
720			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
721			resets = <&cpg 331>;
722			#dma-cells = <1>;
723			dma-channels = <2>;
724		};
725
726		dmac0: dma-controller@e6700000 {
727			compatible = "renesas,dmac-r8a774c0",
728				     "renesas,rcar-dmac";
729			reg = <0 0xe6700000 0 0x10000>;
730			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
731				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
732				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
733				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
734				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
735				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
736				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
737				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
738				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
739				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
740				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
741				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
742				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
743				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
744				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
745				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
746				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
747			interrupt-names = "error",
748					"ch0", "ch1", "ch2", "ch3",
749					"ch4", "ch5", "ch6", "ch7",
750					"ch8", "ch9", "ch10", "ch11",
751					"ch12", "ch13", "ch14", "ch15";
752			clocks = <&cpg CPG_MOD 219>;
753			clock-names = "fck";
754			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
755			resets = <&cpg 219>;
756			#dma-cells = <1>;
757			dma-channels = <16>;
758			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
759			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
760			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
761			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
762			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
763			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
764			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
765			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
766		};
767
768		dmac1: dma-controller@e7300000 {
769			compatible = "renesas,dmac-r8a774c0",
770				     "renesas,rcar-dmac";
771			reg = <0 0xe7300000 0 0x10000>;
772			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
773				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
774				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
775				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
776				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
777				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
778				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
779				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
780				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
781				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
782				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
783				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
784				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
785				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
786				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
787				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
788				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
789			interrupt-names = "error",
790					"ch0", "ch1", "ch2", "ch3",
791					"ch4", "ch5", "ch6", "ch7",
792					"ch8", "ch9", "ch10", "ch11",
793					"ch12", "ch13", "ch14", "ch15";
794			clocks = <&cpg CPG_MOD 218>;
795			clock-names = "fck";
796			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
797			resets = <&cpg 218>;
798			#dma-cells = <1>;
799			dma-channels = <16>;
800			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
801			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
802			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
803			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
804			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
805			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
806			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
807			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
808		};
809
810		dmac2: dma-controller@e7310000 {
811			compatible = "renesas,dmac-r8a774c0",
812				     "renesas,rcar-dmac";
813			reg = <0 0xe7310000 0 0x10000>;
814			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
815				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
816				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
817				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
818				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
819				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
820				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
821				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
822				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
823				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
824				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
825				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
826				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
827				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
828				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
829				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
830				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
831			interrupt-names = "error",
832					"ch0", "ch1", "ch2", "ch3",
833					"ch4", "ch5", "ch6", "ch7",
834					"ch8", "ch9", "ch10", "ch11",
835					"ch12", "ch13", "ch14", "ch15";
836			clocks = <&cpg CPG_MOD 217>;
837			clock-names = "fck";
838			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
839			resets = <&cpg 217>;
840			#dma-cells = <1>;
841			dma-channels = <16>;
842			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
843			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
844			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
845			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
846			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
847			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
848			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
849			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
850		};
851
852		ipmmu_ds0: iommu@e6740000 {
853			compatible = "renesas,ipmmu-r8a774c0";
854			reg = <0 0xe6740000 0 0x1000>;
855			renesas,ipmmu-main = <&ipmmu_mm 0>;
856			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
857			#iommu-cells = <1>;
858		};
859
860		ipmmu_ds1: iommu@e7740000 {
861			compatible = "renesas,ipmmu-r8a774c0";
862			reg = <0 0xe7740000 0 0x1000>;
863			renesas,ipmmu-main = <&ipmmu_mm 1>;
864			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
865			#iommu-cells = <1>;
866		};
867
868		ipmmu_hc: iommu@e6570000 {
869			compatible = "renesas,ipmmu-r8a774c0";
870			reg = <0 0xe6570000 0 0x1000>;
871			renesas,ipmmu-main = <&ipmmu_mm 2>;
872			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
873			#iommu-cells = <1>;
874		};
875
876		ipmmu_mm: iommu@e67b0000 {
877			compatible = "renesas,ipmmu-r8a774c0";
878			reg = <0 0xe67b0000 0 0x1000>;
879			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
880				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
881			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
882			#iommu-cells = <1>;
883		};
884
885		ipmmu_mp: iommu@ec670000 {
886			compatible = "renesas,ipmmu-r8a774c0";
887			reg = <0 0xec670000 0 0x1000>;
888			renesas,ipmmu-main = <&ipmmu_mm 4>;
889			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
890			#iommu-cells = <1>;
891		};
892
893		ipmmu_pv0: iommu@fd800000 {
894			compatible = "renesas,ipmmu-r8a774c0";
895			reg = <0 0xfd800000 0 0x1000>;
896			renesas,ipmmu-main = <&ipmmu_mm 6>;
897			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
898			#iommu-cells = <1>;
899		};
900
901		ipmmu_vc0: iommu@fe6b0000 {
902			compatible = "renesas,ipmmu-r8a774c0";
903			reg = <0 0xfe6b0000 0 0x1000>;
904			renesas,ipmmu-main = <&ipmmu_mm 12>;
905			power-domains = <&sysc R8A774C0_PD_A3VC>;
906			#iommu-cells = <1>;
907		};
908
909		ipmmu_vi0: iommu@febd0000 {
910			compatible = "renesas,ipmmu-r8a774c0";
911			reg = <0 0xfebd0000 0 0x1000>;
912			renesas,ipmmu-main = <&ipmmu_mm 14>;
913			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
914			#iommu-cells = <1>;
915		};
916
917		ipmmu_vp0: iommu@fe990000 {
918			compatible = "renesas,ipmmu-r8a774c0";
919			reg = <0 0xfe990000 0 0x1000>;
920			renesas,ipmmu-main = <&ipmmu_mm 16>;
921			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
922			#iommu-cells = <1>;
923		};
924
925		avb: ethernet@e6800000 {
926			compatible = "renesas,etheravb-r8a774c0",
927				     "renesas,etheravb-rcar-gen3";
928			reg = <0 0xe6800000 0 0x800>;
929			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
930				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
931				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
932				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
933				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
934				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
935				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
936				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
937				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
938				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
939				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
940				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
941				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
942				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
943				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
944				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
945				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
946				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
947				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
948				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
949				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
950				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
951				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
952				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
953				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
954			interrupt-names = "ch0", "ch1", "ch2", "ch3",
955					  "ch4", "ch5", "ch6", "ch7",
956					  "ch8", "ch9", "ch10", "ch11",
957					  "ch12", "ch13", "ch14", "ch15",
958					  "ch16", "ch17", "ch18", "ch19",
959					  "ch20", "ch21", "ch22", "ch23",
960					  "ch24";
961			clocks = <&cpg CPG_MOD 812>;
962			clock-names = "fck";
963			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
964			resets = <&cpg 812>;
965			phy-mode = "rgmii";
966			rx-internal-delay-ps = <0>;
967			iommus = <&ipmmu_ds0 16>;
968			#address-cells = <1>;
969			#size-cells = <0>;
970			status = "disabled";
971		};
972
973		can0: can@e6c30000 {
974			compatible = "renesas,can-r8a774c0",
975				     "renesas,rcar-gen3-can";
976			reg = <0 0xe6c30000 0 0x1000>;
977			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
978			clocks = <&cpg CPG_MOD 916>,
979				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
980				 <&can_clk>;
981			clock-names = "clkp1", "clkp2", "can_clk";
982			assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
983			assigned-clock-rates = <40000000>;
984			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
985			resets = <&cpg 916>;
986			status = "disabled";
987		};
988
989		can1: can@e6c38000 {
990			compatible = "renesas,can-r8a774c0",
991				     "renesas,rcar-gen3-can";
992			reg = <0 0xe6c38000 0 0x1000>;
993			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
994			clocks = <&cpg CPG_MOD 915>,
995				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
996				 <&can_clk>;
997			clock-names = "clkp1", "clkp2", "can_clk";
998			assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
999			assigned-clock-rates = <40000000>;
1000			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1001			resets = <&cpg 915>;
1002			status = "disabled";
1003		};
1004
1005		canfd: can@e66c0000 {
1006			compatible = "renesas,r8a774c0-canfd",
1007				     "renesas,rcar-gen3-canfd";
1008			reg = <0 0xe66c0000 0 0x8000>;
1009			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1010				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1011			clocks = <&cpg CPG_MOD 914>,
1012				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1013				 <&can_clk>;
1014			clock-names = "fck", "canfd", "can_clk";
1015			assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1016			assigned-clock-rates = <40000000>;
1017			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1018			resets = <&cpg 914>;
1019			status = "disabled";
1020
1021			channel0 {
1022				status = "disabled";
1023			};
1024
1025			channel1 {
1026				status = "disabled";
1027			};
1028		};
1029
1030		pwm0: pwm@e6e30000 {
1031			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1032			reg = <0 0xe6e30000 0 0x8>;
1033			clocks = <&cpg CPG_MOD 523>;
1034			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1035			resets = <&cpg 523>;
1036			#pwm-cells = <2>;
1037			status = "disabled";
1038		};
1039
1040		pwm1: pwm@e6e31000 {
1041			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1042			reg = <0 0xe6e31000 0 0x8>;
1043			clocks = <&cpg CPG_MOD 523>;
1044			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1045			resets = <&cpg 523>;
1046			#pwm-cells = <2>;
1047			status = "disabled";
1048		};
1049
1050		pwm2: pwm@e6e32000 {
1051			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1052			reg = <0 0xe6e32000 0 0x8>;
1053			clocks = <&cpg CPG_MOD 523>;
1054			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1055			resets = <&cpg 523>;
1056			#pwm-cells = <2>;
1057			status = "disabled";
1058		};
1059
1060		pwm3: pwm@e6e33000 {
1061			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1062			reg = <0 0xe6e33000 0 0x8>;
1063			clocks = <&cpg CPG_MOD 523>;
1064			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1065			resets = <&cpg 523>;
1066			#pwm-cells = <2>;
1067			status = "disabled";
1068		};
1069
1070		pwm4: pwm@e6e34000 {
1071			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1072			reg = <0 0xe6e34000 0 0x8>;
1073			clocks = <&cpg CPG_MOD 523>;
1074			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1075			resets = <&cpg 523>;
1076			#pwm-cells = <2>;
1077			status = "disabled";
1078		};
1079
1080		pwm5: pwm@e6e35000 {
1081			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1082			reg = <0 0xe6e35000 0 0x8>;
1083			clocks = <&cpg CPG_MOD 523>;
1084			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1085			resets = <&cpg 523>;
1086			#pwm-cells = <2>;
1087			status = "disabled";
1088		};
1089
1090		pwm6: pwm@e6e36000 {
1091			compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1092			reg = <0 0xe6e36000 0 0x8>;
1093			clocks = <&cpg CPG_MOD 523>;
1094			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1095			resets = <&cpg 523>;
1096			#pwm-cells = <2>;
1097			status = "disabled";
1098		};
1099
1100		scif0: serial@e6e60000 {
1101			compatible = "renesas,scif-r8a774c0",
1102				     "renesas,rcar-gen3-scif", "renesas,scif";
1103			reg = <0 0xe6e60000 0 64>;
1104			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1105			clocks = <&cpg CPG_MOD 207>,
1106				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1107				 <&scif_clk>;
1108			clock-names = "fck", "brg_int", "scif_clk";
1109			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1110			       <&dmac2 0x51>, <&dmac2 0x50>;
1111			dma-names = "tx", "rx", "tx", "rx";
1112			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1113			resets = <&cpg 207>;
1114			status = "disabled";
1115		};
1116
1117		scif1: serial@e6e68000 {
1118			compatible = "renesas,scif-r8a774c0",
1119				     "renesas,rcar-gen3-scif", "renesas,scif";
1120			reg = <0 0xe6e68000 0 64>;
1121			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1122			clocks = <&cpg CPG_MOD 206>,
1123				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1124				 <&scif_clk>;
1125			clock-names = "fck", "brg_int", "scif_clk";
1126			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1127			       <&dmac2 0x53>, <&dmac2 0x52>;
1128			dma-names = "tx", "rx", "tx", "rx";
1129			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1130			resets = <&cpg 206>;
1131			status = "disabled";
1132		};
1133
1134		scif2: serial@e6e88000 {
1135			compatible = "renesas,scif-r8a774c0",
1136				     "renesas,rcar-gen3-scif", "renesas,scif";
1137			reg = <0 0xe6e88000 0 64>;
1138			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1139			clocks = <&cpg CPG_MOD 310>,
1140				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1141				 <&scif_clk>;
1142			clock-names = "fck", "brg_int", "scif_clk";
1143			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1144			       <&dmac2 0x13>, <&dmac2 0x12>;
1145			dma-names = "tx", "rx", "tx", "rx";
1146			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1147			resets = <&cpg 310>;
1148			status = "disabled";
1149		};
1150
1151		scif3: serial@e6c50000 {
1152			compatible = "renesas,scif-r8a774c0",
1153				     "renesas,rcar-gen3-scif", "renesas,scif";
1154			reg = <0 0xe6c50000 0 64>;
1155			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1156			clocks = <&cpg CPG_MOD 204>,
1157				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1158				 <&scif_clk>;
1159			clock-names = "fck", "brg_int", "scif_clk";
1160			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1161			dma-names = "tx", "rx";
1162			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1163			resets = <&cpg 204>;
1164			status = "disabled";
1165		};
1166
1167		scif4: serial@e6c40000 {
1168			compatible = "renesas,scif-r8a774c0",
1169				     "renesas,rcar-gen3-scif", "renesas,scif";
1170			reg = <0 0xe6c40000 0 64>;
1171			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1172			clocks = <&cpg CPG_MOD 203>,
1173				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1174				 <&scif_clk>;
1175			clock-names = "fck", "brg_int", "scif_clk";
1176			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1177			dma-names = "tx", "rx";
1178			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1179			resets = <&cpg 203>;
1180			status = "disabled";
1181		};
1182
1183		scif5: serial@e6f30000 {
1184			compatible = "renesas,scif-r8a774c0",
1185				     "renesas,rcar-gen3-scif", "renesas,scif";
1186			reg = <0 0xe6f30000 0 64>;
1187			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1188			clocks = <&cpg CPG_MOD 202>,
1189				 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1190				 <&scif_clk>;
1191			clock-names = "fck", "brg_int", "scif_clk";
1192			dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1193			dma-names = "tx", "rx";
1194			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1195			resets = <&cpg 202>;
1196			status = "disabled";
1197		};
1198
1199		msiof0: spi@e6e90000 {
1200			compatible = "renesas,msiof-r8a774c0",
1201				     "renesas,rcar-gen3-msiof";
1202			reg = <0 0xe6e90000 0 0x0064>;
1203			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1204			clocks = <&cpg CPG_MOD 211>;
1205			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1206			       <&dmac2 0x41>, <&dmac2 0x40>;
1207			dma-names = "tx", "rx", "tx", "rx";
1208			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1209			resets = <&cpg 211>;
1210			#address-cells = <1>;
1211			#size-cells = <0>;
1212			status = "disabled";
1213		};
1214
1215		msiof1: spi@e6ea0000 {
1216			compatible = "renesas,msiof-r8a774c0",
1217				     "renesas,rcar-gen3-msiof";
1218			reg = <0 0xe6ea0000 0 0x0064>;
1219			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1220			clocks = <&cpg CPG_MOD 210>;
1221			dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1222			dma-names = "tx", "rx";
1223			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1224			resets = <&cpg 210>;
1225			#address-cells = <1>;
1226			#size-cells = <0>;
1227			status = "disabled";
1228		};
1229
1230		msiof2: spi@e6c00000 {
1231			compatible = "renesas,msiof-r8a774c0",
1232				     "renesas,rcar-gen3-msiof";
1233			reg = <0 0xe6c00000 0 0x0064>;
1234			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1235			clocks = <&cpg CPG_MOD 209>;
1236			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1237			dma-names = "tx", "rx";
1238			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1239			resets = <&cpg 209>;
1240			#address-cells = <1>;
1241			#size-cells = <0>;
1242			status = "disabled";
1243		};
1244
1245		msiof3: spi@e6c10000 {
1246			compatible = "renesas,msiof-r8a774c0",
1247				     "renesas,rcar-gen3-msiof";
1248			reg = <0 0xe6c10000 0 0x0064>;
1249			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1250			clocks = <&cpg CPG_MOD 208>;
1251			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1252			dma-names = "tx", "rx";
1253			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1254			resets = <&cpg 208>;
1255			#address-cells = <1>;
1256			#size-cells = <0>;
1257			status = "disabled";
1258		};
1259
1260		vin4: video@e6ef4000 {
1261			compatible = "renesas,vin-r8a774c0";
1262			reg = <0 0xe6ef4000 0 0x1000>;
1263			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1264			clocks = <&cpg CPG_MOD 807>;
1265			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1266			resets = <&cpg 807>;
1267			renesas,id = <4>;
1268			status = "disabled";
1269
1270			ports {
1271				#address-cells = <1>;
1272				#size-cells = <0>;
1273
1274				port@1 {
1275					#address-cells = <1>;
1276					#size-cells = <0>;
1277
1278					reg = <1>;
1279
1280					vin4csi40: endpoint@2 {
1281						reg = <2>;
1282						remote-endpoint= <&csi40vin4>;
1283					};
1284				};
1285			};
1286		};
1287
1288		vin5: video@e6ef5000 {
1289			compatible = "renesas,vin-r8a774c0";
1290			reg = <0 0xe6ef5000 0 0x1000>;
1291			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1292			clocks = <&cpg CPG_MOD 806>;
1293			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1294			resets = <&cpg 806>;
1295			renesas,id = <5>;
1296			status = "disabled";
1297
1298			ports {
1299				#address-cells = <1>;
1300				#size-cells = <0>;
1301
1302				port@1 {
1303					#address-cells = <1>;
1304					#size-cells = <0>;
1305
1306					reg = <1>;
1307
1308					vin5csi40: endpoint@2 {
1309						reg = <2>;
1310						remote-endpoint= <&csi40vin5>;
1311					};
1312				};
1313			};
1314		};
1315
1316		rcar_sound: sound@ec500000 {
1317			/*
1318			 * #sound-dai-cells is required
1319			 *
1320			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
1321			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
1322			 */
1323			/*
1324			 * #clock-cells is required for audio_clkout0/1/2/3
1325			 *
1326			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
1327			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
1328			 */
1329			compatible = "renesas,rcar_sound-r8a774c0",
1330				     "renesas,rcar_sound-gen3";
1331			reg =	<0 0xec500000 0 0x1000>, /* SCU */
1332				<0 0xec5a0000 0 0x100>,  /* ADG */
1333				<0 0xec540000 0 0x1000>, /* SSIU */
1334				<0 0xec541000 0 0x280>,  /* SSI */
1335				<0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
1336			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1337
1338			clocks = <&cpg CPG_MOD 1005>,
1339				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1340				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1341				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1342				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1343				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1344				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1345				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1346				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1347				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1348				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1349				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1350				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1351				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1352				 <&audio_clk_a>, <&audio_clk_b>,
1353				 <&audio_clk_c>,
1354				 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
1355			clock-names = "ssi-all",
1356				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1357				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1358				      "ssi.1", "ssi.0",
1359				      "src.9", "src.8", "src.7", "src.6",
1360				      "src.5", "src.4", "src.3", "src.2",
1361				      "src.1", "src.0",
1362				      "mix.1", "mix.0",
1363				      "ctu.1", "ctu.0",
1364				      "dvc.0", "dvc.1",
1365				      "clk_a", "clk_b", "clk_c", "clk_i";
1366			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1367			resets = <&cpg 1005>,
1368				 <&cpg 1006>, <&cpg 1007>,
1369				 <&cpg 1008>, <&cpg 1009>,
1370				 <&cpg 1010>, <&cpg 1011>,
1371				 <&cpg 1012>, <&cpg 1013>,
1372				 <&cpg 1014>, <&cpg 1015>;
1373			reset-names = "ssi-all",
1374				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1375				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1376				      "ssi.1", "ssi.0";
1377			status = "disabled";
1378
1379			rcar_sound,ctu {
1380				ctu00: ctu-0 { };
1381				ctu01: ctu-1 { };
1382				ctu02: ctu-2 { };
1383				ctu03: ctu-3 { };
1384				ctu10: ctu-4 { };
1385				ctu11: ctu-5 { };
1386				ctu12: ctu-6 { };
1387				ctu13: ctu-7 { };
1388			};
1389
1390			rcar_sound,dvc {
1391				dvc0: dvc-0 {
1392					dmas = <&audma0 0xbc>;
1393					dma-names = "tx";
1394				};
1395				dvc1: dvc-1 {
1396					dmas = <&audma0 0xbe>;
1397					dma-names = "tx";
1398				};
1399			};
1400
1401			rcar_sound,mix {
1402				mix0: mix-0 { };
1403				mix1: mix-1 { };
1404			};
1405
1406			rcar_sound,src {
1407				src0: src-0 {
1408					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1409					dmas = <&audma0 0x85>, <&audma0 0x9a>;
1410					dma-names = "rx", "tx";
1411				};
1412				src1: src-1 {
1413					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1414					dmas = <&audma0 0x87>, <&audma0 0x9c>;
1415					dma-names = "rx", "tx";
1416				};
1417				src2: src-2 {
1418					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1419					dmas = <&audma0 0x89>, <&audma0 0x9e>;
1420					dma-names = "rx", "tx";
1421				};
1422				src3: src-3 {
1423					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1424					dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1425					dma-names = "rx", "tx";
1426				};
1427				src4: src-4 {
1428					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1429					dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1430					dma-names = "rx", "tx";
1431				};
1432				src5: src-5 {
1433					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1434					dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1435					dma-names = "rx", "tx";
1436				};
1437				src6: src-6 {
1438					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1439					dmas = <&audma0 0x91>, <&audma0 0xb4>;
1440					dma-names = "rx", "tx";
1441				};
1442				src7: src-7 {
1443					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1444					dmas = <&audma0 0x93>, <&audma0 0xb6>;
1445					dma-names = "rx", "tx";
1446				};
1447				src8: src-8 {
1448					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1449					dmas = <&audma0 0x95>, <&audma0 0xb8>;
1450					dma-names = "rx", "tx";
1451				};
1452				src9: src-9 {
1453					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1454					dmas = <&audma0 0x97>, <&audma0 0xba>;
1455					dma-names = "rx", "tx";
1456				};
1457			};
1458
1459			rcar_sound,ssi {
1460				ssi0: ssi-0 {
1461					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1462					dmas = <&audma0 0x01>, <&audma0 0x02>,
1463					       <&audma0 0x15>, <&audma0 0x16>;
1464					dma-names = "rx", "tx", "rxu", "txu";
1465				};
1466				ssi1: ssi-1 {
1467					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1468					dmas = <&audma0 0x03>, <&audma0 0x04>,
1469					       <&audma0 0x49>, <&audma0 0x4a>;
1470					dma-names = "rx", "tx", "rxu", "txu";
1471				};
1472				ssi2: ssi-2 {
1473					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1474					dmas = <&audma0 0x05>, <&audma0 0x06>,
1475					       <&audma0 0x63>, <&audma0 0x64>;
1476					dma-names = "rx", "tx", "rxu", "txu";
1477				};
1478				ssi3: ssi-3 {
1479					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1480					dmas = <&audma0 0x07>, <&audma0 0x08>,
1481					       <&audma0 0x6f>, <&audma0 0x70>;
1482					dma-names = "rx", "tx", "rxu", "txu";
1483				};
1484				ssi4: ssi-4 {
1485					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1486					dmas = <&audma0 0x09>, <&audma0 0x0a>,
1487					       <&audma0 0x71>, <&audma0 0x72>;
1488					dma-names = "rx", "tx", "rxu", "txu";
1489				};
1490				ssi5: ssi-5 {
1491					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1492					dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1493					       <&audma0 0x73>, <&audma0 0x74>;
1494					dma-names = "rx", "tx", "rxu", "txu";
1495				};
1496				ssi6: ssi-6 {
1497					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1498					dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1499					       <&audma0 0x75>, <&audma0 0x76>;
1500					dma-names = "rx", "tx", "rxu", "txu";
1501				};
1502				ssi7: ssi-7 {
1503					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1504					dmas = <&audma0 0x0f>, <&audma0 0x10>,
1505					       <&audma0 0x79>, <&audma0 0x7a>;
1506					dma-names = "rx", "tx", "rxu", "txu";
1507				};
1508				ssi8: ssi-8 {
1509					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1510					dmas = <&audma0 0x11>, <&audma0 0x12>,
1511					       <&audma0 0x7b>, <&audma0 0x7c>;
1512					dma-names = "rx", "tx", "rxu", "txu";
1513				};
1514				ssi9: ssi-9 {
1515					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1516					dmas = <&audma0 0x13>, <&audma0 0x14>,
1517					       <&audma0 0x7d>, <&audma0 0x7e>;
1518					dma-names = "rx", "tx", "rxu", "txu";
1519				};
1520			};
1521		};
1522
1523		audma0: dma-controller@ec700000 {
1524			compatible = "renesas,dmac-r8a774c0",
1525				     "renesas,rcar-dmac";
1526			reg = <0 0xec700000 0 0x10000>;
1527			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1528				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1529				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1530				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1531				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1532				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1533				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1534				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1535				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1536				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1537				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1538				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1539				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1540				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1541				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1542				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1543				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1544			interrupt-names = "error",
1545					"ch0", "ch1", "ch2", "ch3",
1546					"ch4", "ch5", "ch6", "ch7",
1547					"ch8", "ch9", "ch10", "ch11",
1548					"ch12", "ch13", "ch14", "ch15";
1549			clocks = <&cpg CPG_MOD 502>;
1550			clock-names = "fck";
1551			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1552			resets = <&cpg 502>;
1553			#dma-cells = <1>;
1554			dma-channels = <16>;
1555			iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1556				 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1557				 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1558				 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1559				 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1560				 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1561				 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1562				 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1563		};
1564
1565		xhci0: usb@ee000000 {
1566			compatible = "renesas,xhci-r8a774c0",
1567				     "renesas,rcar-gen3-xhci";
1568			reg = <0 0xee000000 0 0xc00>;
1569			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1570			clocks = <&cpg CPG_MOD 328>;
1571			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1572			resets = <&cpg 328>;
1573			status = "disabled";
1574		};
1575
1576		usb3_peri0: usb@ee020000 {
1577			compatible = "renesas,r8a774c0-usb3-peri",
1578				     "renesas,rcar-gen3-usb3-peri";
1579			reg = <0 0xee020000 0 0x400>;
1580			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1581			clocks = <&cpg CPG_MOD 328>;
1582			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1583			resets = <&cpg 328>;
1584			status = "disabled";
1585		};
1586
1587		ohci0: usb@ee080000 {
1588			compatible = "generic-ohci";
1589			reg = <0 0xee080000 0 0x100>;
1590			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1591			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1592			phys = <&usb2_phy0 1>;
1593			phy-names = "usb";
1594			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1595			resets = <&cpg 703>, <&cpg 704>;
1596			status = "disabled";
1597		};
1598
1599		ehci0: usb@ee080100 {
1600			compatible = "generic-ehci";
1601			reg = <0 0xee080100 0 0x100>;
1602			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1603			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1604			phys = <&usb2_phy0 2>;
1605			phy-names = "usb";
1606			companion = <&ohci0>;
1607			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1608			resets = <&cpg 703>, <&cpg 704>;
1609			status = "disabled";
1610		};
1611
1612		usb2_phy0: usb-phy@ee080200 {
1613			compatible = "renesas,usb2-phy-r8a774c0",
1614				     "renesas,rcar-gen3-usb2-phy";
1615			reg = <0 0xee080200 0 0x700>;
1616			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1617			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1618			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1619			resets = <&cpg 703>, <&cpg 704>;
1620			#phy-cells = <1>;
1621			status = "disabled";
1622		};
1623
1624		sdhi0: mmc@ee100000 {
1625			compatible = "renesas,sdhi-r8a774c0",
1626				     "renesas,rcar-gen3-sdhi";
1627			reg = <0 0xee100000 0 0x2000>;
1628			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1629			clocks = <&cpg CPG_MOD 314>;
1630			max-frequency = <200000000>;
1631			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1632			resets = <&cpg 314>;
1633			status = "disabled";
1634		};
1635
1636		sdhi1: mmc@ee120000 {
1637			compatible = "renesas,sdhi-r8a774c0",
1638				     "renesas,rcar-gen3-sdhi";
1639			reg = <0 0xee120000 0 0x2000>;
1640			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1641			clocks = <&cpg CPG_MOD 313>;
1642			max-frequency = <200000000>;
1643			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1644			resets = <&cpg 313>;
1645			status = "disabled";
1646		};
1647
1648		sdhi3: mmc@ee160000 {
1649			compatible = "renesas,sdhi-r8a774c0",
1650				     "renesas,rcar-gen3-sdhi";
1651			reg = <0 0xee160000 0 0x2000>;
1652			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1653			clocks = <&cpg CPG_MOD 311>;
1654			max-frequency = <200000000>;
1655			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1656			resets = <&cpg 311>;
1657			status = "disabled";
1658		};
1659
1660		rpc: spi@ee200000 {
1661			compatible = "renesas,r8a774c0-rpc-if",
1662				     "renesas,rcar-gen3-rpc-if";
1663			reg = <0 0xee200000 0 0x200>,
1664			      <0 0x08000000 0 0x4000000>,
1665			      <0 0xee208000 0 0x100>;
1666			reg-names = "regs", "dirmap", "wbuf";
1667			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1668			clocks = <&cpg CPG_MOD 917>;
1669			clock-names = "rpc";
1670			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1671			resets = <&cpg 917>;
1672			#address-cells = <1>;
1673			#size-cells = <0>;
1674			status = "disabled";
1675		};
1676
1677		gic: interrupt-controller@f1010000 {
1678			compatible = "arm,gic-400";
1679			#interrupt-cells = <3>;
1680			#address-cells = <0>;
1681			interrupt-controller;
1682			reg = <0x0 0xf1010000 0 0x1000>,
1683			      <0x0 0xf1020000 0 0x20000>,
1684			      <0x0 0xf1040000 0 0x20000>,
1685			      <0x0 0xf1060000 0 0x20000>;
1686			interrupts = <GIC_PPI 9
1687					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1688			clocks = <&cpg CPG_MOD 408>;
1689			clock-names = "clk";
1690			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1691			resets = <&cpg 408>;
1692		};
1693
1694		pciec0: pcie@fe000000 {
1695			compatible = "renesas,pcie-r8a774c0",
1696				     "renesas,pcie-rcar-gen3";
1697			reg = <0 0xfe000000 0 0x80000>;
1698			#address-cells = <3>;
1699			#size-cells = <2>;
1700			bus-range = <0x00 0xff>;
1701			device_type = "pci";
1702			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1703				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1704				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1705				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1706			/* Map all possible DDR as inbound ranges */
1707			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1708			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1709				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1710				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1711			#interrupt-cells = <1>;
1712			interrupt-map-mask = <0 0 0 0>;
1713			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1714			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1715			clock-names = "pcie", "pcie_bus";
1716			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1717			resets = <&cpg 319>;
1718			status = "disabled";
1719		};
1720
1721		pciec0_ep: pcie-ep@fe000000 {
1722			compatible = "renesas,r8a774c0-pcie-ep",
1723				     "renesas,rcar-gen3-pcie-ep";
1724			reg = <0x0 0xfe000000 0 0x80000>,
1725			      <0x0 0xfe100000 0 0x100000>,
1726			      <0x0 0xfe200000 0 0x200000>,
1727			      <0x0 0x30000000 0 0x8000000>,
1728			      <0x0 0x38000000 0 0x8000000>;
1729			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1730			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1731				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1732				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1733			clocks = <&cpg CPG_MOD 319>;
1734			clock-names = "pcie";
1735			resets = <&cpg 319>;
1736			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1737			status = "disabled";
1738		};
1739
1740		vspb0: vsp@fe960000 {
1741			compatible = "renesas,vsp2";
1742			reg = <0 0xfe960000 0 0x8000>;
1743			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1744			clocks = <&cpg CPG_MOD 626>;
1745			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1746			resets = <&cpg 626>;
1747			renesas,fcp = <&fcpvb0>;
1748		};
1749
1750		vspd0: vsp@fea20000 {
1751			compatible = "renesas,vsp2";
1752			reg = <0 0xfea20000 0 0x7000>;
1753			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1754			clocks = <&cpg CPG_MOD 623>;
1755			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1756			resets = <&cpg 623>;
1757			renesas,fcp = <&fcpvd0>;
1758		};
1759
1760		vspd1: vsp@fea28000 {
1761			compatible = "renesas,vsp2";
1762			reg = <0 0xfea28000 0 0x7000>;
1763			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1764			clocks = <&cpg CPG_MOD 622>;
1765			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1766			resets = <&cpg 622>;
1767			renesas,fcp = <&fcpvd1>;
1768		};
1769
1770		vspi0: vsp@fe9a0000 {
1771			compatible = "renesas,vsp2";
1772			reg = <0 0xfe9a0000 0 0x8000>;
1773			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1774			clocks = <&cpg CPG_MOD 631>;
1775			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1776			resets = <&cpg 631>;
1777			renesas,fcp = <&fcpvi0>;
1778		};
1779
1780		fcpvb0: fcp@fe96f000 {
1781			compatible = "renesas,fcpv";
1782			reg = <0 0xfe96f000 0 0x200>;
1783			clocks = <&cpg CPG_MOD 607>;
1784			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1785			resets = <&cpg 607>;
1786			iommus = <&ipmmu_vp0 5>;
1787		};
1788
1789		fcpvd0: fcp@fea27000 {
1790			compatible = "renesas,fcpv";
1791			reg = <0 0xfea27000 0 0x200>;
1792			clocks = <&cpg CPG_MOD 603>;
1793			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1794			resets = <&cpg 603>;
1795			iommus = <&ipmmu_vi0 8>;
1796		};
1797
1798		fcpvd1: fcp@fea2f000 {
1799			compatible = "renesas,fcpv";
1800			reg = <0 0xfea2f000 0 0x200>;
1801			clocks = <&cpg CPG_MOD 602>;
1802			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1803			resets = <&cpg 602>;
1804			iommus = <&ipmmu_vi0 9>;
1805		};
1806
1807		fcpvi0: fcp@fe9af000 {
1808			compatible = "renesas,fcpv";
1809			reg = <0 0xfe9af000 0 0x200>;
1810			clocks = <&cpg CPG_MOD 611>;
1811			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1812			resets = <&cpg 611>;
1813			iommus = <&ipmmu_vp0 8>;
1814		};
1815
1816		csi40: csi2@feaa0000 {
1817			compatible = "renesas,r8a774c0-csi2";
1818			reg = <0 0xfeaa0000 0 0x10000>;
1819			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1820			clocks = <&cpg CPG_MOD 716>;
1821			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1822			resets = <&cpg 716>;
1823			status = "disabled";
1824
1825			ports {
1826				#address-cells = <1>;
1827				#size-cells = <0>;
1828
1829				port@0 {
1830					reg = <0>;
1831				};
1832
1833				port@1 {
1834					#address-cells = <1>;
1835					#size-cells = <0>;
1836
1837					reg = <1>;
1838
1839					csi40vin4: endpoint@0 {
1840						reg = <0>;
1841						remote-endpoint = <&vin4csi40>;
1842					};
1843					csi40vin5: endpoint@1 {
1844						reg = <1>;
1845						remote-endpoint = <&vin5csi40>;
1846					};
1847				};
1848			};
1849		};
1850
1851		du: display@feb00000 {
1852			compatible = "renesas,du-r8a774c0";
1853			reg = <0 0xfeb00000 0 0x40000>;
1854			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1855				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1856			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1857			clock-names = "du.0", "du.1";
1858			resets = <&cpg 724>;
1859			reset-names = "du.0";
1860			renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1861
1862			status = "disabled";
1863
1864			ports {
1865				#address-cells = <1>;
1866				#size-cells = <0>;
1867
1868				port@0 {
1869					reg = <0>;
1870					du_out_rgb: endpoint {
1871					};
1872				};
1873
1874				port@1 {
1875					reg = <1>;
1876					du_out_lvds0: endpoint {
1877						remote-endpoint = <&lvds0_in>;
1878					};
1879				};
1880
1881				port@2 {
1882					reg = <2>;
1883					du_out_lvds1: endpoint {
1884						remote-endpoint = <&lvds1_in>;
1885					};
1886				};
1887			};
1888		};
1889
1890		lvds0: lvds-encoder@feb90000 {
1891			compatible = "renesas,r8a774c0-lvds";
1892			reg = <0 0xfeb90000 0 0x20>;
1893			clocks = <&cpg CPG_MOD 727>;
1894			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1895			resets = <&cpg 727>;
1896			status = "disabled";
1897
1898			renesas,companion = <&lvds1>;
1899
1900			ports {
1901				#address-cells = <1>;
1902				#size-cells = <0>;
1903
1904				port@0 {
1905					reg = <0>;
1906					lvds0_in: endpoint {
1907						remote-endpoint = <&du_out_lvds0>;
1908					};
1909				};
1910
1911				port@1 {
1912					reg = <1>;
1913					lvds0_out: endpoint {
1914					};
1915				};
1916			};
1917		};
1918
1919		lvds1: lvds-encoder@feb90100 {
1920			compatible = "renesas,r8a774c0-lvds";
1921			reg = <0 0xfeb90100 0 0x20>;
1922			clocks = <&cpg CPG_MOD 727>;
1923			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1924			resets = <&cpg 726>;
1925			status = "disabled";
1926
1927			ports {
1928				#address-cells = <1>;
1929				#size-cells = <0>;
1930
1931				port@0 {
1932					reg = <0>;
1933					lvds1_in: endpoint {
1934						remote-endpoint = <&du_out_lvds1>;
1935					};
1936				};
1937
1938				port@1 {
1939					reg = <1>;
1940					lvds1_out: endpoint {
1941					};
1942				};
1943			};
1944		};
1945
1946		prr: chipid@fff00044 {
1947			compatible = "renesas,prr";
1948			reg = <0 0xfff00044 0 4>;
1949		};
1950	};
1951
1952	thermal-zones {
1953		cpu-thermal {
1954			polling-delay-passive = <250>;
1955			polling-delay = <0>;
1956			thermal-sensors = <&thermal 0>;
1957			sustainable-power = <717>;
1958
1959			cooling-maps {
1960				map0 {
1961					trip = <&target>;
1962					cooling-device = <&a53_0 0 2>;
1963					contribution = <1024>;
1964				};
1965			};
1966
1967			trips {
1968				sensor1_crit: sensor1-crit {
1969					temperature = <120000>;
1970					hysteresis = <2000>;
1971					type = "critical";
1972				};
1973
1974				target: trip-point1 {
1975					temperature = <100000>;
1976					hysteresis = <2000>;
1977					type = "passive";
1978				};
1979			};
1980		};
1981	};
1982
1983	timer {
1984		compatible = "arm,armv8-timer";
1985		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1986				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1987				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1988				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1989	};
1990
1991	/* External USB clocks - can be overridden by the board */
1992	usb3s0_clk: usb3s0 {
1993		compatible = "fixed-clock";
1994		#clock-cells = <0>;
1995		clock-frequency = <0>;
1996	};
1997
1998	usb_extal_clk: usb_extal {
1999		compatible = "fixed-clock";
2000		#clock-cells = <0>;
2001		clock-frequency = <0>;
2002	};
2003};
2004