1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2L SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/r9a07g054-cpg.h>
10
11/ {
12	compatible = "renesas,r9a07g054";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	audio_clk1: audio1-clk {
17		compatible = "fixed-clock";
18		#clock-cells = <0>;
19		/* This value must be overridden by boards that provide it */
20		clock-frequency = <0>;
21	};
22
23	audio_clk2: audio2-clk {
24		compatible = "fixed-clock";
25		#clock-cells = <0>;
26		/* This value must be overridden by boards that provide it */
27		clock-frequency = <0>;
28	};
29
30	/* External CAN clock - to be overridden by boards that provide it */
31	can_clk: can-clk {
32		compatible = "fixed-clock";
33		#clock-cells = <0>;
34		clock-frequency = <0>;
35	};
36
37	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38	extal_clk: extal-clk {
39		compatible = "fixed-clock";
40		#clock-cells = <0>;
41		/* This value must be overridden by the board */
42		clock-frequency = <0>;
43	};
44
45	cluster0_opp: opp-table-0 {
46		compatible = "operating-points-v2";
47		opp-shared;
48
49		opp-150000000 {
50			opp-hz = /bits/ 64 <150000000>;
51			opp-microvolt = <1100000>;
52			clock-latency-ns = <300000>;
53		};
54		opp-300000000 {
55			opp-hz = /bits/ 64 <300000000>;
56			opp-microvolt = <1100000>;
57			clock-latency-ns = <300000>;
58		};
59		opp-600000000 {
60			opp-hz = /bits/ 64 <600000000>;
61			opp-microvolt = <1100000>;
62			clock-latency-ns = <300000>;
63		};
64		opp-1200000000 {
65			opp-hz = /bits/ 64 <1200000000>;
66			opp-microvolt = <1100000>;
67			clock-latency-ns = <300000>;
68			opp-suspend;
69		};
70	};
71
72	cpus {
73		#address-cells = <1>;
74		#size-cells = <0>;
75
76		cpu-map {
77			cluster0 {
78				core0 {
79					cpu = <&cpu0>;
80				};
81				core1 {
82					cpu = <&cpu1>;
83				};
84			};
85		};
86
87		cpu0: cpu@0 {
88			compatible = "arm,cortex-a55";
89			reg = <0>;
90			device_type = "cpu";
91			#cooling-cells = <2>;
92			next-level-cache = <&L3_CA55>;
93			enable-method = "psci";
94			clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
95			operating-points-v2 = <&cluster0_opp>;
96		};
97
98		cpu1: cpu@100 {
99			compatible = "arm,cortex-a55";
100			reg = <0x100>;
101			device_type = "cpu";
102			next-level-cache = <&L3_CA55>;
103			enable-method = "psci";
104			clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
105			operating-points-v2 = <&cluster0_opp>;
106		};
107
108		L3_CA55: cache-controller-0 {
109			compatible = "cache";
110			cache-unified;
111			cache-size = <0x40000>;
112			cache-level = <3>;
113		};
114	};
115
116	gpu_opp_table: opp-table-1 {
117		compatible = "operating-points-v2";
118
119		opp-500000000 {
120			opp-hz = /bits/ 64 <500000000>;
121			opp-microvolt = <1100000>;
122		};
123
124		opp-400000000 {
125			opp-hz = /bits/ 64 <400000000>;
126			opp-microvolt = <1100000>;
127		};
128
129		opp-250000000 {
130			opp-hz = /bits/ 64 <250000000>;
131			opp-microvolt = <1100000>;
132		};
133
134		opp-200000000 {
135			opp-hz = /bits/ 64 <200000000>;
136			opp-microvolt = <1100000>;
137		};
138
139		opp-125000000 {
140			opp-hz = /bits/ 64 <125000000>;
141			opp-microvolt = <1100000>;
142		};
143
144		opp-100000000 {
145			opp-hz = /bits/ 64 <100000000>;
146			opp-microvolt = <1100000>;
147		};
148
149		opp-62500000 {
150			opp-hz = /bits/ 64 <62500000>;
151			opp-microvolt = <1100000>;
152		};
153
154		opp-50000000 {
155			opp-hz = /bits/ 64 <50000000>;
156			opp-microvolt = <1100000>;
157		};
158	};
159
160	pmu {
161		compatible = "arm,cortex-a55-pmu";
162		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
163	};
164
165	psci {
166		compatible = "arm,psci-1.0", "arm,psci-0.2";
167		method = "smc";
168	};
169
170	soc: soc {
171		compatible = "simple-bus";
172		interrupt-parent = <&gic>;
173		#address-cells = <2>;
174		#size-cells = <2>;
175		ranges;
176
177		mtu3: timer@10001200 {
178			compatible = "renesas,r9a07g054-mtu3",
179				     "renesas,rz-mtu3";
180			reg = <0 0x10001200 0 0xb00>;
181			interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
182				     <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
183				     <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
184				     <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
185				     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
186				     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
187				     <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
188				     <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
189				     <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
190				     <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
191				     <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
192				     <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
193				     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
194				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
195				     <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
196				     <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
197				     <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
198				     <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
199				     <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
200				     <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
201				     <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
202				     <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
203				     <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
204				     <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
205				     <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
206				     <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
207				     <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
208				     <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
209				     <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
210				     <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
211				     <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
212				     <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
213				     <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
214				     <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
215				     <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
216				     <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
217				     <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
218				     <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
219				     <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
220				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
221				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
222				     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
223				     <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
224				     <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
225			interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
226					  "tciv0", "tgie0", "tgif0",
227					  "tgia1", "tgib1", "tciv1", "tciu1",
228					  "tgia2", "tgib2", "tciv2", "tciu2",
229					  "tgia3", "tgib3", "tgic3", "tgid3",
230					  "tciv3",
231					  "tgia4", "tgib4", "tgic4", "tgid4",
232					  "tciv4",
233					  "tgiu5", "tgiv5", "tgiw5",
234					  "tgia6", "tgib6", "tgic6", "tgid6",
235					  "tciv6",
236					  "tgia7", "tgib7", "tgic7", "tgid7",
237					  "tciv7",
238					  "tgia8", "tgib8", "tgic8", "tgid8",
239					  "tciv8", "tciu8";
240			clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241			power-domains = <&cpg>;
242			resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
243			#pwm-cells = <2>;
244			status = "disabled";
245		};
246
247		ssi0: ssi@10049c00 {
248			compatible = "renesas,r9a07g054-ssi",
249				     "renesas,rz-ssi";
250			reg = <0 0x10049c00 0 0x400>;
251			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252				     <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253				     <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
254			interrupt-names = "int_req", "dma_rx", "dma_tx";
255			clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256				 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
257				 <&audio_clk1>, <&audio_clk2>;
258			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259			resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
260			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261			dma-names = "tx", "rx";
262			power-domains = <&cpg>;
263			#sound-dai-cells = <0>;
264			status = "disabled";
265		};
266
267		ssi1: ssi@1004a000 {
268			compatible = "renesas,r9a07g054-ssi",
269				     "renesas,rz-ssi";
270			reg = <0 0x1004a000 0 0x400>;
271			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272				     <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273				     <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
274			interrupt-names = "int_req", "dma_rx", "dma_tx";
275			clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
276				 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
277				 <&audio_clk1>, <&audio_clk2>;
278			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279			resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
280			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281			dma-names = "tx", "rx";
282			power-domains = <&cpg>;
283			#sound-dai-cells = <0>;
284			status = "disabled";
285		};
286
287		ssi2: ssi@1004a400 {
288			compatible = "renesas,r9a07g054-ssi",
289				     "renesas,rz-ssi";
290			reg = <0 0x1004a400 0 0x400>;
291			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
292				     <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293			interrupt-names = "int_req", "dma_rt";
294			clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
295				 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
296				 <&audio_clk1>, <&audio_clk2>;
297			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298			resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
299			dmas = <&dmac 0x265f>;
300			dma-names = "rt";
301			power-domains = <&cpg>;
302			#sound-dai-cells = <0>;
303			status = "disabled";
304		};
305
306		ssi3: ssi@1004a800 {
307			compatible = "renesas,r9a07g054-ssi",
308				     "renesas,rz-ssi";
309			reg = <0 0x1004a800 0 0x400>;
310			interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311				     <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312				     <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
313			interrupt-names = "int_req", "dma_rx", "dma_tx";
314			clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
315				 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
316				 <&audio_clk1>, <&audio_clk2>;
317			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318			resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
319			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320			dma-names = "tx", "rx";
321			power-domains = <&cpg>;
322			#sound-dai-cells = <0>;
323			status = "disabled";
324		};
325
326		spi0: spi@1004ac00 {
327			compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
328			reg = <0 0x1004ac00 0 0x400>;
329			interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
330				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
331				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
332			interrupt-names = "error", "rx", "tx";
333			clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
334			resets = <&cpg R9A07G054_RSPI0_RST>;
335			dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
336			dma-names = "tx", "rx";
337			power-domains = <&cpg>;
338			num-cs = <1>;
339			#address-cells = <1>;
340			#size-cells = <0>;
341			status = "disabled";
342		};
343
344		spi1: spi@1004b000 {
345			compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
346			reg = <0 0x1004b000 0 0x400>;
347			interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
348				     <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
349				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
350			interrupt-names = "error", "rx", "tx";
351			clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
352			resets = <&cpg R9A07G054_RSPI1_RST>;
353			dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
354			dma-names = "tx", "rx";
355			power-domains = <&cpg>;
356			num-cs = <1>;
357			#address-cells = <1>;
358			#size-cells = <0>;
359			status = "disabled";
360		};
361
362		spi2: spi@1004b400 {
363			compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
364			reg = <0 0x1004b400 0 0x400>;
365			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
366				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
367				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
368			interrupt-names = "error", "rx", "tx";
369			clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
370			resets = <&cpg R9A07G054_RSPI2_RST>;
371			dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
372			dma-names = "tx", "rx";
373			power-domains = <&cpg>;
374			num-cs = <1>;
375			#address-cells = <1>;
376			#size-cells = <0>;
377			status = "disabled";
378		};
379
380		scif0: serial@1004b800 {
381			compatible = "renesas,scif-r9a07g054",
382				     "renesas,scif-r9a07g044";
383			reg = <0 0x1004b800 0 0x400>;
384			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
385				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
386				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
387				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
388				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
389				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
390			interrupt-names = "eri", "rxi", "txi",
391					  "bri", "dri", "tei";
392			clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
393			clock-names = "fck";
394			power-domains = <&cpg>;
395			resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
396			status = "disabled";
397		};
398
399		scif1: serial@1004bc00 {
400			compatible = "renesas,scif-r9a07g054",
401				     "renesas,scif-r9a07g044";
402			reg = <0 0x1004bc00 0 0x400>;
403			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
404				     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
405				     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
406				     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
407				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
408				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
409			interrupt-names = "eri", "rxi", "txi",
410					  "bri", "dri", "tei";
411			clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
412			clock-names = "fck";
413			power-domains = <&cpg>;
414			resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
415			status = "disabled";
416		};
417
418		scif2: serial@1004c000 {
419			compatible = "renesas,scif-r9a07g054",
420				     "renesas,scif-r9a07g044";
421			reg = <0 0x1004c000 0 0x400>;
422			interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
423				     <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
424				     <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
425				     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
426				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
427				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
428			interrupt-names = "eri", "rxi", "txi",
429					  "bri", "dri", "tei";
430			clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
431			clock-names = "fck";
432			power-domains = <&cpg>;
433			resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
434			status = "disabled";
435		};
436
437		scif3: serial@1004c400 {
438			compatible = "renesas,scif-r9a07g054",
439				     "renesas,scif-r9a07g044";
440			reg = <0 0x1004c400 0 0x400>;
441			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
442				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
443				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
444				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
445				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
446				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
447			interrupt-names = "eri", "rxi", "txi",
448					  "bri", "dri", "tei";
449			clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
450			clock-names = "fck";
451			power-domains = <&cpg>;
452			resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
453			status = "disabled";
454		};
455
456		scif4: serial@1004c800 {
457			compatible = "renesas,scif-r9a07g054",
458				     "renesas,scif-r9a07g044";
459			reg = <0 0x1004c800 0 0x400>;
460			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
461				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
462				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
463				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
464				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
465				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
466			interrupt-names = "eri", "rxi", "txi",
467					  "bri", "dri", "tei";
468			clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
469			clock-names = "fck";
470			power-domains = <&cpg>;
471			resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
472			status = "disabled";
473		};
474
475		sci0: serial@1004d000 {
476			compatible = "renesas,r9a07g054-sci", "renesas,sci";
477			reg = <0 0x1004d000 0 0x400>;
478			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
479				     <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
480				     <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
481				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
482			interrupt-names = "eri", "rxi", "txi", "tei";
483			clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
484			clock-names = "fck";
485			power-domains = <&cpg>;
486			resets = <&cpg R9A07G054_SCI0_RST>;
487			status = "disabled";
488		};
489
490		sci1: serial@1004d400 {
491			compatible = "renesas,r9a07g054-sci", "renesas,sci";
492			reg = <0 0x1004d400 0 0x400>;
493			interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
494				     <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
495				     <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
496				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
497			interrupt-names = "eri", "rxi", "txi", "tei";
498			clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
499			clock-names = "fck";
500			power-domains = <&cpg>;
501			resets = <&cpg R9A07G054_SCI1_RST>;
502			status = "disabled";
503		};
504
505		canfd: can@10050000 {
506			compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
507			reg = <0 0x10050000 0 0x8000>;
508			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
509				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
510				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
511				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
512				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
513				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
514				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
515				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
516			interrupt-names = "g_err", "g_recc",
517					  "ch0_err", "ch0_rec", "ch0_trx",
518					  "ch1_err", "ch1_rec", "ch1_trx";
519			clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
520				 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
521				 <&can_clk>;
522			clock-names = "fck", "canfd", "can_clk";
523			assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
524			assigned-clock-rates = <50000000>;
525			resets = <&cpg R9A07G054_CANFD_RSTP_N>,
526				 <&cpg R9A07G054_CANFD_RSTC_N>;
527			reset-names = "rstp_n", "rstc_n";
528			power-domains = <&cpg>;
529			status = "disabled";
530
531			channel0 {
532				status = "disabled";
533			};
534			channel1 {
535				status = "disabled";
536			};
537		};
538
539		i2c0: i2c@10058000 {
540			#address-cells = <1>;
541			#size-cells = <0>;
542			compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
543			reg = <0 0x10058000 0 0x400>;
544			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
545				     <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
546				     <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
547				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
548				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
549				     <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
550				     <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
551				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
552			interrupt-names = "tei", "ri", "ti", "spi", "sti",
553					  "naki", "ali", "tmoi";
554			clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
555			clock-frequency = <100000>;
556			resets = <&cpg R9A07G054_I2C0_MRST>;
557			power-domains = <&cpg>;
558			status = "disabled";
559		};
560
561		i2c1: i2c@10058400 {
562			#address-cells = <1>;
563			#size-cells = <0>;
564			compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
565			reg = <0 0x10058400 0 0x400>;
566			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
567				     <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
568				     <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
569				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
570				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
571				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
572				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
573				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
574			interrupt-names = "tei", "ri", "ti", "spi", "sti",
575					  "naki", "ali", "tmoi";
576			clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
577			clock-frequency = <100000>;
578			resets = <&cpg R9A07G054_I2C1_MRST>;
579			power-domains = <&cpg>;
580			status = "disabled";
581		};
582
583		i2c2: i2c@10058800 {
584			#address-cells = <1>;
585			#size-cells = <0>;
586			compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
587			reg = <0 0x10058800 0 0x400>;
588			interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
589				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
590				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
591				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
592				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
593				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
594				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
595				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
596			interrupt-names = "tei", "ri", "ti", "spi", "sti",
597					  "naki", "ali", "tmoi";
598			clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
599			clock-frequency = <100000>;
600			resets = <&cpg R9A07G054_I2C2_MRST>;
601			power-domains = <&cpg>;
602			status = "disabled";
603		};
604
605		i2c3: i2c@10058c00 {
606			#address-cells = <1>;
607			#size-cells = <0>;
608			compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
609			reg = <0 0x10058c00 0 0x400>;
610			interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
611				     <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
612				     <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
613				     <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
614				     <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
615				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
616				     <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
617				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
618			interrupt-names = "tei", "ri", "ti", "spi", "sti",
619					  "naki", "ali", "tmoi";
620			clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
621			clock-frequency = <100000>;
622			resets = <&cpg R9A07G054_I2C3_MRST>;
623			power-domains = <&cpg>;
624			status = "disabled";
625		};
626
627		adc: adc@10059000 {
628			compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
629			reg = <0 0x10059000 0 0x400>;
630			interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
631			clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
632				 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
633			clock-names = "adclk", "pclk";
634			resets = <&cpg R9A07G054_ADC_PRESETN>,
635				 <&cpg R9A07G054_ADC_ADRST_N>;
636			reset-names = "presetn", "adrst-n";
637			power-domains = <&cpg>;
638			status = "disabled";
639
640			#address-cells = <1>;
641			#size-cells = <0>;
642
643			channel@0 {
644				reg = <0>;
645			};
646			channel@1 {
647				reg = <1>;
648			};
649			channel@2 {
650				reg = <2>;
651			};
652			channel@3 {
653				reg = <3>;
654			};
655			channel@4 {
656				reg = <4>;
657			};
658			channel@5 {
659				reg = <5>;
660			};
661			channel@6 {
662				reg = <6>;
663			};
664			channel@7 {
665				reg = <7>;
666			};
667		};
668
669		tsu: thermal@10059400 {
670			compatible = "renesas,r9a07g054-tsu",
671				     "renesas,rzg2l-tsu";
672			reg = <0 0x10059400 0 0x400>;
673			clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
674			resets = <&cpg R9A07G054_TSU_PRESETN>;
675			power-domains = <&cpg>;
676			#thermal-sensor-cells = <1>;
677		};
678
679		sbc: spi@10060000 {
680			compatible = "renesas,r9a07g054-rpc-if",
681				     "renesas,rzg2l-rpc-if";
682			reg = <0 0x10060000 0 0x10000>,
683			      <0 0x20000000 0 0x10000000>,
684			      <0 0x10070000 0 0x10000>;
685			reg-names = "regs", "dirmap", "wbuf";
686			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
687			clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
688				 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
689			resets = <&cpg R9A07G054_SPI_RST>;
690			power-domains = <&cpg>;
691			#address-cells = <1>;
692			#size-cells = <0>;
693			status = "disabled";
694		};
695
696		cru: video@10830000 {
697			compatible = "renesas,r9a07g054-cru", "renesas,rzg2l-cru";
698			reg = <0 0x10830000 0 0x400>;
699			clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
700				 <&cpg CPG_MOD R9A07G054_CRU_PCLK>,
701				 <&cpg CPG_MOD R9A07G054_CRU_ACLK>;
702			clock-names = "video", "apb", "axi";
703			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
704				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
705				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
706			interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
707			resets = <&cpg R9A07G054_CRU_PRESETN>,
708				 <&cpg R9A07G054_CRU_ARESETN>;
709			reset-names = "presetn", "aresetn";
710			power-domains = <&cpg>;
711			status = "disabled";
712
713			ports {
714				#address-cells = <1>;
715				#size-cells = <0>;
716
717				port@0 {
718					#address-cells = <1>;
719					#size-cells = <0>;
720
721					reg = <0>;
722					cruparallel: endpoint@0 {
723						reg = <0>;
724					};
725				};
726
727				port@1 {
728					#address-cells = <1>;
729					#size-cells = <0>;
730
731					reg = <1>;
732					crucsi2: endpoint@0 {
733						reg = <0>;
734						remote-endpoint = <&csi2cru>;
735					};
736				};
737			};
738		};
739
740		csi2: csi2@10830400 {
741			compatible = "renesas,r9a07g054-csi2", "renesas,rzg2l-csi2";
742			reg = <0 0x10830400 0 0xfc00>;
743			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
744			clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>,
745				 <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
746				 <&cpg CPG_MOD R9A07G054_CRU_PCLK>;
747			clock-names = "system", "video", "apb";
748			resets = <&cpg R9A07G054_CRU_PRESETN>,
749				 <&cpg R9A07G054_CRU_CMN_RSTB>;
750			reset-names = "presetn", "cmn-rstb";
751			power-domains = <&cpg>;
752			status = "disabled";
753
754			ports {
755				#address-cells = <1>;
756				#size-cells = <0>;
757
758				port@0 {
759					reg = <0>;
760				};
761
762				port@1 {
763					#address-cells = <1>;
764					#size-cells = <0>;
765					reg = <1>;
766
767					csi2cru: endpoint@0 {
768						reg = <0>;
769						remote-endpoint = <&crucsi2>;
770					};
771				};
772			};
773		};
774
775		dsi: dsi@10850000 {
776			compatible = "renesas,r9a07g054-mipi-dsi",
777				     "renesas,rzg2l-mipi-dsi";
778			reg = <0 0x10850000 0 0x20000>;
779			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
780				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
781				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
782				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
783				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
784				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
785				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
786			interrupt-names = "seq0", "seq1", "vin1", "rcv",
787					  "ferr", "ppi", "debug";
788			clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>,
789				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>,
790				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>,
791				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>,
792				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>,
793				 <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>;
794			clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
795			resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>,
796				 <&cpg R9A07G054_MIPI_DSI_ARESET_N>,
797				 <&cpg R9A07G054_MIPI_DSI_PRESET_N>;
798			reset-names = "rst", "arst", "prst";
799			power-domains = <&cpg>;
800			status = "disabled";
801		};
802
803		vspd: vsp@10870000 {
804			compatible = "renesas,r9a07g054-vsp2",
805				     "renesas,r9a07g044-vsp2";
806			reg = <0 0x10870000 0 0x10000>;
807			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
808			clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
809				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
810				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
811			clock-names = "aclk", "pclk", "vclk";
812			power-domains = <&cpg>;
813			resets = <&cpg R9A07G054_LCDC_RESET_N>;
814			renesas,fcp = <&fcpvd>;
815		};
816
817		fcpvd: fcp@10880000 {
818			compatible = "renesas,r9a07g054-fcpvd",
819				     "renesas,fcpv";
820			reg = <0 0x10880000 0 0x10000>;
821			clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
822				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
823				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
824			clock-names = "aclk", "pclk", "vclk";
825			power-domains = <&cpg>;
826			resets = <&cpg R9A07G054_LCDC_RESET_N>;
827		};
828
829		cpg: clock-controller@11010000 {
830			compatible = "renesas,r9a07g054-cpg";
831			reg = <0 0x11010000 0 0x10000>;
832			clocks = <&extal_clk>;
833			clock-names = "extal";
834			#clock-cells = <2>;
835			#reset-cells = <1>;
836			#power-domain-cells = <0>;
837		};
838
839		sysc: system-controller@11020000 {
840			compatible = "renesas,r9a07g054-sysc";
841			reg = <0 0x11020000 0 0x10000>;
842			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
843				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
844				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
845				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
846			interrupt-names = "lpm_int", "ca55stbydone_int",
847					  "cm33stbyr_int", "ca55_deny";
848			status = "disabled";
849		};
850
851		pinctrl: pinctrl@11030000 {
852			compatible = "renesas,r9a07g054-pinctrl",
853				     "renesas,r9a07g044-pinctrl";
854			reg = <0 0x11030000 0 0x10000>;
855			gpio-controller;
856			#gpio-cells = <2>;
857			#interrupt-cells = <2>;
858			interrupt-parent = <&irqc>;
859			interrupt-controller;
860			gpio-ranges = <&pinctrl 0 0 392>;
861			clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
862			power-domains = <&cpg>;
863			resets = <&cpg R9A07G054_GPIO_RSTN>,
864				 <&cpg R9A07G054_GPIO_PORT_RESETN>,
865				 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
866		};
867
868		irqc: interrupt-controller@110a0000 {
869			compatible = "renesas,r9a07g054-irqc",
870				     "renesas,rzg2l-irqc";
871			#interrupt-cells = <2>;
872			#address-cells = <0>;
873			interrupt-controller;
874			reg = <0 0x110a0000 0 0x10000>;
875			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
876				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
877				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
878				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
879				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
880				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
881				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
882				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
883				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
884				     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
885				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
886				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
887				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
888				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
889				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
890				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
891				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
892				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
893				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
894				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
895				     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
896				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
897				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
898				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
899				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
900				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
901				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
902				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
903				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
904				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
905				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
906				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
907				     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
908				     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
909				     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
910				     <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
911				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
912				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
913				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
914				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
915				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
916			clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
917				 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
918			clock-names = "clk", "pclk";
919			power-domains = <&cpg>;
920			resets = <&cpg R9A07G054_IA55_RESETN>;
921		};
922
923		dmac: dma-controller@11820000 {
924			compatible = "renesas,r9a07g054-dmac",
925				     "renesas,rz-dmac";
926			reg = <0 0x11820000 0 0x10000>,
927			      <0 0x11830000 0 0x10000>;
928			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
929				     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
930				     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
931				     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
932				     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
933				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
934				     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
935				     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
936				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
937				     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
938				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
939				     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
940				     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
941				     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
942				     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
943				     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
944				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
945			interrupt-names = "error",
946					  "ch0", "ch1", "ch2", "ch3",
947					  "ch4", "ch5", "ch6", "ch7",
948					  "ch8", "ch9", "ch10", "ch11",
949					  "ch12", "ch13", "ch14", "ch15";
950			clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
951				 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
952			clock-names = "main", "register";
953			power-domains = <&cpg>;
954			resets = <&cpg R9A07G054_DMAC_ARESETN>,
955				 <&cpg R9A07G054_DMAC_RST_ASYNC>;
956			reset-names = "arst", "rst_async";
957			#dma-cells = <1>;
958			dma-channels = <16>;
959		};
960
961		gpu: gpu@11840000 {
962			compatible = "renesas,r9a07g054-mali",
963				     "arm,mali-bifrost";
964			reg = <0x0 0x11840000 0x0 0x10000>;
965			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
966				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
967				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
968				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
969			interrupt-names = "job", "mmu", "gpu", "event";
970			clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
971				 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
972				 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
973			clock-names = "gpu", "bus", "bus_ace";
974			power-domains = <&cpg>;
975			resets = <&cpg R9A07G054_GPU_RESETN>,
976				 <&cpg R9A07G054_GPU_AXI_RESETN>,
977				 <&cpg R9A07G054_GPU_ACE_RESETN>;
978			reset-names = "rst", "axi_rst", "ace_rst";
979			operating-points-v2 = <&gpu_opp_table>;
980		};
981
982		gic: interrupt-controller@11900000 {
983			compatible = "arm,gic-v3";
984			#interrupt-cells = <3>;
985			#address-cells = <0>;
986			interrupt-controller;
987			reg = <0x0 0x11900000 0 0x40000>,
988			      <0x0 0x11940000 0 0x60000>;
989			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
990		};
991
992		sdhi0: mmc@11c00000 {
993			compatible = "renesas,sdhi-r9a07g054",
994				     "renesas,rcar-gen3-sdhi";
995			reg = <0x0 0x11c00000 0 0x10000>;
996			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
997				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
998			clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
999				 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1000				 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1001				 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1002			clock-names = "core", "clkh", "cd", "aclk";
1003			resets = <&cpg R9A07G054_SDHI0_IXRST>;
1004			power-domains = <&cpg>;
1005			status = "disabled";
1006		};
1007
1008		sdhi1: mmc@11c10000 {
1009			compatible = "renesas,sdhi-r9a07g054",
1010				     "renesas,rcar-gen3-sdhi";
1011			reg = <0x0 0x11c10000 0 0x10000>;
1012			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1013				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1014			clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1015				 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1016				 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1017				 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1018			clock-names = "core", "clkh", "cd", "aclk";
1019			resets = <&cpg R9A07G054_SDHI1_IXRST>;
1020			power-domains = <&cpg>;
1021			status = "disabled";
1022		};
1023
1024		eth0: ethernet@11c20000 {
1025			compatible = "renesas,r9a07g054-gbeth",
1026				     "renesas,rzg2l-gbeth";
1027			reg = <0 0x11c20000 0 0x10000>;
1028			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1029				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1030				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1031			interrupt-names = "mux", "fil", "arp_ns";
1032			phy-mode = "rgmii";
1033			clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
1034				 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
1035				 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1036			clock-names = "axi", "chi", "refclk";
1037			resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
1038			power-domains = <&cpg>;
1039			#address-cells = <1>;
1040			#size-cells = <0>;
1041			status = "disabled";
1042		};
1043
1044		eth1: ethernet@11c30000 {
1045			compatible = "renesas,r9a07g054-gbeth",
1046				     "renesas,rzg2l-gbeth";
1047			reg = <0 0x11c30000 0 0x10000>;
1048			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1049				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1050				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1051			interrupt-names = "mux", "fil", "arp_ns";
1052			phy-mode = "rgmii";
1053			clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
1054				 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
1055				 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1056			clock-names = "axi", "chi", "refclk";
1057			resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
1058			power-domains = <&cpg>;
1059			#address-cells = <1>;
1060			#size-cells = <0>;
1061			status = "disabled";
1062		};
1063
1064		phyrst: usbphy-ctrl@11c40000 {
1065			compatible = "renesas,r9a07g054-usbphy-ctrl",
1066				     "renesas,rzg2l-usbphy-ctrl";
1067			reg = <0 0x11c40000 0 0x10000>;
1068			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
1069			resets = <&cpg R9A07G054_USB_PRESETN>;
1070			power-domains = <&cpg>;
1071			#reset-cells = <1>;
1072			status = "disabled";
1073		};
1074
1075		ohci0: usb@11c50000 {
1076			compatible = "generic-ohci";
1077			reg = <0 0x11c50000 0 0x100>;
1078			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1079			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1080				 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1081			resets = <&phyrst 0>,
1082				 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1083			phys = <&usb2_phy0 1>;
1084			phy-names = "usb";
1085			power-domains = <&cpg>;
1086			status = "disabled";
1087		};
1088
1089		ohci1: usb@11c70000 {
1090			compatible = "generic-ohci";
1091			reg = <0 0x11c70000 0 0x100>;
1092			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1093			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1094				 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1095			resets = <&phyrst 1>,
1096				 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1097			phys = <&usb2_phy1 1>;
1098			phy-names = "usb";
1099			power-domains = <&cpg>;
1100			status = "disabled";
1101		};
1102
1103		ehci0: usb@11c50100 {
1104			compatible = "generic-ehci";
1105			reg = <0 0x11c50100 0 0x100>;
1106			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1107			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1108				 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1109			resets = <&phyrst 0>,
1110				 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1111			phys = <&usb2_phy0 2>;
1112			phy-names = "usb";
1113			companion = <&ohci0>;
1114			power-domains = <&cpg>;
1115			status = "disabled";
1116		};
1117
1118		ehci1: usb@11c70100 {
1119			compatible = "generic-ehci";
1120			reg = <0 0x11c70100 0 0x100>;
1121			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1122			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1123				 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1124			resets = <&phyrst 1>,
1125				 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1126			phys = <&usb2_phy1 2>;
1127			phy-names = "usb";
1128			companion = <&ohci1>;
1129			power-domains = <&cpg>;
1130			status = "disabled";
1131		};
1132
1133		usb2_phy0: usb-phy@11c50200 {
1134			compatible = "renesas,usb2-phy-r9a07g054",
1135				     "renesas,rzg2l-usb2-phy";
1136			reg = <0 0x11c50200 0 0x700>;
1137			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1138			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1139				 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1140			resets = <&phyrst 0>;
1141			#phy-cells = <1>;
1142			power-domains = <&cpg>;
1143			status = "disabled";
1144		};
1145
1146		usb2_phy1: usb-phy@11c70200 {
1147			compatible = "renesas,usb2-phy-r9a07g054",
1148				     "renesas,rzg2l-usb2-phy";
1149			reg = <0 0x11c70200 0 0x700>;
1150			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1151			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1152				 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1153			resets = <&phyrst 1>;
1154			#phy-cells = <1>;
1155			power-domains = <&cpg>;
1156			status = "disabled";
1157		};
1158
1159		hsusb: usb@11c60000 {
1160			compatible = "renesas,usbhs-r9a07g054",
1161				     "renesas,rza2-usbhs";
1162			reg = <0 0x11c60000 0 0x10000>;
1163			interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1164				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1165				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1166				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1167			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1168				 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
1169			resets = <&phyrst 0>,
1170				 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
1171			renesas,buswait = <7>;
1172			phys = <&usb2_phy0 3>;
1173			phy-names = "usb";
1174			power-domains = <&cpg>;
1175			status = "disabled";
1176		};
1177
1178		wdt0: watchdog@12800800 {
1179			compatible = "renesas,r9a07g054-wdt",
1180				     "renesas,rzg2l-wdt";
1181			reg = <0 0x12800800 0 0x400>;
1182			clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
1183				 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
1184			clock-names = "pclk", "oscclk";
1185			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1186				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1187			interrupt-names = "wdt", "perrout";
1188			resets = <&cpg R9A07G054_WDT0_PRESETN>;
1189			power-domains = <&cpg>;
1190			status = "disabled";
1191		};
1192
1193		wdt1: watchdog@12800c00 {
1194			compatible = "renesas,r9a07g054-wdt",
1195				     "renesas,rzg2l-wdt";
1196			reg = <0 0x12800C00 0 0x400>;
1197			clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
1198				 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
1199			clock-names = "pclk", "oscclk";
1200			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1201				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1202			interrupt-names = "wdt", "perrout";
1203			resets = <&cpg R9A07G054_WDT1_PRESETN>;
1204			power-domains = <&cpg>;
1205			status = "disabled";
1206		};
1207
1208		ostm0: timer@12801000 {
1209			compatible = "renesas,r9a07g054-ostm",
1210				     "renesas,ostm";
1211			reg = <0x0 0x12801000 0x0 0x400>;
1212			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1213			clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1214			resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1215			power-domains = <&cpg>;
1216			status = "disabled";
1217		};
1218
1219		ostm1: timer@12801400 {
1220			compatible = "renesas,r9a07g054-ostm",
1221				     "renesas,ostm";
1222			reg = <0x0 0x12801400 0x0 0x400>;
1223			interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1224			clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1225			resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1226			power-domains = <&cpg>;
1227			status = "disabled";
1228		};
1229
1230		ostm2: timer@12801800 {
1231			compatible = "renesas,r9a07g054-ostm",
1232				     "renesas,ostm";
1233			reg = <0x0 0x12801800 0x0 0x400>;
1234			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1235			clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1236			resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1237			power-domains = <&cpg>;
1238			status = "disabled";
1239		};
1240	};
1241
1242	thermal-zones {
1243		cpu-thermal {
1244			polling-delay-passive = <250>;
1245			polling-delay = <1000>;
1246			thermal-sensors = <&tsu 0>;
1247			sustainable-power = <717>;
1248
1249			cooling-maps {
1250				map0 {
1251					trip = <&target>;
1252					cooling-device = <&cpu0 0 2>;
1253					contribution = <1024>;
1254				};
1255			};
1256
1257			trips {
1258				sensor_crit: sensor-crit {
1259					temperature = <125000>;
1260					hysteresis = <1000>;
1261					type = "critical";
1262				};
1263
1264				target: trip-point {
1265					temperature = <100000>;
1266					hysteresis = <1000>;
1267					type = "passive";
1268				};
1269			};
1270		};
1271	};
1272
1273	timer {
1274		compatible = "arm,armv8-timer";
1275		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1276				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1277				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1278				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1279	};
1280};
1281