1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2LC SMARC EVK parts
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11#include "rzg2lc-smarc-pinfunction.dtsi"
12#include "rz-smarc-common.dtsi"
13
14/ {
15	aliases {
16		serial1 = &scif1;
17		i2c2 = &i2c2;
18	};
19
20	osc1: cec-clock {
21		compatible = "fixed-clock";
22		#clock-cells = <0>;
23		clock-frequency = <12000000>;
24	};
25
26	hdmi-out {
27		compatible = "hdmi-connector";
28		type = "d";
29
30		port {
31			hdmi_con_out: endpoint {
32				remote-endpoint = <&adv7535_out>;
33			};
34		};
35	};
36};
37
38#if (SW_SCIF_CAN || SW_RSPI_CAN)
39&canfd {
40	pinctrl-0 = <&can1_pins>;
41	/delete-node/ channel@0;
42};
43#else
44&canfd {
45	/delete-property/ pinctrl-0;
46	/delete-property/ pinctrl-names;
47	status = "disabled";
48};
49#endif
50
51&cpu_dai {
52	sound-dai = <&ssi0>;
53};
54
55&dsi {
56	status = "okay";
57
58	ports {
59		#address-cells = <1>;
60		#size-cells = <0>;
61
62		port@0 {
63			reg = <0>;
64			dsi0_in: endpoint {
65			};
66		};
67
68		port@1 {
69			reg = <1>;
70			dsi0_out: endpoint {
71				data-lanes = <1 2 3 4>;
72				remote-endpoint = <&adv7535_in>;
73			};
74		};
75	};
76};
77
78&i2c1 {
79	adv7535: hdmi@3d {
80		compatible = "adi,adv7535";
81		reg = <0x3d>;
82
83		interrupt-parent = <&pinctrl>;
84		interrupts = <RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>;
85		clocks = <&osc1>;
86		clock-names = "cec";
87		avdd-supply = <&reg_1p8v>;
88		dvdd-supply = <&reg_1p8v>;
89		pvdd-supply = <&reg_1p8v>;
90		a2vdd-supply = <&reg_1p8v>;
91		v3p3-supply = <&reg_3p3v>;
92		v1p2-supply = <&reg_1p8v>;
93
94		adi,dsi-lanes = <4>;
95
96		ports {
97			#address-cells = <1>;
98			#size-cells = <0>;
99
100			port@0 {
101				reg = <0>;
102				adv7535_in: endpoint {
103					remote-endpoint = <&dsi0_out>;
104				};
105			};
106
107			port@1 {
108				reg = <1>;
109				adv7535_out: endpoint {
110					remote-endpoint = <&hdmi_con_out>;
111				};
112			};
113		};
114	};
115};
116
117&i2c2 {
118	pinctrl-0 = <&i2c2_pins>;
119	pinctrl-names = "default";
120	clock-frequency = <400000>;
121
122	status = "okay";
123
124	wm8978: codec@1a {
125		compatible = "wlf,wm8978";
126		#sound-dai-cells = <0>;
127		reg = <0x1a>;
128	};
129
130	versa3: clock-generator@68 {
131		compatible = "renesas,5p35023";
132		reg = <0x68>;
133		#clock-cells = <1>;
134		clocks = <&x1>;
135
136		renesas,settings = [
137			80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
138			00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
139			80 b0 45 c4 95
140		];
141
142		assigned-clocks = <&versa3 0>, <&versa3 1>,
143				  <&versa3 2>, <&versa3 3>,
144				  <&versa3 4>, <&versa3 5>;
145		assigned-clock-rates = <24000000>, <11289600>,
146				       <11289600>, <12000000>,
147				       <25000000>, <12288000>;
148	};
149};
150
151#if PMOD_MTU3
152&mtu3 {
153	pinctrl-0 = <&mtu3_pins>;
154	pinctrl-names = "default";
155
156	status = "okay";
157};
158
159&spi1 {
160	status = "disabled";
161};
162#endif
163
164/*
165 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
166 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
167 * SW2 should be at position 2->3 so that SER0_TX line is activated
168 * SW3 should be at position 2->3 so that SER0_RX line is activated
169 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
170 */
171#if (!SW_SCIF_CAN && PMOD1_SER0)
172&scif1 {
173	pinctrl-0 = <&scif1_pins>;
174	pinctrl-names = "default";
175
176	uart-has-rtscts;
177	status = "okay";
178};
179#endif
180
181&ssi0 {
182	pinctrl-0 = <&ssi0_pins>;
183	pinctrl-names = "default";
184
185	status = "okay";
186};
187
188#if (SW_RSPI_CAN)
189&spi1 {
190	/delete-property/ pinctrl-0;
191	/delete-property/ pinctrl-names;
192	status = "disabled";
193};
194#endif
195
196&vccq_sdhi1 {
197	gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
198};
199