1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 */
5
6#include <dt-bindings/clock/rk3368-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/rk3368-power.h>
12#include <dt-bindings/soc/rockchip,boot-mode.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	compatible = "rockchip,rk3368";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		ethernet0 = &gmac;
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		i2c2 = &i2c2;
26		i2c3 = &i2c3;
27		i2c4 = &i2c4;
28		i2c5 = &i2c5;
29		serial0 = &uart0;
30		serial1 = &uart1;
31		serial2 = &uart2;
32		serial3 = &uart3;
33		serial4 = &uart4;
34		spi0 = &spi0;
35		spi1 = &spi1;
36		spi2 = &spi2;
37	};
38
39	cpus {
40		#address-cells = <0x2>;
41		#size-cells = <0x0>;
42
43		cpu-map {
44			cluster0 {
45				core0 {
46					cpu = <&cpu_b0>;
47				};
48				core1 {
49					cpu = <&cpu_b1>;
50				};
51				core2 {
52					cpu = <&cpu_b2>;
53				};
54				core3 {
55					cpu = <&cpu_b3>;
56				};
57			};
58
59			cluster1 {
60				core0 {
61					cpu = <&cpu_l0>;
62				};
63				core1 {
64					cpu = <&cpu_l1>;
65				};
66				core2 {
67					cpu = <&cpu_l2>;
68				};
69				core3 {
70					cpu = <&cpu_l3>;
71				};
72			};
73		};
74
75		cpu_l0: cpu@0 {
76			device_type = "cpu";
77			compatible = "arm,cortex-a53";
78			reg = <0x0 0x0>;
79			enable-method = "psci";
80			#cooling-cells = <2>; /* min followed by max */
81		};
82
83		cpu_l1: cpu@1 {
84			device_type = "cpu";
85			compatible = "arm,cortex-a53";
86			reg = <0x0 0x1>;
87			enable-method = "psci";
88			#cooling-cells = <2>; /* min followed by max */
89		};
90
91		cpu_l2: cpu@2 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a53";
94			reg = <0x0 0x2>;
95			enable-method = "psci";
96			#cooling-cells = <2>; /* min followed by max */
97		};
98
99		cpu_l3: cpu@3 {
100			device_type = "cpu";
101			compatible = "arm,cortex-a53";
102			reg = <0x0 0x3>;
103			enable-method = "psci";
104			#cooling-cells = <2>; /* min followed by max */
105		};
106
107		cpu_b0: cpu@100 {
108			device_type = "cpu";
109			compatible = "arm,cortex-a53";
110			reg = <0x0 0x100>;
111			enable-method = "psci";
112			#cooling-cells = <2>; /* min followed by max */
113		};
114
115		cpu_b1: cpu@101 {
116			device_type = "cpu";
117			compatible = "arm,cortex-a53";
118			reg = <0x0 0x101>;
119			enable-method = "psci";
120			#cooling-cells = <2>; /* min followed by max */
121		};
122
123		cpu_b2: cpu@102 {
124			device_type = "cpu";
125			compatible = "arm,cortex-a53";
126			reg = <0x0 0x102>;
127			enable-method = "psci";
128			#cooling-cells = <2>; /* min followed by max */
129		};
130
131		cpu_b3: cpu@103 {
132			device_type = "cpu";
133			compatible = "arm,cortex-a53";
134			reg = <0x0 0x103>;
135			enable-method = "psci";
136			#cooling-cells = <2>; /* min followed by max */
137		};
138	};
139
140	arm-pmu {
141		compatible = "arm,armv8-pmuv3";
142		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
143			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
144			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
145			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
146			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
147			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
148			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
149			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
150		interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
151				     <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
152				     <&cpu_b2>, <&cpu_b3>;
153	};
154
155	psci {
156		compatible = "arm,psci-0.2";
157		method = "smc";
158	};
159
160	timer {
161		compatible = "arm,armv8-timer";
162		interrupts = <GIC_PPI 13
163			(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
164			     <GIC_PPI 14
165			(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
166			     <GIC_PPI 11
167			(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
168			     <GIC_PPI 10
169			(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
170	};
171
172	xin24m: oscillator {
173		compatible = "fixed-clock";
174		clock-frequency = <24000000>;
175		clock-output-names = "xin24m";
176		#clock-cells = <0>;
177	};
178
179	sdmmc: mmc@ff0c0000 {
180		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
181		reg = <0x0 0xff0c0000 0x0 0x4000>;
182		max-frequency = <150000000>;
183		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
184			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
185		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
186		fifo-depth = <0x100>;
187		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
188		resets = <&cru SRST_MMC0>;
189		reset-names = "reset";
190		status = "disabled";
191	};
192
193	sdio0: mmc@ff0d0000 {
194		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
195		reg = <0x0 0xff0d0000 0x0 0x4000>;
196		max-frequency = <150000000>;
197		clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
198			 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
199		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
200		fifo-depth = <0x100>;
201		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
202		resets = <&cru SRST_SDIO0>;
203		reset-names = "reset";
204		status = "disabled";
205	};
206
207	emmc: mmc@ff0f0000 {
208		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
209		reg = <0x0 0xff0f0000 0x0 0x4000>;
210		max-frequency = <150000000>;
211		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
212			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
213		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214		fifo-depth = <0x100>;
215		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
216		resets = <&cru SRST_EMMC>;
217		reset-names = "reset";
218		status = "disabled";
219	};
220
221	saradc: saradc@ff100000 {
222		compatible = "rockchip,saradc";
223		reg = <0x0 0xff100000 0x0 0x100>;
224		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
225		#io-channel-cells = <1>;
226		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
227		clock-names = "saradc", "apb_pclk";
228		resets = <&cru SRST_SARADC>;
229		reset-names = "saradc-apb";
230		status = "disabled";
231	};
232
233	spi0: spi@ff110000 {
234		compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
235		reg = <0x0 0xff110000 0x0 0x1000>;
236		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
237		clock-names = "spiclk", "apb_pclk";
238		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
239		pinctrl-names = "default";
240		pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
241		#address-cells = <1>;
242		#size-cells = <0>;
243		status = "disabled";
244	};
245
246	spi1: spi@ff120000 {
247		compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
248		reg = <0x0 0xff120000 0x0 0x1000>;
249		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
250		clock-names = "spiclk", "apb_pclk";
251		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
252		pinctrl-names = "default";
253		pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
254		#address-cells = <1>;
255		#size-cells = <0>;
256		status = "disabled";
257	};
258
259	spi2: spi@ff130000 {
260		compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
261		reg = <0x0 0xff130000 0x0 0x1000>;
262		clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
263		clock-names = "spiclk", "apb_pclk";
264		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
265		pinctrl-names = "default";
266		pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
267		#address-cells = <1>;
268		#size-cells = <0>;
269		status = "disabled";
270	};
271
272	i2c2: i2c@ff140000 {
273		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
274		reg = <0x0 0xff140000 0x0 0x1000>;
275		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
276		#address-cells = <1>;
277		#size-cells = <0>;
278		clock-names = "i2c";
279		clocks = <&cru PCLK_I2C2>;
280		pinctrl-names = "default";
281		pinctrl-0 = <&i2c2_xfer>;
282		status = "disabled";
283	};
284
285	i2c3: i2c@ff150000 {
286		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
287		reg = <0x0 0xff150000 0x0 0x1000>;
288		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
289		#address-cells = <1>;
290		#size-cells = <0>;
291		clock-names = "i2c";
292		clocks = <&cru PCLK_I2C3>;
293		pinctrl-names = "default";
294		pinctrl-0 = <&i2c3_xfer>;
295		status = "disabled";
296	};
297
298	i2c4: i2c@ff160000 {
299		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
300		reg = <0x0 0xff160000 0x0 0x1000>;
301		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
302		#address-cells = <1>;
303		#size-cells = <0>;
304		clock-names = "i2c";
305		clocks = <&cru PCLK_I2C4>;
306		pinctrl-names = "default";
307		pinctrl-0 = <&i2c4_xfer>;
308		status = "disabled";
309	};
310
311	i2c5: i2c@ff170000 {
312		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
313		reg = <0x0 0xff170000 0x0 0x1000>;
314		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
315		#address-cells = <1>;
316		#size-cells = <0>;
317		clock-names = "i2c";
318		clocks = <&cru PCLK_I2C5>;
319		pinctrl-names = "default";
320		pinctrl-0 = <&i2c5_xfer>;
321		status = "disabled";
322	};
323
324	uart0: serial@ff180000 {
325		compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
326		reg = <0x0 0xff180000 0x0 0x100>;
327		clock-frequency = <24000000>;
328		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
329		clock-names = "baudclk", "apb_pclk";
330		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
331		reg-shift = <2>;
332		reg-io-width = <4>;
333		status = "disabled";
334	};
335
336	uart1: serial@ff190000 {
337		compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
338		reg = <0x0 0xff190000 0x0 0x100>;
339		clock-frequency = <24000000>;
340		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
341		clock-names = "baudclk", "apb_pclk";
342		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
343		reg-shift = <2>;
344		reg-io-width = <4>;
345		status = "disabled";
346	};
347
348	uart3: serial@ff1b0000 {
349		compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
350		reg = <0x0 0xff1b0000 0x0 0x100>;
351		clock-frequency = <24000000>;
352		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
353		clock-names = "baudclk", "apb_pclk";
354		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
355		reg-shift = <2>;
356		reg-io-width = <4>;
357		status = "disabled";
358	};
359
360	uart4: serial@ff1c0000 {
361		compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
362		reg = <0x0 0xff1c0000 0x0 0x100>;
363		clock-frequency = <24000000>;
364		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
365		clock-names = "baudclk", "apb_pclk";
366		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
367		reg-shift = <2>;
368		reg-io-width = <4>;
369		status = "disabled";
370	};
371
372	dmac_peri: dma-controller@ff250000 {
373		compatible = "arm,pl330", "arm,primecell";
374		reg = <0x0 0xff250000 0x0 0x4000>;
375		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
376			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
377		#dma-cells = <1>;
378		arm,pl330-broken-no-flushp;
379		arm,pl330-periph-burst;
380		clocks = <&cru ACLK_DMAC_PERI>;
381		clock-names = "apb_pclk";
382	};
383
384	thermal-zones {
385		cpu_thermal: cpu-thermal {
386			polling-delay-passive = <100>; /* milliseconds */
387			polling-delay = <5000>; /* milliseconds */
388
389			thermal-sensors = <&tsadc 0>;
390
391			trips {
392				cpu_alert0: cpu_alert0 {
393					temperature = <75000>; /* millicelsius */
394					hysteresis = <2000>; /* millicelsius */
395					type = "passive";
396				};
397				cpu_alert1: cpu_alert1 {
398					temperature = <80000>; /* millicelsius */
399					hysteresis = <2000>; /* millicelsius */
400					type = "passive";
401				};
402				cpu_crit: cpu_crit {
403					temperature = <95000>; /* millicelsius */
404					hysteresis = <2000>; /* millicelsius */
405					type = "critical";
406				};
407			};
408
409			cooling-maps {
410				map0 {
411					trip = <&cpu_alert0>;
412					cooling-device =
413					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
414					<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
415					<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
416					<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
417				};
418				map1 {
419					trip = <&cpu_alert1>;
420					cooling-device =
421					<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
422					<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
423					<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
424					<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
425				};
426			};
427		};
428
429		gpu_thermal: gpu-thermal {
430			polling-delay-passive = <100>; /* milliseconds */
431			polling-delay = <5000>; /* milliseconds */
432
433			thermal-sensors = <&tsadc 1>;
434
435			trips {
436				gpu_alert0: gpu_alert0 {
437					temperature = <80000>; /* millicelsius */
438					hysteresis = <2000>; /* millicelsius */
439					type = "passive";
440				};
441				gpu_crit: gpu_crit {
442					temperature = <115000>; /* millicelsius */
443					hysteresis = <2000>; /* millicelsius */
444					type = "critical";
445				};
446			};
447
448			cooling-maps {
449				map0 {
450					trip = <&gpu_alert0>;
451					cooling-device =
452					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
453					<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
454					<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
455					<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
456				};
457			};
458		};
459	};
460
461	tsadc: tsadc@ff280000 {
462		compatible = "rockchip,rk3368-tsadc";
463		reg = <0x0 0xff280000 0x0 0x100>;
464		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
465		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
466		clock-names = "tsadc", "apb_pclk";
467		resets = <&cru SRST_TSADC>;
468		reset-names = "tsadc-apb";
469		pinctrl-names = "init", "default", "sleep";
470		pinctrl-0 = <&otp_pin>;
471		pinctrl-1 = <&otp_out>;
472		pinctrl-2 = <&otp_pin>;
473		#thermal-sensor-cells = <1>;
474		rockchip,hw-tshut-temp = <95000>;
475		status = "disabled";
476	};
477
478	gmac: ethernet@ff290000 {
479		compatible = "rockchip,rk3368-gmac";
480		reg = <0x0 0xff290000 0x0 0x10000>;
481		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
482		interrupt-names = "macirq";
483		rockchip,grf = <&grf>;
484		clocks = <&cru SCLK_MAC>,
485			<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
486			<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
487			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
488		clock-names = "stmmaceth",
489			"mac_clk_rx", "mac_clk_tx",
490			"clk_mac_ref", "clk_mac_refout",
491			"aclk_mac", "pclk_mac";
492		status = "disabled";
493	};
494
495	usb_host0_ehci: usb@ff500000 {
496		compatible = "generic-ehci";
497		reg = <0x0 0xff500000 0x0 0x100>;
498		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
499		clocks = <&cru HCLK_HOST0>;
500		status = "disabled";
501	};
502
503	usb_otg: usb@ff580000 {
504		compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
505				"snps,dwc2";
506		reg = <0x0 0xff580000 0x0 0x40000>;
507		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
508		clocks = <&cru HCLK_OTG0>;
509		clock-names = "otg";
510		dr_mode = "otg";
511		g-np-tx-fifo-size = <16>;
512		g-rx-fifo-size = <275>;
513		g-tx-fifo-size = <256 128 128 64 64 32>;
514		status = "disabled";
515	};
516
517	dmac_bus: dma-controller@ff600000 {
518		compatible = "arm,pl330", "arm,primecell";
519		reg = <0x0 0xff600000 0x0 0x4000>;
520		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
521			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
522		#dma-cells = <1>;
523		arm,pl330-broken-no-flushp;
524		arm,pl330-periph-burst;
525		clocks = <&cru ACLK_DMAC_BUS>;
526		clock-names = "apb_pclk";
527	};
528
529	i2c0: i2c@ff650000 {
530		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
531		reg = <0x0 0xff650000 0x0 0x1000>;
532		clocks = <&cru PCLK_I2C0>;
533		clock-names = "i2c";
534		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
535		pinctrl-names = "default";
536		pinctrl-0 = <&i2c0_xfer>;
537		#address-cells = <1>;
538		#size-cells = <0>;
539		status = "disabled";
540	};
541
542	i2c1: i2c@ff660000 {
543		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
544		reg = <0x0 0xff660000 0x0 0x1000>;
545		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
546		#address-cells = <1>;
547		#size-cells = <0>;
548		clock-names = "i2c";
549		clocks = <&cru PCLK_I2C1>;
550		pinctrl-names = "default";
551		pinctrl-0 = <&i2c1_xfer>;
552		status = "disabled";
553	};
554
555	pwm0: pwm@ff680000 {
556		compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
557		reg = <0x0 0xff680000 0x0 0x10>;
558		#pwm-cells = <3>;
559		pinctrl-names = "default";
560		pinctrl-0 = <&pwm0_pin>;
561		clocks = <&cru PCLK_PWM1>;
562		status = "disabled";
563	};
564
565	pwm1: pwm@ff680010 {
566		compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
567		reg = <0x0 0xff680010 0x0 0x10>;
568		#pwm-cells = <3>;
569		pinctrl-names = "default";
570		pinctrl-0 = <&pwm1_pin>;
571		clocks = <&cru PCLK_PWM1>;
572		status = "disabled";
573	};
574
575	pwm2: pwm@ff680020 {
576		compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
577		reg = <0x0 0xff680020 0x0 0x10>;
578		#pwm-cells = <3>;
579		clocks = <&cru PCLK_PWM1>;
580		status = "disabled";
581	};
582
583	pwm3: pwm@ff680030 {
584		compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
585		reg = <0x0 0xff680030 0x0 0x10>;
586		#pwm-cells = <3>;
587		pinctrl-names = "default";
588		pinctrl-0 = <&pwm3_pin>;
589		clocks = <&cru PCLK_PWM1>;
590		status = "disabled";
591	};
592
593	uart2: serial@ff690000 {
594		compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
595		reg = <0x0 0xff690000 0x0 0x100>;
596		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
597		clock-names = "baudclk", "apb_pclk";
598		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
599		pinctrl-names = "default";
600		pinctrl-0 = <&uart2_xfer>;
601		reg-shift = <2>;
602		reg-io-width = <4>;
603		status = "disabled";
604	};
605
606	mbox: mbox@ff6b0000 {
607		compatible = "rockchip,rk3368-mailbox";
608		reg = <0x0 0xff6b0000 0x0 0x1000>;
609		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
610			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
611			     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
612			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
613		clocks = <&cru PCLK_MAILBOX>;
614		clock-names = "pclk_mailbox";
615		#mbox-cells = <1>;
616		status = "disabled";
617	};
618
619	pmu: power-management@ff730000 {
620		compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
621		reg = <0x0 0xff730000 0x0 0x1000>;
622
623		power: power-controller {
624			compatible = "rockchip,rk3368-power-controller";
625			#power-domain-cells = <1>;
626			#address-cells = <1>;
627			#size-cells = <0>;
628
629			/*
630			 * Note: Although SCLK_* are the working clocks
631			 * of device without including on the NOC, needed for
632			 * synchronous reset.
633			 *
634			 * The clocks on the which NOC:
635			 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
636			 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
637			 * ACLK_RGA is on ACLK_RGA_NIU.
638			 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
639			 *
640			 * Which clock are device clocks:
641			 *	clocks		devices
642			 *	*_IEP		IEP:Image Enhancement Processor
643			 *	*_ISP		ISP:Image Signal Processing
644			 *	*_VIP		VIP:Video Input Processor
645			 *	*_VOP*		VOP:Visual Output Processor
646			 *	*_RGA		RGA
647			 *	*_EDP*		EDP
648			 *	*_DPHY*		LVDS
649			 *	*_HDMI		HDMI
650			 *	*_MIPI_*	MIPI
651			 */
652			power-domain@RK3368_PD_VIO {
653				reg = <RK3368_PD_VIO>;
654				clocks = <&cru ACLK_IEP>,
655					 <&cru ACLK_ISP>,
656					 <&cru ACLK_VIP>,
657					 <&cru ACLK_RGA>,
658					 <&cru ACLK_VOP>,
659					 <&cru ACLK_VOP_IEP>,
660					 <&cru DCLK_VOP>,
661					 <&cru HCLK_IEP>,
662					 <&cru HCLK_ISP>,
663					 <&cru HCLK_RGA>,
664					 <&cru HCLK_VIP>,
665					 <&cru HCLK_VOP>,
666					 <&cru HCLK_VIO_HDCPMMU>,
667					 <&cru PCLK_EDP_CTRL>,
668					 <&cru PCLK_HDMI_CTRL>,
669					 <&cru PCLK_HDCP>,
670					 <&cru PCLK_ISP>,
671					 <&cru PCLK_VIP>,
672					 <&cru PCLK_DPHYRX>,
673					 <&cru PCLK_DPHYTX0>,
674					 <&cru PCLK_MIPI_CSI>,
675					 <&cru PCLK_MIPI_DSI0>,
676					 <&cru SCLK_VOP0_PWM>,
677					 <&cru SCLK_EDP_24M>,
678					 <&cru SCLK_EDP>,
679					 <&cru SCLK_HDCP>,
680					 <&cru SCLK_ISP>,
681					 <&cru SCLK_RGA>,
682					 <&cru SCLK_HDMI_CEC>,
683					 <&cru SCLK_HDMI_HDCP>;
684				pm_qos = <&qos_iep>,
685					 <&qos_isp_r0>,
686					 <&qos_isp_r1>,
687					 <&qos_isp_w0>,
688					 <&qos_isp_w1>,
689					 <&qos_vip>,
690					 <&qos_vop>,
691					 <&qos_rga_r>,
692					 <&qos_rga_w>;
693				#power-domain-cells = <0>;
694			};
695
696			/*
697			 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
698			 * (video endecoder & decoder) clocks that on the
699			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
700			 */
701			power-domain@RK3368_PD_VIDEO {
702				reg = <RK3368_PD_VIDEO>;
703				clocks = <&cru ACLK_VIDEO>,
704					 <&cru HCLK_VIDEO>,
705					 <&cru SCLK_HEVC_CABAC>,
706					 <&cru SCLK_HEVC_CORE>;
707				pm_qos = <&qos_hevc_r>,
708					 <&qos_vpu_r>,
709					 <&qos_vpu_w>;
710				#power-domain-cells = <0>;
711			};
712
713			/*
714			 * Note: ACLK_GPU is the GPU clock,
715			 * and on the ACLK_GPU_NIU (NOC).
716			 */
717			power-domain@RK3368_PD_GPU_1 {
718				reg = <RK3368_PD_GPU_1>;
719				clocks = <&cru ACLK_GPU_CFG>,
720					 <&cru ACLK_GPU_MEM>,
721					 <&cru SCLK_GPU_CORE>;
722				pm_qos = <&qos_gpu>;
723				#power-domain-cells = <0>;
724			};
725		};
726	};
727
728	pmugrf: syscon@ff738000 {
729		compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
730		reg = <0x0 0xff738000 0x0 0x1000>;
731
732		pmu_io_domains: io-domains {
733			compatible = "rockchip,rk3368-pmu-io-voltage-domain";
734			status = "disabled";
735		};
736
737		reboot-mode {
738			compatible = "syscon-reboot-mode";
739			offset = <0x200>;
740			mode-normal = <BOOT_NORMAL>;
741			mode-recovery = <BOOT_RECOVERY>;
742			mode-bootloader = <BOOT_FASTBOOT>;
743			mode-loader = <BOOT_BL_DOWNLOAD>;
744		};
745	};
746
747	cru: clock-controller@ff760000 {
748		compatible = "rockchip,rk3368-cru";
749		reg = <0x0 0xff760000 0x0 0x1000>;
750		clocks = <&xin24m>;
751		clock-names = "xin24m";
752		rockchip,grf = <&grf>;
753		#clock-cells = <1>;
754		#reset-cells = <1>;
755	};
756
757	grf: syscon@ff770000 {
758		compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
759		reg = <0x0 0xff770000 0x0 0x1000>;
760
761		io_domains: io-domains {
762			compatible = "rockchip,rk3368-io-voltage-domain";
763			status = "disabled";
764		};
765	};
766
767	wdt: watchdog@ff800000 {
768		compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
769		reg = <0x0 0xff800000 0x0 0x100>;
770		clocks = <&cru PCLK_WDT>;
771		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
772		status = "disabled";
773	};
774
775	timer0: timer@ff810000 {
776		compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
777		reg = <0x0 0xff810000 0x0 0x20>;
778		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
779		clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
780		clock-names = "pclk", "timer";
781	};
782
783	spdif: spdif@ff880000 {
784		compatible = "rockchip,rk3368-spdif";
785		reg = <0x0 0xff880000 0x0 0x1000>;
786		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
787		clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
788		clock-names = "mclk", "hclk";
789		dmas = <&dmac_bus 3>;
790		dma-names = "tx";
791		pinctrl-names = "default";
792		pinctrl-0 = <&spdif_tx>;
793		status = "disabled";
794	};
795
796	i2s_2ch: i2s-2ch@ff890000 {
797		compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
798		reg = <0x0 0xff890000 0x0 0x1000>;
799		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
800		clock-names = "i2s_clk", "i2s_hclk";
801		clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
802		dmas = <&dmac_bus 6>, <&dmac_bus 7>;
803		dma-names = "tx", "rx";
804		status = "disabled";
805	};
806
807	i2s_8ch: i2s-8ch@ff898000 {
808		compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
809		reg = <0x0 0xff898000 0x0 0x1000>;
810		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
811		clock-names = "i2s_clk", "i2s_hclk";
812		clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
813		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
814		dma-names = "tx", "rx";
815		pinctrl-names = "default";
816		pinctrl-0 = <&i2s_8ch_bus>;
817		status = "disabled";
818	};
819
820	iep_mmu: iommu@ff900800 {
821		compatible = "rockchip,iommu";
822		reg = <0x0 0xff900800 0x0 0x100>;
823		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
824		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
825		clock-names = "aclk", "iface";
826		power-domains = <&power RK3368_PD_VIO>;
827		#iommu-cells = <0>;
828		status = "disabled";
829	};
830
831	isp_mmu: iommu@ff914000 {
832		compatible = "rockchip,iommu";
833		reg = <0x0 0xff914000 0x0 0x100>,
834		      <0x0 0xff915000 0x0 0x100>;
835		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
836		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
837		clock-names = "aclk", "iface";
838		#iommu-cells = <0>;
839		power-domains = <&power RK3368_PD_VIO>;
840		rockchip,disable-mmu-reset;
841		status = "disabled";
842	};
843
844	vop_mmu: iommu@ff930300 {
845		compatible = "rockchip,iommu";
846		reg = <0x0 0xff930300 0x0 0x100>;
847		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
848		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
849		clock-names = "aclk", "iface";
850		power-domains = <&power RK3368_PD_VIO>;
851		#iommu-cells = <0>;
852		status = "disabled";
853	};
854
855	hevc_mmu: iommu@ff9a0440 {
856		compatible = "rockchip,iommu";
857		reg = <0x0 0xff9a0440 0x0 0x40>,
858		      <0x0 0xff9a0480 0x0 0x40>;
859		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
860		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
861		clock-names = "aclk", "iface";
862		#iommu-cells = <0>;
863		status = "disabled";
864	};
865
866	vpu_mmu: iommu@ff9a0800 {
867		compatible = "rockchip,iommu";
868		reg = <0x0 0xff9a0800 0x0 0x100>;
869		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
870			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
871		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
872		clock-names = "aclk", "iface";
873		#iommu-cells = <0>;
874		status = "disabled";
875	};
876
877	qos_iep: qos@ffad0000 {
878		compatible = "rockchip,rk3368-qos", "syscon";
879		reg = <0x0 0xffad0000 0x0 0x20>;
880	};
881
882	qos_isp_r0: qos@ffad0080 {
883		compatible = "rockchip,rk3368-qos", "syscon";
884		reg = <0x0 0xffad0080 0x0 0x20>;
885	};
886
887	qos_isp_r1: qos@ffad0100 {
888		compatible = "rockchip,rk3368-qos", "syscon";
889		reg = <0x0 0xffad0100 0x0 0x20>;
890	};
891
892	qos_isp_w0: qos@ffad0180 {
893		compatible = "rockchip,rk3368-qos", "syscon";
894		reg = <0x0 0xffad0180 0x0 0x20>;
895	};
896
897	qos_isp_w1: qos@ffad0200 {
898		compatible = "rockchip,rk3368-qos", "syscon";
899		reg = <0x0 0xffad0200 0x0 0x20>;
900	};
901
902	qos_vip: qos@ffad0280 {
903		compatible = "rockchip,rk3368-qos", "syscon";
904		reg = <0x0 0xffad0280 0x0 0x20>;
905	};
906
907	qos_vop: qos@ffad0300 {
908		compatible = "rockchip,rk3368-qos", "syscon";
909		reg = <0x0 0xffad0300 0x0 0x20>;
910	};
911
912	qos_rga_r: qos@ffad0380 {
913		compatible = "rockchip,rk3368-qos", "syscon";
914		reg = <0x0 0xffad0380 0x0 0x20>;
915	};
916
917	qos_rga_w: qos@ffad0400 {
918		compatible = "rockchip,rk3368-qos", "syscon";
919		reg = <0x0 0xffad0400 0x0 0x20>;
920	};
921
922	qos_hevc_r: qos@ffae0000 {
923		compatible = "rockchip,rk3368-qos", "syscon";
924		reg = <0x0 0xffae0000 0x0 0x20>;
925	};
926
927	qos_vpu_r: qos@ffae0100 {
928		compatible = "rockchip,rk3368-qos", "syscon";
929		reg = <0x0 0xffae0100 0x0 0x20>;
930	};
931
932	qos_vpu_w: qos@ffae0180 {
933		compatible = "rockchip,rk3368-qos", "syscon";
934		reg = <0x0 0xffae0180 0x0 0x20>;
935	};
936
937	qos_gpu: qos@ffaf0000 {
938		compatible = "rockchip,rk3368-qos", "syscon";
939		reg = <0x0 0xffaf0000 0x0 0x20>;
940	};
941
942	efuse256: efuse@ffb00000 {
943		compatible = "rockchip,rk3368-efuse";
944		reg = <0x0 0xffb00000 0x0 0x20>;
945		#address-cells = <1>;
946		#size-cells = <1>;
947		clocks = <&cru PCLK_EFUSE256>;
948		clock-names = "pclk_efuse";
949
950		cpu_leakage: cpu-leakage@17 {
951			reg = <0x17 0x1>;
952		};
953		temp_adjust: temp-adjust@1f {
954			reg = <0x1f 0x1>;
955		};
956	};
957
958	gic: interrupt-controller@ffb71000 {
959		compatible = "arm,gic-400";
960		interrupt-controller;
961		#interrupt-cells = <3>;
962		#address-cells = <0>;
963
964		reg = <0x0 0xffb71000 0x0 0x1000>,
965		      <0x0 0xffb72000 0x0 0x2000>,
966		      <0x0 0xffb74000 0x0 0x2000>,
967		      <0x0 0xffb76000 0x0 0x2000>;
968		interrupts = <GIC_PPI 9
969		      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
970	};
971
972	pinctrl: pinctrl {
973		compatible = "rockchip,rk3368-pinctrl";
974		rockchip,grf = <&grf>;
975		rockchip,pmu = <&pmugrf>;
976		#address-cells = <0x2>;
977		#size-cells = <0x2>;
978		ranges;
979
980		gpio0: gpio@ff750000 {
981			compatible = "rockchip,gpio-bank";
982			reg = <0x0 0xff750000 0x0 0x100>;
983			clocks = <&cru PCLK_GPIO0>;
984			interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
985
986			gpio-controller;
987			#gpio-cells = <0x2>;
988
989			interrupt-controller;
990			#interrupt-cells = <0x2>;
991		};
992
993		gpio1: gpio@ff780000 {
994			compatible = "rockchip,gpio-bank";
995			reg = <0x0 0xff780000 0x0 0x100>;
996			clocks = <&cru PCLK_GPIO1>;
997			interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
998
999			gpio-controller;
1000			#gpio-cells = <0x2>;
1001
1002			interrupt-controller;
1003			#interrupt-cells = <0x2>;
1004		};
1005
1006		gpio2: gpio@ff790000 {
1007			compatible = "rockchip,gpio-bank";
1008			reg = <0x0 0xff790000 0x0 0x100>;
1009			clocks = <&cru PCLK_GPIO2>;
1010			interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1011
1012			gpio-controller;
1013			#gpio-cells = <0x2>;
1014
1015			interrupt-controller;
1016			#interrupt-cells = <0x2>;
1017		};
1018
1019		gpio3: gpio@ff7a0000 {
1020			compatible = "rockchip,gpio-bank";
1021			reg = <0x0 0xff7a0000 0x0 0x100>;
1022			clocks = <&cru PCLK_GPIO3>;
1023			interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1024
1025			gpio-controller;
1026			#gpio-cells = <0x2>;
1027
1028			interrupt-controller;
1029			#interrupt-cells = <0x2>;
1030		};
1031
1032		pcfg_pull_up: pcfg-pull-up {
1033			bias-pull-up;
1034		};
1035
1036		pcfg_pull_down: pcfg-pull-down {
1037			bias-pull-down;
1038		};
1039
1040		pcfg_pull_none: pcfg-pull-none {
1041			bias-disable;
1042		};
1043
1044		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1045			bias-disable;
1046			drive-strength = <12>;
1047		};
1048
1049		emmc {
1050			emmc_clk: emmc-clk {
1051				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1052			};
1053
1054			emmc_cmd: emmc-cmd {
1055				rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1056			};
1057
1058			emmc_pwr: emmc-pwr {
1059				rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1060			};
1061
1062			emmc_bus1: emmc-bus1 {
1063				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1064			};
1065
1066			emmc_bus4: emmc-bus4 {
1067				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1068						<1 RK_PC3 2 &pcfg_pull_up>,
1069						<1 RK_PC4 2 &pcfg_pull_up>,
1070						<1 RK_PC5 2 &pcfg_pull_up>;
1071			};
1072
1073			emmc_bus8: emmc-bus8 {
1074				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1075						<1 RK_PC3 2 &pcfg_pull_up>,
1076						<1 RK_PC4 2 &pcfg_pull_up>,
1077						<1 RK_PC5 2 &pcfg_pull_up>,
1078						<1 RK_PC6 2 &pcfg_pull_up>,
1079						<1 RK_PC7 2 &pcfg_pull_up>,
1080						<1 RK_PD0 2 &pcfg_pull_up>,
1081						<1 RK_PD1 2 &pcfg_pull_up>;
1082			};
1083		};
1084
1085		gmac {
1086			rgmii_pins: rgmii-pins {
1087				rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1088						<3 RK_PD0 1 &pcfg_pull_none>,
1089						<3 RK_PC3 1 &pcfg_pull_none>,
1090						<3 RK_PB0 1 &pcfg_pull_none_12ma>,
1091						<3 RK_PB1 1 &pcfg_pull_none_12ma>,
1092						<3 RK_PB2 1 &pcfg_pull_none_12ma>,
1093						<3 RK_PB6 1 &pcfg_pull_none_12ma>,
1094						<3 RK_PD4 1 &pcfg_pull_none_12ma>,
1095						<3 RK_PB5 1 &pcfg_pull_none_12ma>,
1096						<3 RK_PB7 1 &pcfg_pull_none>,
1097						<3 RK_PC0 1 &pcfg_pull_none>,
1098						<3 RK_PC1 1 &pcfg_pull_none>,
1099						<3 RK_PC2 1 &pcfg_pull_none>,
1100						<3 RK_PD1 1 &pcfg_pull_none>,
1101						<3 RK_PC4 1 &pcfg_pull_none>;
1102			};
1103
1104			rmii_pins: rmii-pins {
1105				rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1106						<3 RK_PD0 1 &pcfg_pull_none>,
1107						<3 RK_PC3 1 &pcfg_pull_none>,
1108						<3 RK_PB0 1 &pcfg_pull_none_12ma>,
1109						<3 RK_PB1 1 &pcfg_pull_none_12ma>,
1110						<3 RK_PB5 1 &pcfg_pull_none_12ma>,
1111						<3 RK_PB7 1 &pcfg_pull_none>,
1112						<3 RK_PC0 1 &pcfg_pull_none>,
1113						<3 RK_PC4 1 &pcfg_pull_none>,
1114						<3 RK_PC5 1 &pcfg_pull_none>;
1115			};
1116		};
1117
1118		i2c0 {
1119			i2c0_xfer: i2c0-xfer {
1120				rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1121						<0 RK_PA7 1 &pcfg_pull_none>;
1122			};
1123		};
1124
1125		i2c1 {
1126			i2c1_xfer: i2c1-xfer {
1127				rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1128						<2 RK_PC6 1 &pcfg_pull_none>;
1129			};
1130		};
1131
1132		i2c2 {
1133			i2c2_xfer: i2c2-xfer {
1134				rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1135						<3 RK_PD7 2 &pcfg_pull_none>;
1136			};
1137		};
1138
1139		i2c3 {
1140			i2c3_xfer: i2c3-xfer {
1141				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1142						<1 RK_PC1 1 &pcfg_pull_none>;
1143			};
1144		};
1145
1146		i2c4 {
1147			i2c4_xfer: i2c4-xfer {
1148				rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1149						<3 RK_PD1 2 &pcfg_pull_none>;
1150			};
1151		};
1152
1153		i2c5 {
1154			i2c5_xfer: i2c5-xfer {
1155				rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1156						<3 RK_PD3 2 &pcfg_pull_none>;
1157			};
1158		};
1159
1160		i2s {
1161			i2s_8ch_bus: i2s-8ch-bus {
1162				rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1163						<2 RK_PB5 1 &pcfg_pull_none>,
1164						<2 RK_PB6 1 &pcfg_pull_none>,
1165						<2 RK_PB7 1 &pcfg_pull_none>,
1166						<2 RK_PC0 1 &pcfg_pull_none>,
1167						<2 RK_PC1 1 &pcfg_pull_none>,
1168						<2 RK_PC2 1 &pcfg_pull_none>,
1169						<2 RK_PC3 1 &pcfg_pull_none>,
1170						<2 RK_PC4 1 &pcfg_pull_none>;
1171			};
1172		};
1173
1174		pwm0 {
1175			pwm0_pin: pwm0-pin {
1176				rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1177			};
1178		};
1179
1180		pwm1 {
1181			pwm1_pin: pwm1-pin {
1182				rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1183			};
1184		};
1185
1186		pwm3 {
1187			pwm3_pin: pwm3-pin {
1188				rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1189			};
1190		};
1191
1192		sdio0 {
1193			sdio0_bus1: sdio0-bus1 {
1194				rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1195			};
1196
1197			sdio0_bus4: sdio0-bus4 {
1198				rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1199						<2 RK_PD5 1 &pcfg_pull_up>,
1200						<2 RK_PD6 1 &pcfg_pull_up>,
1201						<2 RK_PD7 1 &pcfg_pull_up>;
1202			};
1203
1204			sdio0_cmd: sdio0-cmd {
1205				rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1206			};
1207
1208			sdio0_clk: sdio0-clk {
1209				rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1210			};
1211
1212			sdio0_cd: sdio0-cd {
1213				rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1214			};
1215
1216			sdio0_wp: sdio0-wp {
1217				rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1218			};
1219
1220			sdio0_pwr: sdio0-pwr {
1221				rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1222			};
1223
1224			sdio0_bkpwr: sdio0-bkpwr {
1225				rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1226			};
1227
1228			sdio0_int: sdio0-int {
1229				rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1230			};
1231		};
1232
1233		sdmmc {
1234			sdmmc_clk: sdmmc-clk {
1235				rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1236			};
1237
1238			sdmmc_cmd: sdmmc-cmd {
1239				rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1240			};
1241
1242			sdmmc_cd: sdmmc-cd {
1243				rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1244			};
1245
1246			sdmmc_bus1: sdmmc-bus1 {
1247				rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1248			};
1249
1250			sdmmc_bus4: sdmmc-bus4 {
1251				rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1252						<2 RK_PA6 1 &pcfg_pull_up>,
1253						<2 RK_PA7 1 &pcfg_pull_up>,
1254						<2 RK_PB0 1 &pcfg_pull_up>;
1255			};
1256		};
1257
1258		spdif {
1259			spdif_tx: spdif-tx {
1260				rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1261			};
1262		};
1263
1264		spi0 {
1265			spi0_clk: spi0-clk {
1266				rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1267			};
1268			spi0_cs0: spi0-cs0 {
1269				rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1270			};
1271			spi0_cs1: spi0-cs1 {
1272				rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1273			};
1274			spi0_tx: spi0-tx {
1275				rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1276			};
1277			spi0_rx: spi0-rx {
1278				rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1279			};
1280		};
1281
1282		spi1 {
1283			spi1_clk: spi1-clk {
1284				rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1285			};
1286			spi1_cs0: spi1-cs0 {
1287				rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1288			};
1289			spi1_cs1: spi1-cs1 {
1290				rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1291			};
1292			spi1_rx: spi1-rx {
1293				rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1294			};
1295			spi1_tx: spi1-tx {
1296				rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1297			};
1298		};
1299
1300		spi2 {
1301			spi2_clk: spi2-clk {
1302				rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1303			};
1304			spi2_cs0: spi2-cs0 {
1305				rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1306			};
1307			spi2_rx: spi2-rx {
1308				rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1309			};
1310			spi2_tx: spi2-tx {
1311				rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1312			};
1313		};
1314
1315		tsadc {
1316			otp_pin: otp-pin {
1317				rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1318			};
1319
1320			otp_out: otp-out {
1321				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1322			};
1323		};
1324
1325		uart0 {
1326			uart0_xfer: uart0-xfer {
1327				rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1328						<2 RK_PD1 1 &pcfg_pull_none>;
1329			};
1330
1331			uart0_cts: uart0-cts {
1332				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1333			};
1334
1335			uart0_rts: uart0-rts {
1336				rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1337			};
1338		};
1339
1340		uart1 {
1341			uart1_xfer: uart1-xfer {
1342				rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1343						<0 RK_PC5 3 &pcfg_pull_none>;
1344			};
1345
1346			uart1_cts: uart1-cts {
1347				rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1348			};
1349
1350			uart1_rts: uart1-rts {
1351				rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1352			};
1353		};
1354
1355		uart2 {
1356			uart2_xfer: uart2-xfer {
1357				rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1358						<2 RK_PA5 2 &pcfg_pull_none>;
1359			};
1360			/* no rts / cts for uart2 */
1361		};
1362
1363		uart3 {
1364			uart3_xfer: uart3-xfer {
1365				rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1366						<3 RK_PD6 3 &pcfg_pull_none>;
1367			};
1368
1369			uart3_cts: uart3-cts {
1370				rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1371			};
1372
1373			uart3_rts: uart3-rts {
1374				rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1375			};
1376		};
1377
1378		uart4 {
1379			uart4_xfer: uart4-xfer {
1380				rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1381						<0 RK_PD2 3 &pcfg_pull_none>;
1382			};
1383
1384			uart4_cts: uart4-cts {
1385				rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1386			};
1387
1388			uart4_rts: uart4-rts {
1389				rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1390			};
1391		};
1392	};
1393};
1394