1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 128 thermal-idle { 129 #cooling-cells = <2>; 130 duration-us = <10000>; 131 exit-latency-us = <500>; 132 }; 133 }; 134 135 cpu_b1: cpu@101 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a72"; 138 reg = <0x0 0x101>; 139 enable-method = "psci"; 140 capacity-dmips-mhz = <1024>; 141 clocks = <&cru ARMCLKB>; 142 #cooling-cells = <2>; /* min followed by max */ 143 dynamic-power-coefficient = <436>; 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 145 146 thermal-idle { 147 #cooling-cells = <2>; 148 duration-us = <10000>; 149 exit-latency-us = <500>; 150 }; 151 }; 152 153 idle-states { 154 entry-method = "psci"; 155 156 CPU_SLEEP: cpu-sleep { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x0010000>; 160 entry-latency-us = <120>; 161 exit-latency-us = <250>; 162 min-residency-us = <900>; 163 }; 164 165 CLUSTER_SLEEP: cluster-sleep { 166 compatible = "arm,idle-state"; 167 local-timer-stop; 168 arm,psci-suspend-param = <0x1010000>; 169 entry-latency-us = <400>; 170 exit-latency-us = <500>; 171 min-residency-us = <2000>; 172 }; 173 }; 174 }; 175 176 display-subsystem { 177 compatible = "rockchip,display-subsystem"; 178 ports = <&vopl_out>, <&vopb_out>; 179 }; 180 181 dmc: memory-controller { 182 compatible = "rockchip,rk3399-dmc"; 183 rockchip,pmu = <&pmugrf>; 184 devfreq-events = <&dfi>; 185 clocks = <&cru SCLK_DDRC>; 186 clock-names = "dmc_clk"; 187 status = "disabled"; 188 }; 189 190 pmu_a53 { 191 compatible = "arm,cortex-a53-pmu"; 192 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 193 }; 194 195 pmu_a72 { 196 compatible = "arm,cortex-a72-pmu"; 197 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 198 }; 199 200 psci { 201 compatible = "arm,psci-1.0"; 202 method = "smc"; 203 }; 204 205 timer { 206 compatible = "arm,armv8-timer"; 207 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 208 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 209 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 210 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 211 arm,no-tick-in-suspend; 212 }; 213 214 xin24m: xin24m { 215 compatible = "fixed-clock"; 216 clock-frequency = <24000000>; 217 clock-output-names = "xin24m"; 218 #clock-cells = <0>; 219 }; 220 221 pcie0: pcie@f8000000 { 222 compatible = "rockchip,rk3399-pcie"; 223 reg = <0x0 0xf8000000 0x0 0x2000000>, 224 <0x0 0xfd000000 0x0 0x1000000>; 225 reg-names = "axi-base", "apb-base"; 226 device_type = "pci"; 227 #address-cells = <3>; 228 #size-cells = <2>; 229 #interrupt-cells = <1>; 230 aspm-no-l0s; 231 bus-range = <0x0 0x1f>; 232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 234 clock-names = "aclk", "aclk-perf", 235 "hclk", "pm"; 236 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 237 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 238 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 239 interrupt-names = "sys", "legacy", "client"; 240 interrupt-map-mask = <0 0 0 7>; 241 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 242 <0 0 0 2 &pcie0_intc 1>, 243 <0 0 0 3 &pcie0_intc 2>, 244 <0 0 0 4 &pcie0_intc 3>; 245 max-link-speed = <1>; 246 msi-map = <0x0 &its 0x0 0x1000>; 247 phys = <&pcie_phy 0>, <&pcie_phy 1>, 248 <&pcie_phy 2>, <&pcie_phy 3>; 249 phy-names = "pcie-phy-0", "pcie-phy-1", 250 "pcie-phy-2", "pcie-phy-3"; 251 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, 252 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 253 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 254 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 255 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 256 <&cru SRST_A_PCIE>; 257 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 258 "pm", "pclk", "aclk"; 259 status = "disabled"; 260 261 pcie0_intc: interrupt-controller { 262 interrupt-controller; 263 #address-cells = <0>; 264 #interrupt-cells = <1>; 265 }; 266 }; 267 268 gmac: ethernet@fe300000 { 269 compatible = "rockchip,rk3399-gmac"; 270 reg = <0x0 0xfe300000 0x0 0x10000>; 271 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 272 interrupt-names = "macirq"; 273 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 274 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 275 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 276 <&cru PCLK_GMAC>; 277 clock-names = "stmmaceth", "mac_clk_rx", 278 "mac_clk_tx", "clk_mac_ref", 279 "clk_mac_refout", "aclk_mac", 280 "pclk_mac"; 281 power-domains = <&power RK3399_PD_GMAC>; 282 resets = <&cru SRST_A_GMAC>; 283 reset-names = "stmmaceth"; 284 rockchip,grf = <&grf>; 285 snps,txpbl = <0x4>; 286 status = "disabled"; 287 }; 288 289 sdio0: mmc@fe310000 { 290 compatible = "rockchip,rk3399-dw-mshc", 291 "rockchip,rk3288-dw-mshc"; 292 reg = <0x0 0xfe310000 0x0 0x4000>; 293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 294 max-frequency = <150000000>; 295 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 296 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 297 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 298 fifo-depth = <0x100>; 299 power-domains = <&power RK3399_PD_SDIOAUDIO>; 300 resets = <&cru SRST_SDIO0>; 301 reset-names = "reset"; 302 status = "disabled"; 303 }; 304 305 sdmmc: mmc@fe320000 { 306 compatible = "rockchip,rk3399-dw-mshc", 307 "rockchip,rk3288-dw-mshc"; 308 reg = <0x0 0xfe320000 0x0 0x4000>; 309 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 310 max-frequency = <150000000>; 311 assigned-clocks = <&cru HCLK_SD>; 312 assigned-clock-rates = <200000000>; 313 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 314 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 315 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 316 fifo-depth = <0x100>; 317 power-domains = <&power RK3399_PD_SD>; 318 resets = <&cru SRST_SDMMC>; 319 reset-names = "reset"; 320 status = "disabled"; 321 }; 322 323 sdhci: mmc@fe330000 { 324 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 325 reg = <0x0 0xfe330000 0x0 0x10000>; 326 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 327 arasan,soc-ctl-syscon = <&grf>; 328 assigned-clocks = <&cru SCLK_EMMC>; 329 assigned-clock-rates = <200000000>; 330 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 331 clock-names = "clk_xin", "clk_ahb"; 332 clock-output-names = "emmc_cardclock"; 333 #clock-cells = <0>; 334 phys = <&emmc_phy>; 335 phy-names = "phy_arasan"; 336 power-domains = <&power RK3399_PD_EMMC>; 337 disable-cqe-dcmd; 338 status = "disabled"; 339 }; 340 341 usb_host0_ehci: usb@fe380000 { 342 compatible = "generic-ehci"; 343 reg = <0x0 0xfe380000 0x0 0x20000>; 344 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 345 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 346 <&u2phy0>; 347 phys = <&u2phy0_host>; 348 phy-names = "usb"; 349 status = "disabled"; 350 }; 351 352 usb_host0_ohci: usb@fe3a0000 { 353 compatible = "generic-ohci"; 354 reg = <0x0 0xfe3a0000 0x0 0x20000>; 355 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 357 <&u2phy0>; 358 phys = <&u2phy0_host>; 359 phy-names = "usb"; 360 status = "disabled"; 361 }; 362 363 usb_host1_ehci: usb@fe3c0000 { 364 compatible = "generic-ehci"; 365 reg = <0x0 0xfe3c0000 0x0 0x20000>; 366 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 367 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 368 <&u2phy1>; 369 phys = <&u2phy1_host>; 370 phy-names = "usb"; 371 status = "disabled"; 372 }; 373 374 usb_host1_ohci: usb@fe3e0000 { 375 compatible = "generic-ohci"; 376 reg = <0x0 0xfe3e0000 0x0 0x20000>; 377 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 378 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 379 <&u2phy1>; 380 phys = <&u2phy1_host>; 381 phy-names = "usb"; 382 status = "disabled"; 383 }; 384 385 debug@fe430000 { 386 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 387 reg = <0 0xfe430000 0 0x1000>; 388 clocks = <&cru PCLK_COREDBG_L>; 389 clock-names = "apb_pclk"; 390 cpu = <&cpu_l0>; 391 }; 392 393 debug@fe432000 { 394 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 395 reg = <0 0xfe432000 0 0x1000>; 396 clocks = <&cru PCLK_COREDBG_L>; 397 clock-names = "apb_pclk"; 398 cpu = <&cpu_l1>; 399 }; 400 401 debug@fe434000 { 402 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 403 reg = <0 0xfe434000 0 0x1000>; 404 clocks = <&cru PCLK_COREDBG_L>; 405 clock-names = "apb_pclk"; 406 cpu = <&cpu_l2>; 407 }; 408 409 debug@fe436000 { 410 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 411 reg = <0 0xfe436000 0 0x1000>; 412 clocks = <&cru PCLK_COREDBG_L>; 413 clock-names = "apb_pclk"; 414 cpu = <&cpu_l3>; 415 }; 416 417 debug@fe610000 { 418 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 419 reg = <0 0xfe610000 0 0x1000>; 420 clocks = <&cru PCLK_COREDBG_B>; 421 clock-names = "apb_pclk"; 422 cpu = <&cpu_b0>; 423 }; 424 425 debug@fe710000 { 426 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 427 reg = <0 0xfe710000 0 0x1000>; 428 clocks = <&cru PCLK_COREDBG_B>; 429 clock-names = "apb_pclk"; 430 cpu = <&cpu_b1>; 431 }; 432 433 usbdrd3_0: usb@fe800000 { 434 compatible = "rockchip,rk3399-dwc3"; 435 #address-cells = <2>; 436 #size-cells = <2>; 437 ranges; 438 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 439 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 440 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 441 clock-names = "ref_clk", "suspend_clk", 442 "bus_clk", "aclk_usb3_rksoc_axi_perf", 443 "aclk_usb3", "grf_clk"; 444 resets = <&cru SRST_A_USB3_OTG0>; 445 reset-names = "usb3-otg"; 446 status = "disabled"; 447 448 usbdrd_dwc3_0: usb@fe800000 { 449 compatible = "snps,dwc3"; 450 reg = <0x0 0xfe800000 0x0 0x100000>; 451 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 452 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 453 <&cru SCLK_USB3OTG0_SUSPEND>; 454 clock-names = "ref", "bus_early", "suspend"; 455 dr_mode = "otg"; 456 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 457 phy-names = "usb2-phy", "usb3-phy"; 458 phy_type = "utmi_wide"; 459 snps,dis_enblslpm_quirk; 460 snps,dis-u2-freeclk-exists-quirk; 461 snps,dis_u2_susphy_quirk; 462 snps,dis-del-phy-power-chg-quirk; 463 snps,dis-tx-ipgap-linecheck-quirk; 464 power-domains = <&power RK3399_PD_USB3>; 465 status = "disabled"; 466 }; 467 }; 468 469 usbdrd3_1: usb@fe900000 { 470 compatible = "rockchip,rk3399-dwc3"; 471 #address-cells = <2>; 472 #size-cells = <2>; 473 ranges; 474 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 475 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 476 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 477 clock-names = "ref_clk", "suspend_clk", 478 "bus_clk", "aclk_usb3_rksoc_axi_perf", 479 "aclk_usb3", "grf_clk"; 480 resets = <&cru SRST_A_USB3_OTG1>; 481 reset-names = "usb3-otg"; 482 status = "disabled"; 483 484 usbdrd_dwc3_1: usb@fe900000 { 485 compatible = "snps,dwc3"; 486 reg = <0x0 0xfe900000 0x0 0x100000>; 487 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 488 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 489 <&cru SCLK_USB3OTG1_SUSPEND>; 490 clock-names = "ref", "bus_early", "suspend"; 491 dr_mode = "otg"; 492 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 493 phy-names = "usb2-phy", "usb3-phy"; 494 phy_type = "utmi_wide"; 495 snps,dis_enblslpm_quirk; 496 snps,dis-u2-freeclk-exists-quirk; 497 snps,dis_u2_susphy_quirk; 498 snps,dis-del-phy-power-chg-quirk; 499 snps,dis-tx-ipgap-linecheck-quirk; 500 power-domains = <&power RK3399_PD_USB3>; 501 status = "disabled"; 502 }; 503 }; 504 505 cdn_dp: dp@fec00000 { 506 compatible = "rockchip,rk3399-cdn-dp"; 507 reg = <0x0 0xfec00000 0x0 0x100000>; 508 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 509 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 510 assigned-clock-rates = <100000000>, <200000000>; 511 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 512 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 513 clock-names = "core-clk", "pclk", "spdif", "grf"; 514 phys = <&tcphy0_dp>, <&tcphy1_dp>; 515 power-domains = <&power RK3399_PD_HDCP>; 516 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 517 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 518 reset-names = "spdif", "dptx", "apb", "core"; 519 rockchip,grf = <&grf>; 520 #sound-dai-cells = <1>; 521 status = "disabled"; 522 523 ports { 524 dp_in: port { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 528 dp_in_vopb: endpoint@0 { 529 reg = <0>; 530 remote-endpoint = <&vopb_out_dp>; 531 }; 532 533 dp_in_vopl: endpoint@1 { 534 reg = <1>; 535 remote-endpoint = <&vopl_out_dp>; 536 }; 537 }; 538 }; 539 }; 540 541 gic: interrupt-controller@fee00000 { 542 compatible = "arm,gic-v3"; 543 #interrupt-cells = <4>; 544 #address-cells = <2>; 545 #size-cells = <2>; 546 ranges; 547 interrupt-controller; 548 549 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 550 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 551 <0x0 0xfff00000 0 0x10000>, /* GICC */ 552 <0x0 0xfff10000 0 0x10000>, /* GICH */ 553 <0x0 0xfff20000 0 0x10000>; /* GICV */ 554 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 555 its: msi-controller@fee20000 { 556 compatible = "arm,gic-v3-its"; 557 msi-controller; 558 #msi-cells = <1>; 559 reg = <0x0 0xfee20000 0x0 0x20000>; 560 }; 561 562 ppi-partitions { 563 ppi_cluster0: interrupt-partition-0 { 564 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 565 }; 566 567 ppi_cluster1: interrupt-partition-1 { 568 affinity = <&cpu_b0 &cpu_b1>; 569 }; 570 }; 571 }; 572 573 saradc: saradc@ff100000 { 574 compatible = "rockchip,rk3399-saradc"; 575 reg = <0x0 0xff100000 0x0 0x100>; 576 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 577 #io-channel-cells = <1>; 578 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 579 clock-names = "saradc", "apb_pclk"; 580 resets = <&cru SRST_P_SARADC>; 581 reset-names = "saradc-apb"; 582 status = "disabled"; 583 }; 584 585 crypto0: crypto@ff8b0000 { 586 compatible = "rockchip,rk3399-crypto"; 587 reg = <0x0 0xff8b0000 0x0 0x4000>; 588 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; 589 clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>; 590 clock-names = "hclk_master", "hclk_slave", "sclk"; 591 resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>; 592 reset-names = "master", "slave", "crypto-rst"; 593 }; 594 595 crypto1: crypto@ff8b8000 { 596 compatible = "rockchip,rk3399-crypto"; 597 reg = <0x0 0xff8b8000 0x0 0x4000>; 598 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 599 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>; 600 clock-names = "hclk_master", "hclk_slave", "sclk"; 601 resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>; 602 reset-names = "master", "slave", "crypto-rst"; 603 }; 604 605 i2c1: i2c@ff110000 { 606 compatible = "rockchip,rk3399-i2c"; 607 reg = <0x0 0xff110000 0x0 0x1000>; 608 assigned-clocks = <&cru SCLK_I2C1>; 609 assigned-clock-rates = <200000000>; 610 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 611 clock-names = "i2c", "pclk"; 612 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&i2c1_xfer>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 }; 619 620 i2c2: i2c@ff120000 { 621 compatible = "rockchip,rk3399-i2c"; 622 reg = <0x0 0xff120000 0x0 0x1000>; 623 assigned-clocks = <&cru SCLK_I2C2>; 624 assigned-clock-rates = <200000000>; 625 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 626 clock-names = "i2c", "pclk"; 627 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&i2c2_xfer>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 status = "disabled"; 633 }; 634 635 i2c3: i2c@ff130000 { 636 compatible = "rockchip,rk3399-i2c"; 637 reg = <0x0 0xff130000 0x0 0x1000>; 638 assigned-clocks = <&cru SCLK_I2C3>; 639 assigned-clock-rates = <200000000>; 640 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 641 clock-names = "i2c", "pclk"; 642 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&i2c3_xfer>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 status = "disabled"; 648 }; 649 650 i2c5: i2c@ff140000 { 651 compatible = "rockchip,rk3399-i2c"; 652 reg = <0x0 0xff140000 0x0 0x1000>; 653 assigned-clocks = <&cru SCLK_I2C5>; 654 assigned-clock-rates = <200000000>; 655 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 656 clock-names = "i2c", "pclk"; 657 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&i2c5_xfer>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 status = "disabled"; 663 }; 664 665 i2c6: i2c@ff150000 { 666 compatible = "rockchip,rk3399-i2c"; 667 reg = <0x0 0xff150000 0x0 0x1000>; 668 assigned-clocks = <&cru SCLK_I2C6>; 669 assigned-clock-rates = <200000000>; 670 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 671 clock-names = "i2c", "pclk"; 672 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&i2c6_xfer>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 status = "disabled"; 678 }; 679 680 i2c7: i2c@ff160000 { 681 compatible = "rockchip,rk3399-i2c"; 682 reg = <0x0 0xff160000 0x0 0x1000>; 683 assigned-clocks = <&cru SCLK_I2C7>; 684 assigned-clock-rates = <200000000>; 685 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 686 clock-names = "i2c", "pclk"; 687 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&i2c7_xfer>; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 status = "disabled"; 693 }; 694 695 uart0: serial@ff180000 { 696 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 697 reg = <0x0 0xff180000 0x0 0x100>; 698 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 699 clock-names = "baudclk", "apb_pclk"; 700 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 701 reg-shift = <2>; 702 reg-io-width = <4>; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&uart0_xfer>; 705 status = "disabled"; 706 }; 707 708 uart1: serial@ff190000 { 709 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 710 reg = <0x0 0xff190000 0x0 0x100>; 711 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 712 clock-names = "baudclk", "apb_pclk"; 713 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 714 reg-shift = <2>; 715 reg-io-width = <4>; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&uart1_xfer>; 718 status = "disabled"; 719 }; 720 721 uart2: serial@ff1a0000 { 722 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 723 reg = <0x0 0xff1a0000 0x0 0x100>; 724 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 725 clock-names = "baudclk", "apb_pclk"; 726 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 727 reg-shift = <2>; 728 reg-io-width = <4>; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&uart2c_xfer>; 731 status = "disabled"; 732 }; 733 734 uart3: serial@ff1b0000 { 735 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 736 reg = <0x0 0xff1b0000 0x0 0x100>; 737 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 738 clock-names = "baudclk", "apb_pclk"; 739 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 740 reg-shift = <2>; 741 reg-io-width = <4>; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&uart3_xfer>; 744 status = "disabled"; 745 }; 746 747 spi0: spi@ff1c0000 { 748 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 749 reg = <0x0 0xff1c0000 0x0 0x1000>; 750 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 751 clock-names = "spiclk", "apb_pclk"; 752 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 753 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 754 dma-names = "tx", "rx"; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 status = "disabled"; 760 }; 761 762 spi1: spi@ff1d0000 { 763 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 764 reg = <0x0 0xff1d0000 0x0 0x1000>; 765 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 766 clock-names = "spiclk", "apb_pclk"; 767 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 768 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 769 dma-names = "tx", "rx"; 770 pinctrl-names = "default"; 771 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 spi2: spi@ff1e0000 { 778 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 779 reg = <0x0 0xff1e0000 0x0 0x1000>; 780 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 781 clock-names = "spiclk", "apb_pclk"; 782 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 783 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 784 dma-names = "tx", "rx"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 spi4: spi@ff1f0000 { 793 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 794 reg = <0x0 0xff1f0000 0x0 0x1000>; 795 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 796 clock-names = "spiclk", "apb_pclk"; 797 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 798 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 799 dma-names = "tx", "rx"; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 status = "disabled"; 805 }; 806 807 spi5: spi@ff200000 { 808 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 809 reg = <0x0 0xff200000 0x0 0x1000>; 810 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 811 clock-names = "spiclk", "apb_pclk"; 812 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 813 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 814 dma-names = "tx", "rx"; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 817 power-domains = <&power RK3399_PD_SDIOAUDIO>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 status = "disabled"; 821 }; 822 823 thermal_zones: thermal-zones { 824 cpu_thermal: cpu-thermal { 825 polling-delay-passive = <100>; 826 polling-delay = <1000>; 827 828 thermal-sensors = <&tsadc 0>; 829 830 trips { 831 cpu_alert0: cpu_alert0 { 832 temperature = <70000>; 833 hysteresis = <2000>; 834 type = "passive"; 835 }; 836 cpu_alert1: cpu_alert1 { 837 temperature = <75000>; 838 hysteresis = <2000>; 839 type = "passive"; 840 }; 841 cpu_crit: cpu_crit { 842 temperature = <95000>; 843 hysteresis = <2000>; 844 type = "critical"; 845 }; 846 }; 847 848 cooling-maps { 849 map0 { 850 trip = <&cpu_alert0>; 851 cooling-device = 852 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 853 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 854 }; 855 map1 { 856 trip = <&cpu_alert1>; 857 cooling-device = 858 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 859 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 860 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 861 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 862 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 863 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 864 }; 865 }; 866 }; 867 868 gpu_thermal: gpu-thermal { 869 polling-delay-passive = <100>; 870 polling-delay = <1000>; 871 872 thermal-sensors = <&tsadc 1>; 873 874 trips { 875 gpu_alert0: gpu_alert0 { 876 temperature = <75000>; 877 hysteresis = <2000>; 878 type = "passive"; 879 }; 880 gpu_crit: gpu_crit { 881 temperature = <95000>; 882 hysteresis = <2000>; 883 type = "critical"; 884 }; 885 }; 886 887 cooling-maps { 888 map0 { 889 trip = <&gpu_alert0>; 890 cooling-device = 891 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 892 }; 893 }; 894 }; 895 }; 896 897 tsadc: tsadc@ff260000 { 898 compatible = "rockchip,rk3399-tsadc"; 899 reg = <0x0 0xff260000 0x0 0x100>; 900 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 901 assigned-clocks = <&cru SCLK_TSADC>; 902 assigned-clock-rates = <750000>; 903 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 904 clock-names = "tsadc", "apb_pclk"; 905 resets = <&cru SRST_TSADC>; 906 reset-names = "tsadc-apb"; 907 rockchip,grf = <&grf>; 908 rockchip,hw-tshut-temp = <95000>; 909 pinctrl-names = "init", "default", "sleep"; 910 pinctrl-0 = <&otp_pin>; 911 pinctrl-1 = <&otp_out>; 912 pinctrl-2 = <&otp_pin>; 913 #thermal-sensor-cells = <1>; 914 status = "disabled"; 915 }; 916 917 qos_emmc: qos@ffa58000 { 918 compatible = "rockchip,rk3399-qos", "syscon"; 919 reg = <0x0 0xffa58000 0x0 0x20>; 920 }; 921 922 qos_gmac: qos@ffa5c000 { 923 compatible = "rockchip,rk3399-qos", "syscon"; 924 reg = <0x0 0xffa5c000 0x0 0x20>; 925 }; 926 927 qos_pcie: qos@ffa60080 { 928 compatible = "rockchip,rk3399-qos", "syscon"; 929 reg = <0x0 0xffa60080 0x0 0x20>; 930 }; 931 932 qos_usb_host0: qos@ffa60100 { 933 compatible = "rockchip,rk3399-qos", "syscon"; 934 reg = <0x0 0xffa60100 0x0 0x20>; 935 }; 936 937 qos_usb_host1: qos@ffa60180 { 938 compatible = "rockchip,rk3399-qos", "syscon"; 939 reg = <0x0 0xffa60180 0x0 0x20>; 940 }; 941 942 qos_usb_otg0: qos@ffa70000 { 943 compatible = "rockchip,rk3399-qos", "syscon"; 944 reg = <0x0 0xffa70000 0x0 0x20>; 945 }; 946 947 qos_usb_otg1: qos@ffa70080 { 948 compatible = "rockchip,rk3399-qos", "syscon"; 949 reg = <0x0 0xffa70080 0x0 0x20>; 950 }; 951 952 qos_sd: qos@ffa74000 { 953 compatible = "rockchip,rk3399-qos", "syscon"; 954 reg = <0x0 0xffa74000 0x0 0x20>; 955 }; 956 957 qos_sdioaudio: qos@ffa76000 { 958 compatible = "rockchip,rk3399-qos", "syscon"; 959 reg = <0x0 0xffa76000 0x0 0x20>; 960 }; 961 962 qos_hdcp: qos@ffa90000 { 963 compatible = "rockchip,rk3399-qos", "syscon"; 964 reg = <0x0 0xffa90000 0x0 0x20>; 965 }; 966 967 qos_iep: qos@ffa98000 { 968 compatible = "rockchip,rk3399-qos", "syscon"; 969 reg = <0x0 0xffa98000 0x0 0x20>; 970 }; 971 972 qos_isp0_m0: qos@ffaa0000 { 973 compatible = "rockchip,rk3399-qos", "syscon"; 974 reg = <0x0 0xffaa0000 0x0 0x20>; 975 }; 976 977 qos_isp0_m1: qos@ffaa0080 { 978 compatible = "rockchip,rk3399-qos", "syscon"; 979 reg = <0x0 0xffaa0080 0x0 0x20>; 980 }; 981 982 qos_isp1_m0: qos@ffaa8000 { 983 compatible = "rockchip,rk3399-qos", "syscon"; 984 reg = <0x0 0xffaa8000 0x0 0x20>; 985 }; 986 987 qos_isp1_m1: qos@ffaa8080 { 988 compatible = "rockchip,rk3399-qos", "syscon"; 989 reg = <0x0 0xffaa8080 0x0 0x20>; 990 }; 991 992 qos_rga_r: qos@ffab0000 { 993 compatible = "rockchip,rk3399-qos", "syscon"; 994 reg = <0x0 0xffab0000 0x0 0x20>; 995 }; 996 997 qos_rga_w: qos@ffab0080 { 998 compatible = "rockchip,rk3399-qos", "syscon"; 999 reg = <0x0 0xffab0080 0x0 0x20>; 1000 }; 1001 1002 qos_video_m0: qos@ffab8000 { 1003 compatible = "rockchip,rk3399-qos", "syscon"; 1004 reg = <0x0 0xffab8000 0x0 0x20>; 1005 }; 1006 1007 qos_video_m1_r: qos@ffac0000 { 1008 compatible = "rockchip,rk3399-qos", "syscon"; 1009 reg = <0x0 0xffac0000 0x0 0x20>; 1010 }; 1011 1012 qos_video_m1_w: qos@ffac0080 { 1013 compatible = "rockchip,rk3399-qos", "syscon"; 1014 reg = <0x0 0xffac0080 0x0 0x20>; 1015 }; 1016 1017 qos_vop_big_r: qos@ffac8000 { 1018 compatible = "rockchip,rk3399-qos", "syscon"; 1019 reg = <0x0 0xffac8000 0x0 0x20>; 1020 }; 1021 1022 qos_vop_big_w: qos@ffac8080 { 1023 compatible = "rockchip,rk3399-qos", "syscon"; 1024 reg = <0x0 0xffac8080 0x0 0x20>; 1025 }; 1026 1027 qos_vop_little: qos@ffad0000 { 1028 compatible = "rockchip,rk3399-qos", "syscon"; 1029 reg = <0x0 0xffad0000 0x0 0x20>; 1030 }; 1031 1032 qos_perihp: qos@ffad8080 { 1033 compatible = "rockchip,rk3399-qos", "syscon"; 1034 reg = <0x0 0xffad8080 0x0 0x20>; 1035 }; 1036 1037 qos_gpu: qos@ffae0000 { 1038 compatible = "rockchip,rk3399-qos", "syscon"; 1039 reg = <0x0 0xffae0000 0x0 0x20>; 1040 }; 1041 1042 pmu: power-management@ff310000 { 1043 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 1044 reg = <0x0 0xff310000 0x0 0x1000>; 1045 1046 /* 1047 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 1048 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 1049 * Some of the power domains are grouped together for every 1050 * voltage domain. 1051 * The detail contents as below. 1052 */ 1053 power: power-controller { 1054 compatible = "rockchip,rk3399-power-controller"; 1055 #power-domain-cells = <1>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 1059 /* These power domains are grouped by VD_CENTER */ 1060 power-domain@RK3399_PD_IEP { 1061 reg = <RK3399_PD_IEP>; 1062 clocks = <&cru ACLK_IEP>, 1063 <&cru HCLK_IEP>; 1064 pm_qos = <&qos_iep>; 1065 #power-domain-cells = <0>; 1066 }; 1067 power-domain@RK3399_PD_RGA { 1068 reg = <RK3399_PD_RGA>; 1069 clocks = <&cru ACLK_RGA>, 1070 <&cru HCLK_RGA>; 1071 pm_qos = <&qos_rga_r>, 1072 <&qos_rga_w>; 1073 #power-domain-cells = <0>; 1074 }; 1075 power-domain@RK3399_PD_VCODEC { 1076 reg = <RK3399_PD_VCODEC>; 1077 clocks = <&cru ACLK_VCODEC>, 1078 <&cru HCLK_VCODEC>; 1079 pm_qos = <&qos_video_m0>; 1080 #power-domain-cells = <0>; 1081 }; 1082 power-domain@RK3399_PD_VDU { 1083 reg = <RK3399_PD_VDU>; 1084 clocks = <&cru ACLK_VDU>, 1085 <&cru HCLK_VDU>; 1086 pm_qos = <&qos_video_m1_r>, 1087 <&qos_video_m1_w>; 1088 #power-domain-cells = <0>; 1089 }; 1090 1091 /* These power domains are grouped by VD_GPU */ 1092 power-domain@RK3399_PD_GPU { 1093 reg = <RK3399_PD_GPU>; 1094 clocks = <&cru ACLK_GPU>; 1095 pm_qos = <&qos_gpu>; 1096 #power-domain-cells = <0>; 1097 }; 1098 1099 /* These power domains are grouped by VD_LOGIC */ 1100 power-domain@RK3399_PD_EDP { 1101 reg = <RK3399_PD_EDP>; 1102 clocks = <&cru PCLK_EDP_CTRL>; 1103 #power-domain-cells = <0>; 1104 }; 1105 power-domain@RK3399_PD_EMMC { 1106 reg = <RK3399_PD_EMMC>; 1107 clocks = <&cru ACLK_EMMC>; 1108 pm_qos = <&qos_emmc>; 1109 #power-domain-cells = <0>; 1110 }; 1111 power-domain@RK3399_PD_GMAC { 1112 reg = <RK3399_PD_GMAC>; 1113 clocks = <&cru ACLK_GMAC>, 1114 <&cru PCLK_GMAC>; 1115 pm_qos = <&qos_gmac>; 1116 #power-domain-cells = <0>; 1117 }; 1118 power-domain@RK3399_PD_SD { 1119 reg = <RK3399_PD_SD>; 1120 clocks = <&cru HCLK_SDMMC>, 1121 <&cru SCLK_SDMMC>; 1122 pm_qos = <&qos_sd>; 1123 #power-domain-cells = <0>; 1124 }; 1125 power-domain@RK3399_PD_SDIOAUDIO { 1126 reg = <RK3399_PD_SDIOAUDIO>; 1127 clocks = <&cru HCLK_SDIO>; 1128 pm_qos = <&qos_sdioaudio>; 1129 #power-domain-cells = <0>; 1130 }; 1131 power-domain@RK3399_PD_TCPD0 { 1132 reg = <RK3399_PD_TCPD0>; 1133 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1134 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1135 #power-domain-cells = <0>; 1136 }; 1137 power-domain@RK3399_PD_TCPD1 { 1138 reg = <RK3399_PD_TCPD1>; 1139 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1140 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1141 #power-domain-cells = <0>; 1142 }; 1143 power-domain@RK3399_PD_USB3 { 1144 reg = <RK3399_PD_USB3>; 1145 clocks = <&cru ACLK_USB3>; 1146 pm_qos = <&qos_usb_otg0>, 1147 <&qos_usb_otg1>; 1148 #power-domain-cells = <0>; 1149 }; 1150 power-domain@RK3399_PD_VIO { 1151 reg = <RK3399_PD_VIO>; 1152 #power-domain-cells = <1>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 1156 power-domain@RK3399_PD_HDCP { 1157 reg = <RK3399_PD_HDCP>; 1158 clocks = <&cru ACLK_HDCP>, 1159 <&cru HCLK_HDCP>, 1160 <&cru PCLK_HDCP>; 1161 pm_qos = <&qos_hdcp>; 1162 #power-domain-cells = <0>; 1163 }; 1164 power-domain@RK3399_PD_ISP0 { 1165 reg = <RK3399_PD_ISP0>; 1166 clocks = <&cru ACLK_ISP0>, 1167 <&cru HCLK_ISP0>; 1168 pm_qos = <&qos_isp0_m0>, 1169 <&qos_isp0_m1>; 1170 #power-domain-cells = <0>; 1171 }; 1172 power-domain@RK3399_PD_ISP1 { 1173 reg = <RK3399_PD_ISP1>; 1174 clocks = <&cru ACLK_ISP1>, 1175 <&cru HCLK_ISP1>; 1176 pm_qos = <&qos_isp1_m0>, 1177 <&qos_isp1_m1>; 1178 #power-domain-cells = <0>; 1179 }; 1180 power-domain@RK3399_PD_VO { 1181 reg = <RK3399_PD_VO>; 1182 #power-domain-cells = <1>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 1186 power-domain@RK3399_PD_VOPB { 1187 reg = <RK3399_PD_VOPB>; 1188 clocks = <&cru ACLK_VOP0>, 1189 <&cru HCLK_VOP0>; 1190 pm_qos = <&qos_vop_big_r>, 1191 <&qos_vop_big_w>; 1192 #power-domain-cells = <0>; 1193 }; 1194 power-domain@RK3399_PD_VOPL { 1195 reg = <RK3399_PD_VOPL>; 1196 clocks = <&cru ACLK_VOP1>, 1197 <&cru HCLK_VOP1>; 1198 pm_qos = <&qos_vop_little>; 1199 #power-domain-cells = <0>; 1200 }; 1201 }; 1202 }; 1203 }; 1204 }; 1205 1206 pmugrf: syscon@ff320000 { 1207 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1208 reg = <0x0 0xff320000 0x0 0x1000>; 1209 1210 pmu_io_domains: io-domains { 1211 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1212 status = "disabled"; 1213 }; 1214 }; 1215 1216 spi3: spi@ff350000 { 1217 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1218 reg = <0x0 0xff350000 0x0 0x1000>; 1219 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1220 clock-names = "spiclk", "apb_pclk"; 1221 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 status = "disabled"; 1227 }; 1228 1229 uart4: serial@ff370000 { 1230 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1231 reg = <0x0 0xff370000 0x0 0x100>; 1232 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1233 clock-names = "baudclk", "apb_pclk"; 1234 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1235 reg-shift = <2>; 1236 reg-io-width = <4>; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&uart4_xfer>; 1239 status = "disabled"; 1240 }; 1241 1242 i2c0: i2c@ff3c0000 { 1243 compatible = "rockchip,rk3399-i2c"; 1244 reg = <0x0 0xff3c0000 0x0 0x1000>; 1245 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1246 assigned-clock-rates = <200000000>; 1247 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1248 clock-names = "i2c", "pclk"; 1249 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&i2c0_xfer>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 i2c4: i2c@ff3d0000 { 1258 compatible = "rockchip,rk3399-i2c"; 1259 reg = <0x0 0xff3d0000 0x0 0x1000>; 1260 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1261 assigned-clock-rates = <200000000>; 1262 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1263 clock-names = "i2c", "pclk"; 1264 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&i2c4_xfer>; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 status = "disabled"; 1270 }; 1271 1272 i2c8: i2c@ff3e0000 { 1273 compatible = "rockchip,rk3399-i2c"; 1274 reg = <0x0 0xff3e0000 0x0 0x1000>; 1275 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1276 assigned-clock-rates = <200000000>; 1277 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1278 clock-names = "i2c", "pclk"; 1279 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&i2c8_xfer>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 pwm0: pwm@ff420000 { 1288 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1289 reg = <0x0 0xff420000 0x0 0x10>; 1290 #pwm-cells = <3>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&pwm0_pin>; 1293 clocks = <&pmucru PCLK_RKPWM_PMU>; 1294 status = "disabled"; 1295 }; 1296 1297 pwm1: pwm@ff420010 { 1298 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1299 reg = <0x0 0xff420010 0x0 0x10>; 1300 #pwm-cells = <3>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&pwm1_pin>; 1303 clocks = <&pmucru PCLK_RKPWM_PMU>; 1304 status = "disabled"; 1305 }; 1306 1307 pwm2: pwm@ff420020 { 1308 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1309 reg = <0x0 0xff420020 0x0 0x10>; 1310 #pwm-cells = <3>; 1311 pinctrl-names = "default"; 1312 pinctrl-0 = <&pwm2_pin>; 1313 clocks = <&pmucru PCLK_RKPWM_PMU>; 1314 status = "disabled"; 1315 }; 1316 1317 pwm3: pwm@ff420030 { 1318 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1319 reg = <0x0 0xff420030 0x0 0x10>; 1320 #pwm-cells = <3>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&pwm3a_pin>; 1323 clocks = <&pmucru PCLK_RKPWM_PMU>; 1324 status = "disabled"; 1325 }; 1326 1327 dfi: dfi@ff630000 { 1328 reg = <0x00 0xff630000 0x00 0x4000>; 1329 compatible = "rockchip,rk3399-dfi"; 1330 rockchip,pmu = <&pmugrf>; 1331 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1332 clocks = <&cru PCLK_DDR_MON>; 1333 clock-names = "pclk_ddr_mon"; 1334 status = "disabled"; 1335 }; 1336 1337 vpu: video-codec@ff650000 { 1338 compatible = "rockchip,rk3399-vpu"; 1339 reg = <0x0 0xff650000 0x0 0x800>; 1340 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1341 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1342 interrupt-names = "vepu", "vdpu"; 1343 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1344 clock-names = "aclk", "hclk"; 1345 iommus = <&vpu_mmu>; 1346 power-domains = <&power RK3399_PD_VCODEC>; 1347 }; 1348 1349 vpu_mmu: iommu@ff650800 { 1350 compatible = "rockchip,iommu"; 1351 reg = <0x0 0xff650800 0x0 0x40>; 1352 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1353 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1354 clock-names = "aclk", "iface"; 1355 #iommu-cells = <0>; 1356 power-domains = <&power RK3399_PD_VCODEC>; 1357 }; 1358 1359 vdec: video-codec@ff660000 { 1360 compatible = "rockchip,rk3399-vdec"; 1361 reg = <0x0 0xff660000 0x0 0x400>; 1362 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1363 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1364 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1365 clock-names = "axi", "ahb", "cabac", "core"; 1366 iommus = <&vdec_mmu>; 1367 power-domains = <&power RK3399_PD_VDU>; 1368 }; 1369 1370 vdec_mmu: iommu@ff660480 { 1371 compatible = "rockchip,iommu"; 1372 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1373 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1374 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1375 clock-names = "aclk", "iface"; 1376 power-domains = <&power RK3399_PD_VDU>; 1377 #iommu-cells = <0>; 1378 }; 1379 1380 iep_mmu: iommu@ff670800 { 1381 compatible = "rockchip,iommu"; 1382 reg = <0x0 0xff670800 0x0 0x40>; 1383 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1384 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1385 clock-names = "aclk", "iface"; 1386 #iommu-cells = <0>; 1387 status = "disabled"; 1388 }; 1389 1390 rga: rga@ff680000 { 1391 compatible = "rockchip,rk3399-rga"; 1392 reg = <0x0 0xff680000 0x0 0x10000>; 1393 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1394 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1395 clock-names = "aclk", "hclk", "sclk"; 1396 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1397 reset-names = "core", "axi", "ahb"; 1398 power-domains = <&power RK3399_PD_RGA>; 1399 }; 1400 1401 efuse0: efuse@ff690000 { 1402 compatible = "rockchip,rk3399-efuse"; 1403 reg = <0x0 0xff690000 0x0 0x80>; 1404 #address-cells = <1>; 1405 #size-cells = <1>; 1406 clocks = <&cru PCLK_EFUSE1024NS>; 1407 clock-names = "pclk_efuse"; 1408 1409 /* Data cells */ 1410 cpu_id: cpu-id@7 { 1411 reg = <0x07 0x10>; 1412 }; 1413 cpub_leakage: cpu-leakage@17 { 1414 reg = <0x17 0x1>; 1415 }; 1416 gpu_leakage: gpu-leakage@18 { 1417 reg = <0x18 0x1>; 1418 }; 1419 center_leakage: center-leakage@19 { 1420 reg = <0x19 0x1>; 1421 }; 1422 cpul_leakage: cpu-leakage@1a { 1423 reg = <0x1a 0x1>; 1424 }; 1425 logic_leakage: logic-leakage@1b { 1426 reg = <0x1b 0x1>; 1427 }; 1428 wafer_info: wafer-info@1c { 1429 reg = <0x1c 0x1>; 1430 }; 1431 }; 1432 1433 dmac_bus: dma-controller@ff6d0000 { 1434 compatible = "arm,pl330", "arm,primecell"; 1435 reg = <0x0 0xff6d0000 0x0 0x4000>; 1436 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 1437 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1438 #dma-cells = <1>; 1439 arm,pl330-periph-burst; 1440 clocks = <&cru ACLK_DMAC0_PERILP>; 1441 clock-names = "apb_pclk"; 1442 }; 1443 1444 dmac_peri: dma-controller@ff6e0000 { 1445 compatible = "arm,pl330", "arm,primecell"; 1446 reg = <0x0 0xff6e0000 0x0 0x4000>; 1447 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 1448 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 1449 #dma-cells = <1>; 1450 arm,pl330-periph-burst; 1451 clocks = <&cru ACLK_DMAC1_PERILP>; 1452 clock-names = "apb_pclk"; 1453 }; 1454 1455 pmucru: clock-controller@ff750000 { 1456 compatible = "rockchip,rk3399-pmucru"; 1457 reg = <0x0 0xff750000 0x0 0x1000>; 1458 clocks = <&xin24m>; 1459 clock-names = "xin24m"; 1460 rockchip,grf = <&pmugrf>; 1461 #clock-cells = <1>; 1462 #reset-cells = <1>; 1463 assigned-clocks = <&pmucru PLL_PPLL>; 1464 assigned-clock-rates = <676000000>; 1465 }; 1466 1467 cru: clock-controller@ff760000 { 1468 compatible = "rockchip,rk3399-cru"; 1469 reg = <0x0 0xff760000 0x0 0x1000>; 1470 clocks = <&xin24m>; 1471 clock-names = "xin24m"; 1472 rockchip,grf = <&grf>; 1473 #clock-cells = <1>; 1474 #reset-cells = <1>; 1475 assigned-clocks = 1476 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1477 <&cru PLL_NPLL>, 1478 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1479 <&cru PCLK_PERIHP>, 1480 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1481 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1482 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1483 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1484 <&cru ACLK_GIC_PRE>, 1485 <&cru PCLK_DDR>, 1486 <&cru ACLK_VDU>; 1487 assigned-clock-rates = 1488 <594000000>, <800000000>, 1489 <1000000000>, 1490 <150000000>, <75000000>, 1491 <37500000>, 1492 <100000000>, <100000000>, 1493 <50000000>, <600000000>, 1494 <100000000>, <50000000>, 1495 <400000000>, <400000000>, 1496 <200000000>, 1497 <200000000>, 1498 <400000000>; 1499 }; 1500 1501 grf: syscon@ff770000 { 1502 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1503 reg = <0x0 0xff770000 0x0 0x10000>; 1504 #address-cells = <1>; 1505 #size-cells = <1>; 1506 1507 io_domains: io-domains { 1508 compatible = "rockchip,rk3399-io-voltage-domain"; 1509 status = "disabled"; 1510 }; 1511 1512 mipi_dphy_rx0: mipi-dphy-rx0 { 1513 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1514 clocks = <&cru SCLK_MIPIDPHY_REF>, 1515 <&cru SCLK_DPHY_RX0_CFG>, 1516 <&cru PCLK_VIO_GRF>; 1517 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1518 power-domains = <&power RK3399_PD_VIO>; 1519 #phy-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 1523 u2phy0: usb2phy@e450 { 1524 compatible = "rockchip,rk3399-usb2phy"; 1525 reg = <0xe450 0x10>; 1526 clocks = <&cru SCLK_USB2PHY0_REF>; 1527 clock-names = "phyclk"; 1528 #clock-cells = <0>; 1529 clock-output-names = "clk_usbphy0_480m"; 1530 status = "disabled"; 1531 1532 u2phy0_host: host-port { 1533 #phy-cells = <0>; 1534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1535 interrupt-names = "linestate"; 1536 status = "disabled"; 1537 }; 1538 1539 u2phy0_otg: otg-port { 1540 #phy-cells = <0>; 1541 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1542 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1543 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1544 interrupt-names = "otg-bvalid", "otg-id", 1545 "linestate"; 1546 status = "disabled"; 1547 }; 1548 }; 1549 1550 u2phy1: usb2phy@e460 { 1551 compatible = "rockchip,rk3399-usb2phy"; 1552 reg = <0xe460 0x10>; 1553 clocks = <&cru SCLK_USB2PHY1_REF>; 1554 clock-names = "phyclk"; 1555 #clock-cells = <0>; 1556 clock-output-names = "clk_usbphy1_480m"; 1557 status = "disabled"; 1558 1559 u2phy1_host: host-port { 1560 #phy-cells = <0>; 1561 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1562 interrupt-names = "linestate"; 1563 status = "disabled"; 1564 }; 1565 1566 u2phy1_otg: otg-port { 1567 #phy-cells = <0>; 1568 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1569 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1570 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1571 interrupt-names = "otg-bvalid", "otg-id", 1572 "linestate"; 1573 status = "disabled"; 1574 }; 1575 }; 1576 1577 emmc_phy: phy@f780 { 1578 compatible = "rockchip,rk3399-emmc-phy"; 1579 reg = <0xf780 0x24>; 1580 clocks = <&sdhci>; 1581 clock-names = "emmcclk"; 1582 drive-impedance-ohm = <50>; 1583 #phy-cells = <0>; 1584 status = "disabled"; 1585 }; 1586 1587 pcie_phy: pcie-phy { 1588 compatible = "rockchip,rk3399-pcie-phy"; 1589 clocks = <&cru SCLK_PCIEPHY_REF>; 1590 clock-names = "refclk"; 1591 #phy-cells = <1>; 1592 resets = <&cru SRST_PCIEPHY>; 1593 reset-names = "phy"; 1594 status = "disabled"; 1595 }; 1596 }; 1597 1598 tcphy0: phy@ff7c0000 { 1599 compatible = "rockchip,rk3399-typec-phy"; 1600 reg = <0x0 0xff7c0000 0x0 0x40000>; 1601 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1602 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1603 clock-names = "tcpdcore", "tcpdphy-ref"; 1604 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1605 assigned-clock-rates = <50000000>; 1606 power-domains = <&power RK3399_PD_TCPD0>; 1607 resets = <&cru SRST_UPHY0>, 1608 <&cru SRST_UPHY0_PIPE_L00>, 1609 <&cru SRST_P_UPHY0_TCPHY>; 1610 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1611 rockchip,grf = <&grf>; 1612 status = "disabled"; 1613 1614 tcphy0_dp: dp-port { 1615 #phy-cells = <0>; 1616 }; 1617 1618 tcphy0_usb3: usb3-port { 1619 #phy-cells = <0>; 1620 }; 1621 }; 1622 1623 tcphy1: phy@ff800000 { 1624 compatible = "rockchip,rk3399-typec-phy"; 1625 reg = <0x0 0xff800000 0x0 0x40000>; 1626 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1627 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1628 clock-names = "tcpdcore", "tcpdphy-ref"; 1629 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1630 assigned-clock-rates = <50000000>; 1631 power-domains = <&power RK3399_PD_TCPD1>; 1632 resets = <&cru SRST_UPHY1>, 1633 <&cru SRST_UPHY1_PIPE_L00>, 1634 <&cru SRST_P_UPHY1_TCPHY>; 1635 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1636 rockchip,grf = <&grf>; 1637 status = "disabled"; 1638 1639 tcphy1_dp: dp-port { 1640 #phy-cells = <0>; 1641 }; 1642 1643 tcphy1_usb3: usb3-port { 1644 #phy-cells = <0>; 1645 }; 1646 }; 1647 1648 watchdog@ff848000 { 1649 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; 1650 reg = <0x0 0xff848000 0x0 0x100>; 1651 clocks = <&cru PCLK_WDT>; 1652 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1653 }; 1654 1655 rktimer: rktimer@ff850000 { 1656 compatible = "rockchip,rk3399-timer"; 1657 reg = <0x0 0xff850000 0x0 0x1000>; 1658 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1659 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1660 clock-names = "pclk", "timer"; 1661 }; 1662 1663 spdif: spdif@ff870000 { 1664 compatible = "rockchip,rk3399-spdif"; 1665 reg = <0x0 0xff870000 0x0 0x1000>; 1666 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1667 dmas = <&dmac_bus 7>; 1668 dma-names = "tx"; 1669 clock-names = "mclk", "hclk"; 1670 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&spdif_bus>; 1673 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1674 #sound-dai-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 i2s0: i2s@ff880000 { 1679 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1680 reg = <0x0 0xff880000 0x0 0x1000>; 1681 rockchip,grf = <&grf>; 1682 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1683 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1684 dma-names = "tx", "rx"; 1685 clock-names = "i2s_clk", "i2s_hclk"; 1686 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1687 pinctrl-names = "bclk_on", "bclk_off"; 1688 pinctrl-0 = <&i2s0_8ch_bus>; 1689 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; 1690 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1691 #sound-dai-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 i2s1: i2s@ff890000 { 1696 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1697 reg = <0x0 0xff890000 0x0 0x1000>; 1698 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1699 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1700 dma-names = "tx", "rx"; 1701 clock-names = "i2s_clk", "i2s_hclk"; 1702 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&i2s1_2ch_bus>; 1705 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1706 #sound-dai-cells = <0>; 1707 status = "disabled"; 1708 }; 1709 1710 i2s2: i2s@ff8a0000 { 1711 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1712 reg = <0x0 0xff8a0000 0x0 0x1000>; 1713 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1714 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1715 dma-names = "tx", "rx"; 1716 clock-names = "i2s_clk", "i2s_hclk"; 1717 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1718 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1719 #sound-dai-cells = <0>; 1720 status = "disabled"; 1721 }; 1722 1723 vopl: vop@ff8f0000 { 1724 compatible = "rockchip,rk3399-vop-lit"; 1725 reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; 1726 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1727 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1728 assigned-clock-rates = <400000000>, <100000000>; 1729 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1730 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1731 iommus = <&vopl_mmu>; 1732 power-domains = <&power RK3399_PD_VOPL>; 1733 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1734 reset-names = "axi", "ahb", "dclk"; 1735 status = "disabled"; 1736 1737 vopl_out: port { 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 1741 vopl_out_mipi: endpoint@0 { 1742 reg = <0>; 1743 remote-endpoint = <&mipi_in_vopl>; 1744 }; 1745 1746 vopl_out_edp: endpoint@1 { 1747 reg = <1>; 1748 remote-endpoint = <&edp_in_vopl>; 1749 }; 1750 1751 vopl_out_hdmi: endpoint@2 { 1752 reg = <2>; 1753 remote-endpoint = <&hdmi_in_vopl>; 1754 }; 1755 1756 vopl_out_mipi1: endpoint@3 { 1757 reg = <3>; 1758 remote-endpoint = <&mipi1_in_vopl>; 1759 }; 1760 1761 vopl_out_dp: endpoint@4 { 1762 reg = <4>; 1763 remote-endpoint = <&dp_in_vopl>; 1764 }; 1765 }; 1766 }; 1767 1768 vopl_mmu: iommu@ff8f3f00 { 1769 compatible = "rockchip,iommu"; 1770 reg = <0x0 0xff8f3f00 0x0 0x100>; 1771 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1772 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1773 clock-names = "aclk", "iface"; 1774 power-domains = <&power RK3399_PD_VOPL>; 1775 #iommu-cells = <0>; 1776 status = "disabled"; 1777 }; 1778 1779 vopb: vop@ff900000 { 1780 compatible = "rockchip,rk3399-vop-big"; 1781 reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; 1782 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1783 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1784 assigned-clock-rates = <400000000>, <100000000>; 1785 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1786 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1787 iommus = <&vopb_mmu>; 1788 power-domains = <&power RK3399_PD_VOPB>; 1789 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1790 reset-names = "axi", "ahb", "dclk"; 1791 status = "disabled"; 1792 1793 vopb_out: port { 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 1797 vopb_out_edp: endpoint@0 { 1798 reg = <0>; 1799 remote-endpoint = <&edp_in_vopb>; 1800 }; 1801 1802 vopb_out_mipi: endpoint@1 { 1803 reg = <1>; 1804 remote-endpoint = <&mipi_in_vopb>; 1805 }; 1806 1807 vopb_out_hdmi: endpoint@2 { 1808 reg = <2>; 1809 remote-endpoint = <&hdmi_in_vopb>; 1810 }; 1811 1812 vopb_out_mipi1: endpoint@3 { 1813 reg = <3>; 1814 remote-endpoint = <&mipi1_in_vopb>; 1815 }; 1816 1817 vopb_out_dp: endpoint@4 { 1818 reg = <4>; 1819 remote-endpoint = <&dp_in_vopb>; 1820 }; 1821 }; 1822 }; 1823 1824 vopb_mmu: iommu@ff903f00 { 1825 compatible = "rockchip,iommu"; 1826 reg = <0x0 0xff903f00 0x0 0x100>; 1827 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1828 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1829 clock-names = "aclk", "iface"; 1830 power-domains = <&power RK3399_PD_VOPB>; 1831 #iommu-cells = <0>; 1832 status = "disabled"; 1833 }; 1834 1835 isp0: isp0@ff910000 { 1836 compatible = "rockchip,rk3399-cif-isp"; 1837 reg = <0x0 0xff910000 0x0 0x4000>; 1838 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1839 clocks = <&cru SCLK_ISP0>, 1840 <&cru ACLK_ISP0_WRAPPER>, 1841 <&cru HCLK_ISP0_WRAPPER>; 1842 clock-names = "isp", "aclk", "hclk"; 1843 iommus = <&isp0_mmu>; 1844 phys = <&mipi_dphy_rx0>; 1845 phy-names = "dphy"; 1846 power-domains = <&power RK3399_PD_ISP0>; 1847 status = "disabled"; 1848 1849 ports { 1850 #address-cells = <1>; 1851 #size-cells = <0>; 1852 1853 port@0 { 1854 reg = <0>; 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 }; 1858 }; 1859 }; 1860 1861 isp0_mmu: iommu@ff914000 { 1862 compatible = "rockchip,iommu"; 1863 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1864 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1865 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1866 clock-names = "aclk", "iface"; 1867 #iommu-cells = <0>; 1868 power-domains = <&power RK3399_PD_ISP0>; 1869 rockchip,disable-mmu-reset; 1870 }; 1871 1872 isp1: isp1@ff920000 { 1873 compatible = "rockchip,rk3399-cif-isp"; 1874 reg = <0x0 0xff920000 0x0 0x4000>; 1875 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1876 clocks = <&cru SCLK_ISP1>, 1877 <&cru ACLK_ISP1_WRAPPER>, 1878 <&cru HCLK_ISP1_WRAPPER>; 1879 clock-names = "isp", "aclk", "hclk"; 1880 iommus = <&isp1_mmu>; 1881 phys = <&mipi_dsi1>; 1882 phy-names = "dphy"; 1883 power-domains = <&power RK3399_PD_ISP1>; 1884 status = "disabled"; 1885 1886 ports { 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 1890 port@0 { 1891 reg = <0>; 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 }; 1895 }; 1896 }; 1897 1898 isp1_mmu: iommu@ff924000 { 1899 compatible = "rockchip,iommu"; 1900 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1901 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1902 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1903 clock-names = "aclk", "iface"; 1904 #iommu-cells = <0>; 1905 power-domains = <&power RK3399_PD_ISP1>; 1906 rockchip,disable-mmu-reset; 1907 }; 1908 1909 hdmi_sound: hdmi-sound { 1910 compatible = "simple-audio-card"; 1911 simple-audio-card,format = "i2s"; 1912 simple-audio-card,mclk-fs = <256>; 1913 simple-audio-card,name = "hdmi-sound"; 1914 status = "disabled"; 1915 1916 simple-audio-card,cpu { 1917 sound-dai = <&i2s2>; 1918 }; 1919 simple-audio-card,codec { 1920 sound-dai = <&hdmi>; 1921 }; 1922 }; 1923 1924 hdmi: hdmi@ff940000 { 1925 compatible = "rockchip,rk3399-dw-hdmi"; 1926 reg = <0x0 0xff940000 0x0 0x20000>; 1927 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1928 clocks = <&cru PCLK_HDMI_CTRL>, 1929 <&cru SCLK_HDMI_SFR>, 1930 <&cru SCLK_HDMI_CEC>, 1931 <&cru PCLK_VIO_GRF>, 1932 <&cru PLL_VPLL>; 1933 clock-names = "iahb", "isfr", "cec", "grf", "ref"; 1934 power-domains = <&power RK3399_PD_HDCP>; 1935 reg-io-width = <4>; 1936 rockchip,grf = <&grf>; 1937 #sound-dai-cells = <0>; 1938 status = "disabled"; 1939 1940 ports { 1941 hdmi_in: port { 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 1945 hdmi_in_vopb: endpoint@0 { 1946 reg = <0>; 1947 remote-endpoint = <&vopb_out_hdmi>; 1948 }; 1949 hdmi_in_vopl: endpoint@1 { 1950 reg = <1>; 1951 remote-endpoint = <&vopl_out_hdmi>; 1952 }; 1953 }; 1954 }; 1955 }; 1956 1957 mipi_dsi: dsi@ff960000 { 1958 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1959 reg = <0x0 0xff960000 0x0 0x8000>; 1960 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1961 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1962 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1963 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1964 power-domains = <&power RK3399_PD_VIO>; 1965 resets = <&cru SRST_P_MIPI_DSI0>; 1966 reset-names = "apb"; 1967 rockchip,grf = <&grf>; 1968 #address-cells = <1>; 1969 #size-cells = <0>; 1970 status = "disabled"; 1971 1972 ports { 1973 #address-cells = <1>; 1974 #size-cells = <0>; 1975 1976 mipi_in: port@0 { 1977 reg = <0>; 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 1981 mipi_in_vopb: endpoint@0 { 1982 reg = <0>; 1983 remote-endpoint = <&vopb_out_mipi>; 1984 }; 1985 1986 mipi_in_vopl: endpoint@1 { 1987 reg = <1>; 1988 remote-endpoint = <&vopl_out_mipi>; 1989 }; 1990 }; 1991 1992 mipi_out: port@1 { 1993 reg = <1>; 1994 }; 1995 }; 1996 }; 1997 1998 mipi_dsi1: dsi@ff968000 { 1999 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 2000 reg = <0x0 0xff968000 0x0 0x8000>; 2001 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 2002 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 2003 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 2004 clock-names = "ref", "pclk", "phy_cfg", "grf"; 2005 power-domains = <&power RK3399_PD_VIO>; 2006 resets = <&cru SRST_P_MIPI_DSI1>; 2007 reset-names = "apb"; 2008 rockchip,grf = <&grf>; 2009 #address-cells = <1>; 2010 #size-cells = <0>; 2011 #phy-cells = <0>; 2012 status = "disabled"; 2013 2014 ports { 2015 #address-cells = <1>; 2016 #size-cells = <0>; 2017 2018 mipi1_in: port@0 { 2019 reg = <0>; 2020 #address-cells = <1>; 2021 #size-cells = <0>; 2022 2023 mipi1_in_vopb: endpoint@0 { 2024 reg = <0>; 2025 remote-endpoint = <&vopb_out_mipi1>; 2026 }; 2027 2028 mipi1_in_vopl: endpoint@1 { 2029 reg = <1>; 2030 remote-endpoint = <&vopl_out_mipi1>; 2031 }; 2032 }; 2033 2034 mipi1_out: port@1 { 2035 reg = <1>; 2036 }; 2037 }; 2038 }; 2039 2040 edp: dp@ff970000 { 2041 compatible = "rockchip,rk3399-edp"; 2042 reg = <0x0 0xff970000 0x0 0x8000>; 2043 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 2044 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 2045 clock-names = "dp", "pclk", "grf"; 2046 pinctrl-names = "default"; 2047 pinctrl-0 = <&edp_hpd>; 2048 power-domains = <&power RK3399_PD_EDP>; 2049 resets = <&cru SRST_P_EDP_CTRL>; 2050 reset-names = "dp"; 2051 rockchip,grf = <&grf>; 2052 status = "disabled"; 2053 2054 ports { 2055 #address-cells = <1>; 2056 #size-cells = <0>; 2057 2058 edp_in: port@0 { 2059 reg = <0>; 2060 #address-cells = <1>; 2061 #size-cells = <0>; 2062 2063 edp_in_vopb: endpoint@0 { 2064 reg = <0>; 2065 remote-endpoint = <&vopb_out_edp>; 2066 }; 2067 2068 edp_in_vopl: endpoint@1 { 2069 reg = <1>; 2070 remote-endpoint = <&vopl_out_edp>; 2071 }; 2072 }; 2073 2074 edp_out: port@1 { 2075 reg = <1>; 2076 }; 2077 }; 2078 }; 2079 2080 gpu: gpu@ff9a0000 { 2081 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 2082 reg = <0x0 0xff9a0000 0x0 0x10000>; 2083 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 2084 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 2085 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2086 interrupt-names = "job", "mmu", "gpu"; 2087 clocks = <&cru ACLK_GPU>; 2088 #cooling-cells = <2>; 2089 power-domains = <&power RK3399_PD_GPU>; 2090 status = "disabled"; 2091 }; 2092 2093 pinctrl: pinctrl { 2094 compatible = "rockchip,rk3399-pinctrl"; 2095 rockchip,grf = <&grf>; 2096 rockchip,pmu = <&pmugrf>; 2097 #address-cells = <2>; 2098 #size-cells = <2>; 2099 ranges; 2100 2101 gpio0: gpio@ff720000 { 2102 compatible = "rockchip,gpio-bank"; 2103 reg = <0x0 0xff720000 0x0 0x100>; 2104 clocks = <&pmucru PCLK_GPIO0_PMU>; 2105 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2106 2107 gpio-controller; 2108 #gpio-cells = <0x2>; 2109 2110 interrupt-controller; 2111 #interrupt-cells = <0x2>; 2112 }; 2113 2114 gpio1: gpio@ff730000 { 2115 compatible = "rockchip,gpio-bank"; 2116 reg = <0x0 0xff730000 0x0 0x100>; 2117 clocks = <&pmucru PCLK_GPIO1_PMU>; 2118 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 2119 2120 gpio-controller; 2121 #gpio-cells = <0x2>; 2122 2123 interrupt-controller; 2124 #interrupt-cells = <0x2>; 2125 }; 2126 2127 gpio2: gpio@ff780000 { 2128 compatible = "rockchip,gpio-bank"; 2129 reg = <0x0 0xff780000 0x0 0x100>; 2130 clocks = <&cru PCLK_GPIO2>; 2131 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 2132 2133 gpio-controller; 2134 #gpio-cells = <0x2>; 2135 2136 interrupt-controller; 2137 #interrupt-cells = <0x2>; 2138 }; 2139 2140 gpio3: gpio@ff788000 { 2141 compatible = "rockchip,gpio-bank"; 2142 reg = <0x0 0xff788000 0x0 0x100>; 2143 clocks = <&cru PCLK_GPIO3>; 2144 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 2145 2146 gpio-controller; 2147 #gpio-cells = <0x2>; 2148 2149 interrupt-controller; 2150 #interrupt-cells = <0x2>; 2151 }; 2152 2153 gpio4: gpio@ff790000 { 2154 compatible = "rockchip,gpio-bank"; 2155 reg = <0x0 0xff790000 0x0 0x100>; 2156 clocks = <&cru PCLK_GPIO4>; 2157 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2158 2159 gpio-controller; 2160 #gpio-cells = <0x2>; 2161 2162 interrupt-controller; 2163 #interrupt-cells = <0x2>; 2164 }; 2165 2166 pcfg_pull_up: pcfg-pull-up { 2167 bias-pull-up; 2168 }; 2169 2170 pcfg_pull_down: pcfg-pull-down { 2171 bias-pull-down; 2172 }; 2173 2174 pcfg_pull_none: pcfg-pull-none { 2175 bias-disable; 2176 }; 2177 2178 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2179 bias-disable; 2180 drive-strength = <12>; 2181 }; 2182 2183 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2184 bias-disable; 2185 drive-strength = <13>; 2186 }; 2187 2188 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2189 bias-disable; 2190 drive-strength = <18>; 2191 }; 2192 2193 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2194 bias-disable; 2195 drive-strength = <20>; 2196 }; 2197 2198 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2199 bias-pull-up; 2200 drive-strength = <2>; 2201 }; 2202 2203 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2204 bias-pull-up; 2205 drive-strength = <8>; 2206 }; 2207 2208 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2209 bias-pull-up; 2210 drive-strength = <18>; 2211 }; 2212 2213 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2214 bias-pull-up; 2215 drive-strength = <20>; 2216 }; 2217 2218 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2219 bias-pull-down; 2220 drive-strength = <4>; 2221 }; 2222 2223 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2224 bias-pull-down; 2225 drive-strength = <8>; 2226 }; 2227 2228 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2229 bias-pull-down; 2230 drive-strength = <12>; 2231 }; 2232 2233 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2234 bias-pull-down; 2235 drive-strength = <18>; 2236 }; 2237 2238 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2239 bias-pull-down; 2240 drive-strength = <20>; 2241 }; 2242 2243 pcfg_output_high: pcfg-output-high { 2244 output-high; 2245 }; 2246 2247 pcfg_output_low: pcfg-output-low { 2248 output-low; 2249 }; 2250 2251 pcfg_input_enable: pcfg-input-enable { 2252 input-enable; 2253 }; 2254 2255 pcfg_input_pull_up: pcfg-input-pull-up { 2256 input-enable; 2257 bias-pull-up; 2258 }; 2259 2260 pcfg_input_pull_down: pcfg-input-pull-down { 2261 input-enable; 2262 bias-pull-down; 2263 }; 2264 2265 clock { 2266 clk_32k: clk-32k { 2267 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2268 }; 2269 }; 2270 2271 cif { 2272 cif_clkin: cif-clkin { 2273 rockchip,pins = 2274 <2 RK_PB2 3 &pcfg_pull_none>; 2275 }; 2276 2277 cif_clkouta: cif-clkouta { 2278 rockchip,pins = 2279 <2 RK_PB3 3 &pcfg_pull_none>; 2280 }; 2281 }; 2282 2283 edp { 2284 edp_hpd: edp-hpd { 2285 rockchip,pins = 2286 <4 RK_PC7 2 &pcfg_pull_none>; 2287 }; 2288 }; 2289 2290 gmac { 2291 rgmii_pins: rgmii-pins { 2292 rockchip,pins = 2293 /* mac_txclk */ 2294 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2295 /* mac_rxclk */ 2296 <3 RK_PB6 1 &pcfg_pull_none>, 2297 /* mac_mdio */ 2298 <3 RK_PB5 1 &pcfg_pull_none>, 2299 /* mac_txen */ 2300 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2301 /* mac_clk */ 2302 <3 RK_PB3 1 &pcfg_pull_none>, 2303 /* mac_rxdv */ 2304 <3 RK_PB1 1 &pcfg_pull_none>, 2305 /* mac_mdc */ 2306 <3 RK_PB0 1 &pcfg_pull_none>, 2307 /* mac_rxd1 */ 2308 <3 RK_PA7 1 &pcfg_pull_none>, 2309 /* mac_rxd0 */ 2310 <3 RK_PA6 1 &pcfg_pull_none>, 2311 /* mac_txd1 */ 2312 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2313 /* mac_txd0 */ 2314 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2315 /* mac_rxd3 */ 2316 <3 RK_PA3 1 &pcfg_pull_none>, 2317 /* mac_rxd2 */ 2318 <3 RK_PA2 1 &pcfg_pull_none>, 2319 /* mac_txd3 */ 2320 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2321 /* mac_txd2 */ 2322 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2323 }; 2324 2325 rmii_pins: rmii-pins { 2326 rockchip,pins = 2327 /* mac_mdio */ 2328 <3 RK_PB5 1 &pcfg_pull_none>, 2329 /* mac_txen */ 2330 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2331 /* mac_clk */ 2332 <3 RK_PB3 1 &pcfg_pull_none>, 2333 /* mac_rxer */ 2334 <3 RK_PB2 1 &pcfg_pull_none>, 2335 /* mac_rxdv */ 2336 <3 RK_PB1 1 &pcfg_pull_none>, 2337 /* mac_mdc */ 2338 <3 RK_PB0 1 &pcfg_pull_none>, 2339 /* mac_rxd1 */ 2340 <3 RK_PA7 1 &pcfg_pull_none>, 2341 /* mac_rxd0 */ 2342 <3 RK_PA6 1 &pcfg_pull_none>, 2343 /* mac_txd1 */ 2344 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2345 /* mac_txd0 */ 2346 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2347 }; 2348 }; 2349 2350 i2c0 { 2351 i2c0_xfer: i2c0-xfer { 2352 rockchip,pins = 2353 <1 RK_PB7 2 &pcfg_pull_none>, 2354 <1 RK_PC0 2 &pcfg_pull_none>; 2355 }; 2356 }; 2357 2358 i2c1 { 2359 i2c1_xfer: i2c1-xfer { 2360 rockchip,pins = 2361 <4 RK_PA2 1 &pcfg_pull_none>, 2362 <4 RK_PA1 1 &pcfg_pull_none>; 2363 }; 2364 }; 2365 2366 i2c2 { 2367 i2c2_xfer: i2c2-xfer { 2368 rockchip,pins = 2369 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2370 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2371 }; 2372 }; 2373 2374 i2c3 { 2375 i2c3_xfer: i2c3-xfer { 2376 rockchip,pins = 2377 <4 RK_PC1 1 &pcfg_pull_none>, 2378 <4 RK_PC0 1 &pcfg_pull_none>; 2379 }; 2380 }; 2381 2382 i2c4 { 2383 i2c4_xfer: i2c4-xfer { 2384 rockchip,pins = 2385 <1 RK_PB4 1 &pcfg_pull_none>, 2386 <1 RK_PB3 1 &pcfg_pull_none>; 2387 }; 2388 }; 2389 2390 i2c5 { 2391 i2c5_xfer: i2c5-xfer { 2392 rockchip,pins = 2393 <3 RK_PB3 2 &pcfg_pull_none>, 2394 <3 RK_PB2 2 &pcfg_pull_none>; 2395 }; 2396 }; 2397 2398 i2c6 { 2399 i2c6_xfer: i2c6-xfer { 2400 rockchip,pins = 2401 <2 RK_PB2 2 &pcfg_pull_none>, 2402 <2 RK_PB1 2 &pcfg_pull_none>; 2403 }; 2404 }; 2405 2406 i2c7 { 2407 i2c7_xfer: i2c7-xfer { 2408 rockchip,pins = 2409 <2 RK_PB0 2 &pcfg_pull_none>, 2410 <2 RK_PA7 2 &pcfg_pull_none>; 2411 }; 2412 }; 2413 2414 i2c8 { 2415 i2c8_xfer: i2c8-xfer { 2416 rockchip,pins = 2417 <1 RK_PC5 1 &pcfg_pull_none>, 2418 <1 RK_PC4 1 &pcfg_pull_none>; 2419 }; 2420 }; 2421 2422 i2s0 { 2423 i2s0_2ch_bus: i2s0-2ch-bus { 2424 rockchip,pins = 2425 <3 RK_PD0 1 &pcfg_pull_none>, 2426 <3 RK_PD1 1 &pcfg_pull_none>, 2427 <3 RK_PD2 1 &pcfg_pull_none>, 2428 <3 RK_PD3 1 &pcfg_pull_none>, 2429 <3 RK_PD7 1 &pcfg_pull_none>, 2430 <4 RK_PA0 1 &pcfg_pull_none>; 2431 }; 2432 2433 i2s0_8ch_bus: i2s0-8ch-bus { 2434 rockchip,pins = 2435 <3 RK_PD0 1 &pcfg_pull_none>, 2436 <3 RK_PD1 1 &pcfg_pull_none>, 2437 <3 RK_PD2 1 &pcfg_pull_none>, 2438 <3 RK_PD3 1 &pcfg_pull_none>, 2439 <3 RK_PD4 1 &pcfg_pull_none>, 2440 <3 RK_PD5 1 &pcfg_pull_none>, 2441 <3 RK_PD6 1 &pcfg_pull_none>, 2442 <3 RK_PD7 1 &pcfg_pull_none>, 2443 <4 RK_PA0 1 &pcfg_pull_none>; 2444 }; 2445 2446 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { 2447 rockchip,pins = 2448 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 2449 <3 RK_PD1 1 &pcfg_pull_none>, 2450 <3 RK_PD2 1 &pcfg_pull_none>, 2451 <3 RK_PD3 1 &pcfg_pull_none>, 2452 <3 RK_PD4 1 &pcfg_pull_none>, 2453 <3 RK_PD5 1 &pcfg_pull_none>, 2454 <3 RK_PD6 1 &pcfg_pull_none>, 2455 <3 RK_PD7 1 &pcfg_pull_none>, 2456 <4 RK_PA0 1 &pcfg_pull_none>; 2457 }; 2458 }; 2459 2460 i2s1 { 2461 i2s1_2ch_bus: i2s1-2ch-bus { 2462 rockchip,pins = 2463 <4 RK_PA3 1 &pcfg_pull_none>, 2464 <4 RK_PA4 1 &pcfg_pull_none>, 2465 <4 RK_PA5 1 &pcfg_pull_none>, 2466 <4 RK_PA6 1 &pcfg_pull_none>, 2467 <4 RK_PA7 1 &pcfg_pull_none>; 2468 }; 2469 2470 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { 2471 rockchip,pins = 2472 <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, 2473 <4 RK_PA4 1 &pcfg_pull_none>, 2474 <4 RK_PA5 1 &pcfg_pull_none>, 2475 <4 RK_PA6 1 &pcfg_pull_none>, 2476 <4 RK_PA7 1 &pcfg_pull_none>; 2477 }; 2478 }; 2479 2480 sdio0 { 2481 sdio0_bus1: sdio0-bus1 { 2482 rockchip,pins = 2483 <2 RK_PC4 1 &pcfg_pull_up>; 2484 }; 2485 2486 sdio0_bus4: sdio0-bus4 { 2487 rockchip,pins = 2488 <2 RK_PC4 1 &pcfg_pull_up>, 2489 <2 RK_PC5 1 &pcfg_pull_up>, 2490 <2 RK_PC6 1 &pcfg_pull_up>, 2491 <2 RK_PC7 1 &pcfg_pull_up>; 2492 }; 2493 2494 sdio0_cmd: sdio0-cmd { 2495 rockchip,pins = 2496 <2 RK_PD0 1 &pcfg_pull_up>; 2497 }; 2498 2499 sdio0_clk: sdio0-clk { 2500 rockchip,pins = 2501 <2 RK_PD1 1 &pcfg_pull_none>; 2502 }; 2503 2504 sdio0_cd: sdio0-cd { 2505 rockchip,pins = 2506 <2 RK_PD2 1 &pcfg_pull_up>; 2507 }; 2508 2509 sdio0_pwr: sdio0-pwr { 2510 rockchip,pins = 2511 <2 RK_PD3 1 &pcfg_pull_up>; 2512 }; 2513 2514 sdio0_bkpwr: sdio0-bkpwr { 2515 rockchip,pins = 2516 <2 RK_PD4 1 &pcfg_pull_up>; 2517 }; 2518 2519 sdio0_wp: sdio0-wp { 2520 rockchip,pins = 2521 <0 RK_PA3 1 &pcfg_pull_up>; 2522 }; 2523 2524 sdio0_int: sdio0-int { 2525 rockchip,pins = 2526 <0 RK_PA4 1 &pcfg_pull_up>; 2527 }; 2528 }; 2529 2530 sdmmc { 2531 sdmmc_bus1: sdmmc-bus1 { 2532 rockchip,pins = 2533 <4 RK_PB0 1 &pcfg_pull_up>; 2534 }; 2535 2536 sdmmc_bus4: sdmmc-bus4 { 2537 rockchip,pins = 2538 <4 RK_PB0 1 &pcfg_pull_up>, 2539 <4 RK_PB1 1 &pcfg_pull_up>, 2540 <4 RK_PB2 1 &pcfg_pull_up>, 2541 <4 RK_PB3 1 &pcfg_pull_up>; 2542 }; 2543 2544 sdmmc_clk: sdmmc-clk { 2545 rockchip,pins = 2546 <4 RK_PB4 1 &pcfg_pull_none>; 2547 }; 2548 2549 sdmmc_cmd: sdmmc-cmd { 2550 rockchip,pins = 2551 <4 RK_PB5 1 &pcfg_pull_up>; 2552 }; 2553 2554 sdmmc_cd: sdmmc-cd { 2555 rockchip,pins = 2556 <0 RK_PA7 1 &pcfg_pull_up>; 2557 }; 2558 2559 sdmmc_wp: sdmmc-wp { 2560 rockchip,pins = 2561 <0 RK_PB0 1 &pcfg_pull_up>; 2562 }; 2563 }; 2564 2565 suspend { 2566 ap_pwroff: ap-pwroff { 2567 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2568 }; 2569 2570 ddrio_pwroff: ddrio-pwroff { 2571 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2572 }; 2573 }; 2574 2575 spdif { 2576 spdif_bus: spdif-bus { 2577 rockchip,pins = 2578 <4 RK_PC5 1 &pcfg_pull_none>; 2579 }; 2580 2581 spdif_bus_1: spdif-bus-1 { 2582 rockchip,pins = 2583 <3 RK_PC0 3 &pcfg_pull_none>; 2584 }; 2585 }; 2586 2587 spi0 { 2588 spi0_clk: spi0-clk { 2589 rockchip,pins = 2590 <3 RK_PA6 2 &pcfg_pull_up>; 2591 }; 2592 spi0_cs0: spi0-cs0 { 2593 rockchip,pins = 2594 <3 RK_PA7 2 &pcfg_pull_up>; 2595 }; 2596 spi0_cs1: spi0-cs1 { 2597 rockchip,pins = 2598 <3 RK_PB0 2 &pcfg_pull_up>; 2599 }; 2600 spi0_tx: spi0-tx { 2601 rockchip,pins = 2602 <3 RK_PA5 2 &pcfg_pull_up>; 2603 }; 2604 spi0_rx: spi0-rx { 2605 rockchip,pins = 2606 <3 RK_PA4 2 &pcfg_pull_up>; 2607 }; 2608 }; 2609 2610 spi1 { 2611 spi1_clk: spi1-clk { 2612 rockchip,pins = 2613 <1 RK_PB1 2 &pcfg_pull_up>; 2614 }; 2615 spi1_cs0: spi1-cs0 { 2616 rockchip,pins = 2617 <1 RK_PB2 2 &pcfg_pull_up>; 2618 }; 2619 spi1_rx: spi1-rx { 2620 rockchip,pins = 2621 <1 RK_PA7 2 &pcfg_pull_up>; 2622 }; 2623 spi1_tx: spi1-tx { 2624 rockchip,pins = 2625 <1 RK_PB0 2 &pcfg_pull_up>; 2626 }; 2627 }; 2628 2629 spi2 { 2630 spi2_clk: spi2-clk { 2631 rockchip,pins = 2632 <2 RK_PB3 1 &pcfg_pull_up>; 2633 }; 2634 spi2_cs0: spi2-cs0 { 2635 rockchip,pins = 2636 <2 RK_PB4 1 &pcfg_pull_up>; 2637 }; 2638 spi2_rx: spi2-rx { 2639 rockchip,pins = 2640 <2 RK_PB1 1 &pcfg_pull_up>; 2641 }; 2642 spi2_tx: spi2-tx { 2643 rockchip,pins = 2644 <2 RK_PB2 1 &pcfg_pull_up>; 2645 }; 2646 }; 2647 2648 spi3 { 2649 spi3_clk: spi3-clk { 2650 rockchip,pins = 2651 <1 RK_PC1 1 &pcfg_pull_up>; 2652 }; 2653 spi3_cs0: spi3-cs0 { 2654 rockchip,pins = 2655 <1 RK_PC2 1 &pcfg_pull_up>; 2656 }; 2657 spi3_rx: spi3-rx { 2658 rockchip,pins = 2659 <1 RK_PB7 1 &pcfg_pull_up>; 2660 }; 2661 spi3_tx: spi3-tx { 2662 rockchip,pins = 2663 <1 RK_PC0 1 &pcfg_pull_up>; 2664 }; 2665 }; 2666 2667 spi4 { 2668 spi4_clk: spi4-clk { 2669 rockchip,pins = 2670 <3 RK_PA2 2 &pcfg_pull_up>; 2671 }; 2672 spi4_cs0: spi4-cs0 { 2673 rockchip,pins = 2674 <3 RK_PA3 2 &pcfg_pull_up>; 2675 }; 2676 spi4_rx: spi4-rx { 2677 rockchip,pins = 2678 <3 RK_PA0 2 &pcfg_pull_up>; 2679 }; 2680 spi4_tx: spi4-tx { 2681 rockchip,pins = 2682 <3 RK_PA1 2 &pcfg_pull_up>; 2683 }; 2684 }; 2685 2686 spi5 { 2687 spi5_clk: spi5-clk { 2688 rockchip,pins = 2689 <2 RK_PC6 2 &pcfg_pull_up>; 2690 }; 2691 spi5_cs0: spi5-cs0 { 2692 rockchip,pins = 2693 <2 RK_PC7 2 &pcfg_pull_up>; 2694 }; 2695 spi5_rx: spi5-rx { 2696 rockchip,pins = 2697 <2 RK_PC4 2 &pcfg_pull_up>; 2698 }; 2699 spi5_tx: spi5-tx { 2700 rockchip,pins = 2701 <2 RK_PC5 2 &pcfg_pull_up>; 2702 }; 2703 }; 2704 2705 testclk { 2706 test_clkout0: test-clkout0 { 2707 rockchip,pins = 2708 <0 RK_PA0 1 &pcfg_pull_none>; 2709 }; 2710 2711 test_clkout1: test-clkout1 { 2712 rockchip,pins = 2713 <2 RK_PD1 2 &pcfg_pull_none>; 2714 }; 2715 2716 test_clkout2: test-clkout2 { 2717 rockchip,pins = 2718 <0 RK_PB0 3 &pcfg_pull_none>; 2719 }; 2720 }; 2721 2722 tsadc { 2723 otp_pin: otp-pin { 2724 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2725 }; 2726 2727 otp_out: otp-out { 2728 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2729 }; 2730 }; 2731 2732 uart0 { 2733 uart0_xfer: uart0-xfer { 2734 rockchip,pins = 2735 <2 RK_PC0 1 &pcfg_pull_up>, 2736 <2 RK_PC1 1 &pcfg_pull_none>; 2737 }; 2738 2739 uart0_cts: uart0-cts { 2740 rockchip,pins = 2741 <2 RK_PC2 1 &pcfg_pull_none>; 2742 }; 2743 2744 uart0_rts: uart0-rts { 2745 rockchip,pins = 2746 <2 RK_PC3 1 &pcfg_pull_none>; 2747 }; 2748 }; 2749 2750 uart1 { 2751 uart1_xfer: uart1-xfer { 2752 rockchip,pins = 2753 <3 RK_PB4 2 &pcfg_pull_up>, 2754 <3 RK_PB5 2 &pcfg_pull_none>; 2755 }; 2756 }; 2757 2758 uart2a { 2759 uart2a_xfer: uart2a-xfer { 2760 rockchip,pins = 2761 <4 RK_PB0 2 &pcfg_pull_up>, 2762 <4 RK_PB1 2 &pcfg_pull_none>; 2763 }; 2764 }; 2765 2766 uart2b { 2767 uart2b_xfer: uart2b-xfer { 2768 rockchip,pins = 2769 <4 RK_PC0 2 &pcfg_pull_up>, 2770 <4 RK_PC1 2 &pcfg_pull_none>; 2771 }; 2772 }; 2773 2774 uart2c { 2775 uart2c_xfer: uart2c-xfer { 2776 rockchip,pins = 2777 <4 RK_PC3 1 &pcfg_pull_up>, 2778 <4 RK_PC4 1 &pcfg_pull_none>; 2779 }; 2780 }; 2781 2782 uart3 { 2783 uart3_xfer: uart3-xfer { 2784 rockchip,pins = 2785 <3 RK_PB6 2 &pcfg_pull_up>, 2786 <3 RK_PB7 2 &pcfg_pull_none>; 2787 }; 2788 2789 uart3_cts: uart3-cts { 2790 rockchip,pins = 2791 <3 RK_PC0 2 &pcfg_pull_none>; 2792 }; 2793 2794 uart3_rts: uart3-rts { 2795 rockchip,pins = 2796 <3 RK_PC1 2 &pcfg_pull_none>; 2797 }; 2798 }; 2799 2800 uart4 { 2801 uart4_xfer: uart4-xfer { 2802 rockchip,pins = 2803 <1 RK_PA7 1 &pcfg_pull_up>, 2804 <1 RK_PB0 1 &pcfg_pull_none>; 2805 }; 2806 }; 2807 2808 uarthdcp { 2809 uarthdcp_xfer: uarthdcp-xfer { 2810 rockchip,pins = 2811 <4 RK_PC5 2 &pcfg_pull_up>, 2812 <4 RK_PC6 2 &pcfg_pull_none>; 2813 }; 2814 }; 2815 2816 pwm0 { 2817 pwm0_pin: pwm0-pin { 2818 rockchip,pins = 2819 <4 RK_PC2 1 &pcfg_pull_none>; 2820 }; 2821 2822 pwm0_pin_pull_down: pwm0-pin-pull-down { 2823 rockchip,pins = 2824 <4 RK_PC2 1 &pcfg_pull_down>; 2825 }; 2826 2827 vop0_pwm_pin: vop0-pwm-pin { 2828 rockchip,pins = 2829 <4 RK_PC2 2 &pcfg_pull_none>; 2830 }; 2831 2832 vop1_pwm_pin: vop1-pwm-pin { 2833 rockchip,pins = 2834 <4 RK_PC2 3 &pcfg_pull_none>; 2835 }; 2836 }; 2837 2838 pwm1 { 2839 pwm1_pin: pwm1-pin { 2840 rockchip,pins = 2841 <4 RK_PC6 1 &pcfg_pull_none>; 2842 }; 2843 2844 pwm1_pin_pull_down: pwm1-pin-pull-down { 2845 rockchip,pins = 2846 <4 RK_PC6 1 &pcfg_pull_down>; 2847 }; 2848 }; 2849 2850 pwm2 { 2851 pwm2_pin: pwm2-pin { 2852 rockchip,pins = 2853 <1 RK_PC3 1 &pcfg_pull_none>; 2854 }; 2855 2856 pwm2_pin_pull_down: pwm2-pin-pull-down { 2857 rockchip,pins = 2858 <1 RK_PC3 1 &pcfg_pull_down>; 2859 }; 2860 }; 2861 2862 pwm3a { 2863 pwm3a_pin: pwm3a-pin { 2864 rockchip,pins = 2865 <0 RK_PA6 1 &pcfg_pull_none>; 2866 }; 2867 }; 2868 2869 pwm3b { 2870 pwm3b_pin: pwm3b-pin { 2871 rockchip,pins = 2872 <1 RK_PB6 1 &pcfg_pull_none>; 2873 }; 2874 }; 2875 2876 hdmi { 2877 hdmi_i2c_xfer: hdmi-i2c-xfer { 2878 rockchip,pins = 2879 <4 RK_PC1 3 &pcfg_pull_none>, 2880 <4 RK_PC0 3 &pcfg_pull_none>; 2881 }; 2882 2883 hdmi_cec: hdmi-cec { 2884 rockchip,pins = 2885 <4 RK_PC7 1 &pcfg_pull_none>; 2886 }; 2887 }; 2888 2889 pcie { 2890 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2891 rockchip,pins = 2892 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2893 }; 2894 2895 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2896 rockchip,pins = 2897 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2898 }; 2899 }; 2900 2901 }; 2902}; 2903