1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11 12/ { 13 compatible = "rockchip,rk3588"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu_l0>; 27 }; 28 core1 { 29 cpu = <&cpu_l1>; 30 }; 31 core2 { 32 cpu = <&cpu_l2>; 33 }; 34 core3 { 35 cpu = <&cpu_l3>; 36 }; 37 }; 38 cluster1 { 39 core0 { 40 cpu = <&cpu_b0>; 41 }; 42 core1 { 43 cpu = <&cpu_b1>; 44 }; 45 }; 46 cluster2 { 47 core0 { 48 cpu = <&cpu_b2>; 49 }; 50 core1 { 51 cpu = <&cpu_b3>; 52 }; 53 }; 54 }; 55 56 cpu_l0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x0>; 60 enable-method = "psci"; 61 capacity-dmips-mhz = <530>; 62 clocks = <&scmi_clk SCMI_CLK_CPUL>; 63 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 64 assigned-clock-rates = <816000000>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 i-cache-size = <32768>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <128>; 69 d-cache-size = <32768>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&l2_cache_l0>; 73 dynamic-power-coefficient = <228>; 74 #cooling-cells = <2>; 75 }; 76 77 cpu_l1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x100>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <530>; 83 clocks = <&scmi_clk SCMI_CLK_CPUL>; 84 cpu-idle-states = <&CPU_SLEEP>; 85 i-cache-size = <32768>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <128>; 88 d-cache-size = <32768>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <128>; 91 next-level-cache = <&l2_cache_l1>; 92 dynamic-power-coefficient = <228>; 93 #cooling-cells = <2>; 94 }; 95 96 cpu_l2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x200>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <530>; 102 clocks = <&scmi_clk SCMI_CLK_CPUL>; 103 cpu-idle-states = <&CPU_SLEEP>; 104 i-cache-size = <32768>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <128>; 107 d-cache-size = <32768>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <128>; 110 next-level-cache = <&l2_cache_l2>; 111 dynamic-power-coefficient = <228>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu_l3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x300>; 119 enable-method = "psci"; 120 capacity-dmips-mhz = <530>; 121 clocks = <&scmi_clk SCMI_CLK_CPUL>; 122 cpu-idle-states = <&CPU_SLEEP>; 123 i-cache-size = <32768>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <128>; 126 d-cache-size = <32768>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&l2_cache_l3>; 130 dynamic-power-coefficient = <228>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu_b0: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a76"; 137 reg = <0x400>; 138 enable-method = "psci"; 139 capacity-dmips-mhz = <1024>; 140 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 141 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 142 assigned-clock-rates = <816000000>; 143 cpu-idle-states = <&CPU_SLEEP>; 144 i-cache-size = <65536>; 145 i-cache-line-size = <64>; 146 i-cache-sets = <256>; 147 d-cache-size = <65536>; 148 d-cache-line-size = <64>; 149 d-cache-sets = <256>; 150 next-level-cache = <&l2_cache_b0>; 151 dynamic-power-coefficient = <416>; 152 #cooling-cells = <2>; 153 }; 154 155 cpu_b1: cpu@500 { 156 device_type = "cpu"; 157 compatible = "arm,cortex-a76"; 158 reg = <0x500>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 162 cpu-idle-states = <&CPU_SLEEP>; 163 i-cache-size = <65536>; 164 i-cache-line-size = <64>; 165 i-cache-sets = <256>; 166 d-cache-size = <65536>; 167 d-cache-line-size = <64>; 168 d-cache-sets = <256>; 169 next-level-cache = <&l2_cache_b1>; 170 dynamic-power-coefficient = <416>; 171 #cooling-cells = <2>; 172 }; 173 174 cpu_b2: cpu@600 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a76"; 177 reg = <0x600>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1024>; 180 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 181 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 182 assigned-clock-rates = <816000000>; 183 cpu-idle-states = <&CPU_SLEEP>; 184 i-cache-size = <65536>; 185 i-cache-line-size = <64>; 186 i-cache-sets = <256>; 187 d-cache-size = <65536>; 188 d-cache-line-size = <64>; 189 d-cache-sets = <256>; 190 next-level-cache = <&l2_cache_b2>; 191 dynamic-power-coefficient = <416>; 192 #cooling-cells = <2>; 193 }; 194 195 cpu_b3: cpu@700 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a76"; 198 reg = <0x700>; 199 enable-method = "psci"; 200 capacity-dmips-mhz = <1024>; 201 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 202 cpu-idle-states = <&CPU_SLEEP>; 203 i-cache-size = <65536>; 204 i-cache-line-size = <64>; 205 i-cache-sets = <256>; 206 d-cache-size = <65536>; 207 d-cache-line-size = <64>; 208 d-cache-sets = <256>; 209 next-level-cache = <&l2_cache_b3>; 210 dynamic-power-coefficient = <416>; 211 #cooling-cells = <2>; 212 }; 213 214 idle-states { 215 entry-method = "psci"; 216 CPU_SLEEP: cpu-sleep { 217 compatible = "arm,idle-state"; 218 local-timer-stop; 219 arm,psci-suspend-param = <0x0010000>; 220 entry-latency-us = <100>; 221 exit-latency-us = <120>; 222 min-residency-us = <1000>; 223 }; 224 }; 225 226 l2_cache_l0: l2-cache-l0 { 227 compatible = "cache"; 228 cache-size = <131072>; 229 cache-line-size = <64>; 230 cache-sets = <512>; 231 cache-level = <2>; 232 cache-unified; 233 next-level-cache = <&l3_cache>; 234 }; 235 236 l2_cache_l1: l2-cache-l1 { 237 compatible = "cache"; 238 cache-size = <131072>; 239 cache-line-size = <64>; 240 cache-sets = <512>; 241 cache-level = <2>; 242 cache-unified; 243 next-level-cache = <&l3_cache>; 244 }; 245 246 l2_cache_l2: l2-cache-l2 { 247 compatible = "cache"; 248 cache-size = <131072>; 249 cache-line-size = <64>; 250 cache-sets = <512>; 251 cache-level = <2>; 252 cache-unified; 253 next-level-cache = <&l3_cache>; 254 }; 255 256 l2_cache_l3: l2-cache-l3 { 257 compatible = "cache"; 258 cache-size = <131072>; 259 cache-line-size = <64>; 260 cache-sets = <512>; 261 cache-level = <2>; 262 cache-unified; 263 next-level-cache = <&l3_cache>; 264 }; 265 266 l2_cache_b0: l2-cache-b0 { 267 compatible = "cache"; 268 cache-size = <524288>; 269 cache-line-size = <64>; 270 cache-sets = <1024>; 271 cache-level = <2>; 272 cache-unified; 273 next-level-cache = <&l3_cache>; 274 }; 275 276 l2_cache_b1: l2-cache-b1 { 277 compatible = "cache"; 278 cache-size = <524288>; 279 cache-line-size = <64>; 280 cache-sets = <1024>; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&l3_cache>; 284 }; 285 286 l2_cache_b2: l2-cache-b2 { 287 compatible = "cache"; 288 cache-size = <524288>; 289 cache-line-size = <64>; 290 cache-sets = <1024>; 291 cache-level = <2>; 292 cache-unified; 293 next-level-cache = <&l3_cache>; 294 }; 295 296 l2_cache_b3: l2-cache-b3 { 297 compatible = "cache"; 298 cache-size = <524288>; 299 cache-line-size = <64>; 300 cache-sets = <1024>; 301 cache-level = <2>; 302 cache-unified; 303 next-level-cache = <&l3_cache>; 304 }; 305 306 l3_cache: l3-cache { 307 compatible = "cache"; 308 cache-size = <3145728>; 309 cache-line-size = <64>; 310 cache-sets = <4096>; 311 cache-level = <3>; 312 cache-unified; 313 }; 314 }; 315 316 firmware { 317 optee: optee { 318 compatible = "linaro,optee-tz"; 319 method = "smc"; 320 }; 321 322 scmi: scmi { 323 compatible = "arm,scmi-smc"; 324 arm,smc-id = <0x82000010>; 325 shmem = <&scmi_shmem>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 scmi_clk: protocol@14 { 330 reg = <0x14>; 331 #clock-cells = <1>; 332 }; 333 334 scmi_reset: protocol@16 { 335 reg = <0x16>; 336 #reset-cells = <1>; 337 }; 338 }; 339 }; 340 341 pmu-a55 { 342 compatible = "arm,cortex-a55-pmu"; 343 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 344 }; 345 346 pmu-a76 { 347 compatible = "arm,cortex-a76-pmu"; 348 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 349 }; 350 351 psci { 352 compatible = "arm,psci-1.0"; 353 method = "smc"; 354 }; 355 356 spll: clock-0 { 357 compatible = "fixed-clock"; 358 clock-frequency = <702000000>; 359 clock-output-names = "spll"; 360 #clock-cells = <0>; 361 }; 362 363 timer { 364 compatible = "arm,armv8-timer"; 365 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 366 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 367 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 368 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 369 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 370 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 371 }; 372 373 xin24m: clock-1 { 374 compatible = "fixed-clock"; 375 clock-frequency = <24000000>; 376 clock-output-names = "xin24m"; 377 #clock-cells = <0>; 378 }; 379 380 xin32k: clock-2 { 381 compatible = "fixed-clock"; 382 clock-frequency = <32768>; 383 clock-output-names = "xin32k"; 384 #clock-cells = <0>; 385 }; 386 387 pmu_sram: sram@10f000 { 388 compatible = "mmio-sram"; 389 reg = <0x0 0x0010f000 0x0 0x100>; 390 ranges = <0 0x0 0x0010f000 0x100>; 391 #address-cells = <1>; 392 #size-cells = <1>; 393 394 scmi_shmem: sram@0 { 395 compatible = "arm,scmi-shmem"; 396 reg = <0x0 0x100>; 397 }; 398 }; 399 400 sys_grf: syscon@fd58c000 { 401 compatible = "rockchip,rk3588-sys-grf", "syscon"; 402 reg = <0x0 0xfd58c000 0x0 0x1000>; 403 }; 404 405 php_grf: syscon@fd5b0000 { 406 compatible = "rockchip,rk3588-php-grf", "syscon"; 407 reg = <0x0 0xfd5b0000 0x0 0x1000>; 408 }; 409 410 ioc: syscon@fd5f0000 { 411 compatible = "rockchip,rk3588-ioc", "syscon"; 412 reg = <0x0 0xfd5f0000 0x0 0x10000>; 413 }; 414 415 system_sram1: sram@fd600000 { 416 compatible = "mmio-sram"; 417 reg = <0x0 0xfd600000 0x0 0x100000>; 418 ranges = <0x0 0x0 0xfd600000 0x100000>; 419 #address-cells = <1>; 420 #size-cells = <1>; 421 }; 422 423 cru: clock-controller@fd7c0000 { 424 compatible = "rockchip,rk3588-cru"; 425 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 426 assigned-clocks = 427 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 428 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 429 <&cru ACLK_CENTER_ROOT>, 430 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 431 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 432 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 433 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 434 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 435 <&cru CLK_GPU>; 436 assigned-clock-rates = 437 <1100000000>, <786432000>, 438 <850000000>, <1188000000>, 439 <702000000>, 440 <400000000>, <500000000>, 441 <800000000>, <100000000>, 442 <400000000>, <100000000>, 443 <200000000>, <500000000>, 444 <375000000>, <150000000>, 445 <200000000>; 446 rockchip,grf = <&php_grf>; 447 #clock-cells = <1>; 448 #reset-cells = <1>; 449 }; 450 451 i2c0: i2c@fd880000 { 452 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 453 reg = <0x0 0xfd880000 0x0 0x1000>; 454 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 455 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 456 clock-names = "i2c", "pclk"; 457 pinctrl-0 = <&i2c0m0_xfer>; 458 pinctrl-names = "default"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 status = "disabled"; 462 }; 463 464 uart0: serial@fd890000 { 465 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 466 reg = <0x0 0xfd890000 0x0 0x100>; 467 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 468 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 469 clock-names = "baudclk", "apb_pclk"; 470 dmas = <&dmac0 6>, <&dmac0 7>; 471 dma-names = "tx", "rx"; 472 pinctrl-0 = <&uart0m1_xfer>; 473 pinctrl-names = "default"; 474 reg-shift = <2>; 475 reg-io-width = <4>; 476 status = "disabled"; 477 }; 478 479 pwm0: pwm@fd8b0000 { 480 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 481 reg = <0x0 0xfd8b0000 0x0 0x10>; 482 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 483 clock-names = "pwm", "pclk"; 484 pinctrl-0 = <&pwm0m0_pins>; 485 pinctrl-names = "default"; 486 #pwm-cells = <3>; 487 status = "disabled"; 488 }; 489 490 pwm1: pwm@fd8b0010 { 491 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 492 reg = <0x0 0xfd8b0010 0x0 0x10>; 493 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 494 clock-names = "pwm", "pclk"; 495 pinctrl-0 = <&pwm1m0_pins>; 496 pinctrl-names = "default"; 497 #pwm-cells = <3>; 498 status = "disabled"; 499 }; 500 501 pwm2: pwm@fd8b0020 { 502 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 503 reg = <0x0 0xfd8b0020 0x0 0x10>; 504 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 505 clock-names = "pwm", "pclk"; 506 pinctrl-0 = <&pwm2m0_pins>; 507 pinctrl-names = "default"; 508 #pwm-cells = <3>; 509 status = "disabled"; 510 }; 511 512 pwm3: pwm@fd8b0030 { 513 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 514 reg = <0x0 0xfd8b0030 0x0 0x10>; 515 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 516 clock-names = "pwm", "pclk"; 517 pinctrl-0 = <&pwm3m0_pins>; 518 pinctrl-names = "default"; 519 #pwm-cells = <3>; 520 status = "disabled"; 521 }; 522 523 pmu: power-management@fd8d8000 { 524 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 525 reg = <0x0 0xfd8d8000 0x0 0x400>; 526 527 power: power-controller { 528 compatible = "rockchip,rk3588-power-controller"; 529 #address-cells = <1>; 530 #power-domain-cells = <1>; 531 #size-cells = <0>; 532 status = "okay"; 533 534 /* These power domains are grouped by VD_NPU */ 535 power-domain@RK3588_PD_NPU { 536 reg = <RK3588_PD_NPU>; 537 #power-domain-cells = <0>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 541 power-domain@RK3588_PD_NPUTOP { 542 reg = <RK3588_PD_NPUTOP>; 543 clocks = <&cru HCLK_NPU_ROOT>, 544 <&cru PCLK_NPU_ROOT>, 545 <&cru CLK_NPU_DSU0>, 546 <&cru HCLK_NPU_CM0_ROOT>; 547 pm_qos = <&qos_npu0_mwr>, 548 <&qos_npu0_mro>, 549 <&qos_mcu_npu>; 550 #power-domain-cells = <0>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 554 power-domain@RK3588_PD_NPU1 { 555 reg = <RK3588_PD_NPU1>; 556 clocks = <&cru HCLK_NPU_ROOT>, 557 <&cru PCLK_NPU_ROOT>, 558 <&cru CLK_NPU_DSU0>; 559 pm_qos = <&qos_npu1>; 560 #power-domain-cells = <0>; 561 }; 562 power-domain@RK3588_PD_NPU2 { 563 reg = <RK3588_PD_NPU2>; 564 clocks = <&cru HCLK_NPU_ROOT>, 565 <&cru PCLK_NPU_ROOT>, 566 <&cru CLK_NPU_DSU0>; 567 pm_qos = <&qos_npu2>; 568 #power-domain-cells = <0>; 569 }; 570 }; 571 }; 572 /* These power domains are grouped by VD_GPU */ 573 power-domain@RK3588_PD_GPU { 574 reg = <RK3588_PD_GPU>; 575 clocks = <&cru CLK_GPU>, 576 <&cru CLK_GPU_COREGROUP>, 577 <&cru CLK_GPU_STACKS>; 578 pm_qos = <&qos_gpu_m0>, 579 <&qos_gpu_m1>, 580 <&qos_gpu_m2>, 581 <&qos_gpu_m3>; 582 #power-domain-cells = <0>; 583 }; 584 /* These power domains are grouped by VD_VCODEC */ 585 power-domain@RK3588_PD_VCODEC { 586 reg = <RK3588_PD_VCODEC>; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 #power-domain-cells = <0>; 590 591 power-domain@RK3588_PD_RKVDEC0 { 592 reg = <RK3588_PD_RKVDEC0>; 593 clocks = <&cru HCLK_RKVDEC0>, 594 <&cru HCLK_VDPU_ROOT>, 595 <&cru ACLK_VDPU_ROOT>, 596 <&cru ACLK_RKVDEC0>, 597 <&cru ACLK_RKVDEC_CCU>; 598 pm_qos = <&qos_rkvdec0>; 599 #power-domain-cells = <0>; 600 }; 601 power-domain@RK3588_PD_RKVDEC1 { 602 reg = <RK3588_PD_RKVDEC1>; 603 clocks = <&cru HCLK_RKVDEC1>, 604 <&cru HCLK_VDPU_ROOT>, 605 <&cru ACLK_VDPU_ROOT>, 606 <&cru ACLK_RKVDEC1>; 607 pm_qos = <&qos_rkvdec1>; 608 #power-domain-cells = <0>; 609 }; 610 power-domain@RK3588_PD_VENC0 { 611 reg = <RK3588_PD_VENC0>; 612 clocks = <&cru HCLK_RKVENC0>, 613 <&cru ACLK_RKVENC0>; 614 pm_qos = <&qos_rkvenc0_m0ro>, 615 <&qos_rkvenc0_m1ro>, 616 <&qos_rkvenc0_m2wo>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 #power-domain-cells = <0>; 620 621 power-domain@RK3588_PD_VENC1 { 622 reg = <RK3588_PD_VENC1>; 623 clocks = <&cru HCLK_RKVENC1>, 624 <&cru HCLK_RKVENC0>, 625 <&cru ACLK_RKVENC0>, 626 <&cru ACLK_RKVENC1>; 627 pm_qos = <&qos_rkvenc1_m0ro>, 628 <&qos_rkvenc1_m1ro>, 629 <&qos_rkvenc1_m2wo>; 630 #power-domain-cells = <0>; 631 }; 632 }; 633 }; 634 /* These power domains are grouped by VD_LOGIC */ 635 power-domain@RK3588_PD_VDPU { 636 reg = <RK3588_PD_VDPU>; 637 clocks = <&cru HCLK_VDPU_ROOT>, 638 <&cru ACLK_VDPU_LOW_ROOT>, 639 <&cru ACLK_VDPU_ROOT>, 640 <&cru ACLK_JPEG_DECODER_ROOT>, 641 <&cru ACLK_IEP2P0>, 642 <&cru HCLK_IEP2P0>, 643 <&cru ACLK_JPEG_ENCODER0>, 644 <&cru HCLK_JPEG_ENCODER0>, 645 <&cru ACLK_JPEG_ENCODER1>, 646 <&cru HCLK_JPEG_ENCODER1>, 647 <&cru ACLK_JPEG_ENCODER2>, 648 <&cru HCLK_JPEG_ENCODER2>, 649 <&cru ACLK_JPEG_ENCODER3>, 650 <&cru HCLK_JPEG_ENCODER3>, 651 <&cru ACLK_JPEG_DECODER>, 652 <&cru HCLK_JPEG_DECODER>, 653 <&cru ACLK_RGA2>, 654 <&cru HCLK_RGA2>; 655 pm_qos = <&qos_iep>, 656 <&qos_jpeg_dec>, 657 <&qos_jpeg_enc0>, 658 <&qos_jpeg_enc1>, 659 <&qos_jpeg_enc2>, 660 <&qos_jpeg_enc3>, 661 <&qos_rga2_mro>, 662 <&qos_rga2_mwo>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 #power-domain-cells = <0>; 666 667 668 power-domain@RK3588_PD_AV1 { 669 reg = <RK3588_PD_AV1>; 670 clocks = <&cru PCLK_AV1>, 671 <&cru ACLK_AV1>, 672 <&cru HCLK_VDPU_ROOT>; 673 pm_qos = <&qos_av1>; 674 #power-domain-cells = <0>; 675 }; 676 power-domain@RK3588_PD_RKVDEC0 { 677 reg = <RK3588_PD_RKVDEC0>; 678 clocks = <&cru HCLK_RKVDEC0>, 679 <&cru HCLK_VDPU_ROOT>, 680 <&cru ACLK_VDPU_ROOT>, 681 <&cru ACLK_RKVDEC0>; 682 pm_qos = <&qos_rkvdec0>; 683 #power-domain-cells = <0>; 684 }; 685 power-domain@RK3588_PD_RKVDEC1 { 686 reg = <RK3588_PD_RKVDEC1>; 687 clocks = <&cru HCLK_RKVDEC1>, 688 <&cru HCLK_VDPU_ROOT>, 689 <&cru ACLK_VDPU_ROOT>; 690 pm_qos = <&qos_rkvdec1>; 691 #power-domain-cells = <0>; 692 }; 693 power-domain@RK3588_PD_RGA30 { 694 reg = <RK3588_PD_RGA30>; 695 clocks = <&cru ACLK_RGA3_0>, 696 <&cru HCLK_RGA3_0>; 697 pm_qos = <&qos_rga3_0>; 698 #power-domain-cells = <0>; 699 }; 700 }; 701 power-domain@RK3588_PD_VOP { 702 reg = <RK3588_PD_VOP>; 703 clocks = <&cru PCLK_VOP_ROOT>, 704 <&cru HCLK_VOP_ROOT>, 705 <&cru ACLK_VOP>; 706 pm_qos = <&qos_vop_m0>, 707 <&qos_vop_m1>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 #power-domain-cells = <0>; 711 712 power-domain@RK3588_PD_VO0 { 713 reg = <RK3588_PD_VO0>; 714 clocks = <&cru PCLK_VO0_ROOT>, 715 <&cru PCLK_VO0_S_ROOT>, 716 <&cru HCLK_VO0_S_ROOT>, 717 <&cru ACLK_VO0_ROOT>, 718 <&cru HCLK_HDCP0>, 719 <&cru ACLK_HDCP0>, 720 <&cru HCLK_VOP_ROOT>; 721 pm_qos = <&qos_hdcp0>; 722 #power-domain-cells = <0>; 723 }; 724 }; 725 power-domain@RK3588_PD_VO1 { 726 reg = <RK3588_PD_VO1>; 727 clocks = <&cru PCLK_VO1_ROOT>, 728 <&cru PCLK_VO1_S_ROOT>, 729 <&cru HCLK_VO1_S_ROOT>, 730 <&cru HCLK_HDCP1>, 731 <&cru ACLK_HDCP1>, 732 <&cru ACLK_HDMIRX_ROOT>, 733 <&cru HCLK_VO1USB_TOP_ROOT>; 734 pm_qos = <&qos_hdcp1>, 735 <&qos_hdmirx>; 736 #power-domain-cells = <0>; 737 }; 738 power-domain@RK3588_PD_VI { 739 reg = <RK3588_PD_VI>; 740 clocks = <&cru HCLK_VI_ROOT>, 741 <&cru PCLK_VI_ROOT>, 742 <&cru HCLK_ISP0>, 743 <&cru ACLK_ISP0>, 744 <&cru HCLK_VICAP>, 745 <&cru ACLK_VICAP>; 746 pm_qos = <&qos_isp0_mro>, 747 <&qos_isp0_mwo>, 748 <&qos_vicap_m0>, 749 <&qos_vicap_m1>; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 #power-domain-cells = <0>; 753 754 power-domain@RK3588_PD_ISP1 { 755 reg = <RK3588_PD_ISP1>; 756 clocks = <&cru HCLK_ISP1>, 757 <&cru ACLK_ISP1>, 758 <&cru HCLK_VI_ROOT>, 759 <&cru PCLK_VI_ROOT>; 760 pm_qos = <&qos_isp1_mwo>, 761 <&qos_isp1_mro>; 762 #power-domain-cells = <0>; 763 }; 764 power-domain@RK3588_PD_FEC { 765 reg = <RK3588_PD_FEC>; 766 clocks = <&cru HCLK_FISHEYE0>, 767 <&cru ACLK_FISHEYE0>, 768 <&cru HCLK_FISHEYE1>, 769 <&cru ACLK_FISHEYE1>, 770 <&cru PCLK_VI_ROOT>; 771 pm_qos = <&qos_fisheye0>, 772 <&qos_fisheye1>; 773 #power-domain-cells = <0>; 774 }; 775 }; 776 power-domain@RK3588_PD_RGA31 { 777 reg = <RK3588_PD_RGA31>; 778 clocks = <&cru HCLK_RGA3_1>, 779 <&cru ACLK_RGA3_1>; 780 pm_qos = <&qos_rga3_1>; 781 #power-domain-cells = <0>; 782 }; 783 power-domain@RK3588_PD_USB { 784 reg = <RK3588_PD_USB>; 785 clocks = <&cru PCLK_PHP_ROOT>, 786 <&cru ACLK_USB_ROOT>, 787 <&cru HCLK_USB_ROOT>, 788 <&cru HCLK_HOST0>, 789 <&cru HCLK_HOST_ARB0>, 790 <&cru HCLK_HOST1>, 791 <&cru HCLK_HOST_ARB1>; 792 pm_qos = <&qos_usb3_0>, 793 <&qos_usb3_1>, 794 <&qos_usb2host_0>, 795 <&qos_usb2host_1>; 796 #power-domain-cells = <0>; 797 }; 798 power-domain@RK3588_PD_GMAC { 799 reg = <RK3588_PD_GMAC>; 800 clocks = <&cru PCLK_PHP_ROOT>, 801 <&cru ACLK_PCIE_ROOT>, 802 <&cru ACLK_PHP_ROOT>; 803 #power-domain-cells = <0>; 804 }; 805 power-domain@RK3588_PD_PCIE { 806 reg = <RK3588_PD_PCIE>; 807 clocks = <&cru PCLK_PHP_ROOT>, 808 <&cru ACLK_PCIE_ROOT>, 809 <&cru ACLK_PHP_ROOT>; 810 #power-domain-cells = <0>; 811 }; 812 power-domain@RK3588_PD_SDIO { 813 reg = <RK3588_PD_SDIO>; 814 clocks = <&cru HCLK_SDIO>, 815 <&cru HCLK_NVM_ROOT>; 816 pm_qos = <&qos_sdio>; 817 #power-domain-cells = <0>; 818 }; 819 power-domain@RK3588_PD_AUDIO { 820 reg = <RK3588_PD_AUDIO>; 821 clocks = <&cru HCLK_AUDIO_ROOT>, 822 <&cru PCLK_AUDIO_ROOT>; 823 #power-domain-cells = <0>; 824 }; 825 power-domain@RK3588_PD_SDMMC { 826 reg = <RK3588_PD_SDMMC>; 827 pm_qos = <&qos_sdmmc>; 828 #power-domain-cells = <0>; 829 }; 830 }; 831 }; 832 833 i2s4_8ch: i2s@fddc0000 { 834 compatible = "rockchip,rk3588-i2s-tdm"; 835 reg = <0x0 0xfddc0000 0x0 0x1000>; 836 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 837 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 838 clock-names = "mclk_tx", "mclk_rx", "hclk"; 839 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 840 assigned-clock-parents = <&cru PLL_AUPLL>; 841 dmas = <&dmac2 0>; 842 dma-names = "tx"; 843 power-domains = <&power RK3588_PD_VO0>; 844 resets = <&cru SRST_M_I2S4_8CH_TX>; 845 reset-names = "tx-m"; 846 #sound-dai-cells = <0>; 847 status = "disabled"; 848 }; 849 850 i2s5_8ch: i2s@fddf0000 { 851 compatible = "rockchip,rk3588-i2s-tdm"; 852 reg = <0x0 0xfddf0000 0x0 0x1000>; 853 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 854 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 855 clock-names = "mclk_tx", "mclk_rx", "hclk"; 856 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 857 assigned-clock-parents = <&cru PLL_AUPLL>; 858 dmas = <&dmac2 2>; 859 dma-names = "tx"; 860 power-domains = <&power RK3588_PD_VO1>; 861 resets = <&cru SRST_M_I2S5_8CH_TX>; 862 reset-names = "tx-m"; 863 #sound-dai-cells = <0>; 864 status = "disabled"; 865 }; 866 867 i2s9_8ch: i2s@fddfc000 { 868 compatible = "rockchip,rk3588-i2s-tdm"; 869 reg = <0x0 0xfddfc000 0x0 0x1000>; 870 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 871 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 872 clock-names = "mclk_tx", "mclk_rx", "hclk"; 873 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 874 assigned-clock-parents = <&cru PLL_AUPLL>; 875 dmas = <&dmac2 23>; 876 dma-names = "rx"; 877 power-domains = <&power RK3588_PD_VO1>; 878 resets = <&cru SRST_M_I2S9_8CH_RX>; 879 reset-names = "rx-m"; 880 #sound-dai-cells = <0>; 881 status = "disabled"; 882 }; 883 884 qos_gpu_m0: qos@fdf35000 { 885 compatible = "rockchip,rk3588-qos", "syscon"; 886 reg = <0x0 0xfdf35000 0x0 0x20>; 887 }; 888 889 qos_gpu_m1: qos@fdf35200 { 890 compatible = "rockchip,rk3588-qos", "syscon"; 891 reg = <0x0 0xfdf35200 0x0 0x20>; 892 }; 893 894 qos_gpu_m2: qos@fdf35400 { 895 compatible = "rockchip,rk3588-qos", "syscon"; 896 reg = <0x0 0xfdf35400 0x0 0x20>; 897 }; 898 899 qos_gpu_m3: qos@fdf35600 { 900 compatible = "rockchip,rk3588-qos", "syscon"; 901 reg = <0x0 0xfdf35600 0x0 0x20>; 902 }; 903 904 qos_rga3_1: qos@fdf36000 { 905 compatible = "rockchip,rk3588-qos", "syscon"; 906 reg = <0x0 0xfdf36000 0x0 0x20>; 907 }; 908 909 qos_sdio: qos@fdf39000 { 910 compatible = "rockchip,rk3588-qos", "syscon"; 911 reg = <0x0 0xfdf39000 0x0 0x20>; 912 }; 913 914 qos_sdmmc: qos@fdf3d800 { 915 compatible = "rockchip,rk3588-qos", "syscon"; 916 reg = <0x0 0xfdf3d800 0x0 0x20>; 917 }; 918 919 qos_usb3_1: qos@fdf3e000 { 920 compatible = "rockchip,rk3588-qos", "syscon"; 921 reg = <0x0 0xfdf3e000 0x0 0x20>; 922 }; 923 924 qos_usb3_0: qos@fdf3e200 { 925 compatible = "rockchip,rk3588-qos", "syscon"; 926 reg = <0x0 0xfdf3e200 0x0 0x20>; 927 }; 928 929 qos_usb2host_0: qos@fdf3e400 { 930 compatible = "rockchip,rk3588-qos", "syscon"; 931 reg = <0x0 0xfdf3e400 0x0 0x20>; 932 }; 933 934 qos_usb2host_1: qos@fdf3e600 { 935 compatible = "rockchip,rk3588-qos", "syscon"; 936 reg = <0x0 0xfdf3e600 0x0 0x20>; 937 }; 938 939 qos_fisheye0: qos@fdf40000 { 940 compatible = "rockchip,rk3588-qos", "syscon"; 941 reg = <0x0 0xfdf40000 0x0 0x20>; 942 }; 943 944 qos_fisheye1: qos@fdf40200 { 945 compatible = "rockchip,rk3588-qos", "syscon"; 946 reg = <0x0 0xfdf40200 0x0 0x20>; 947 }; 948 949 qos_isp0_mro: qos@fdf40400 { 950 compatible = "rockchip,rk3588-qos", "syscon"; 951 reg = <0x0 0xfdf40400 0x0 0x20>; 952 }; 953 954 qos_isp0_mwo: qos@fdf40500 { 955 compatible = "rockchip,rk3588-qos", "syscon"; 956 reg = <0x0 0xfdf40500 0x0 0x20>; 957 }; 958 959 qos_vicap_m0: qos@fdf40600 { 960 compatible = "rockchip,rk3588-qos", "syscon"; 961 reg = <0x0 0xfdf40600 0x0 0x20>; 962 }; 963 964 qos_vicap_m1: qos@fdf40800 { 965 compatible = "rockchip,rk3588-qos", "syscon"; 966 reg = <0x0 0xfdf40800 0x0 0x20>; 967 }; 968 969 qos_isp1_mwo: qos@fdf41000 { 970 compatible = "rockchip,rk3588-qos", "syscon"; 971 reg = <0x0 0xfdf41000 0x0 0x20>; 972 }; 973 974 qos_isp1_mro: qos@fdf41100 { 975 compatible = "rockchip,rk3588-qos", "syscon"; 976 reg = <0x0 0xfdf41100 0x0 0x20>; 977 }; 978 979 qos_rkvenc0_m0ro: qos@fdf60000 { 980 compatible = "rockchip,rk3588-qos", "syscon"; 981 reg = <0x0 0xfdf60000 0x0 0x20>; 982 }; 983 984 qos_rkvenc0_m1ro: qos@fdf60200 { 985 compatible = "rockchip,rk3588-qos", "syscon"; 986 reg = <0x0 0xfdf60200 0x0 0x20>; 987 }; 988 989 qos_rkvenc0_m2wo: qos@fdf60400 { 990 compatible = "rockchip,rk3588-qos", "syscon"; 991 reg = <0x0 0xfdf60400 0x0 0x20>; 992 }; 993 994 qos_rkvenc1_m0ro: qos@fdf61000 { 995 compatible = "rockchip,rk3588-qos", "syscon"; 996 reg = <0x0 0xfdf61000 0x0 0x20>; 997 }; 998 999 qos_rkvenc1_m1ro: qos@fdf61200 { 1000 compatible = "rockchip,rk3588-qos", "syscon"; 1001 reg = <0x0 0xfdf61200 0x0 0x20>; 1002 }; 1003 1004 qos_rkvenc1_m2wo: qos@fdf61400 { 1005 compatible = "rockchip,rk3588-qos", "syscon"; 1006 reg = <0x0 0xfdf61400 0x0 0x20>; 1007 }; 1008 1009 qos_rkvdec0: qos@fdf62000 { 1010 compatible = "rockchip,rk3588-qos", "syscon"; 1011 reg = <0x0 0xfdf62000 0x0 0x20>; 1012 }; 1013 1014 qos_rkvdec1: qos@fdf63000 { 1015 compatible = "rockchip,rk3588-qos", "syscon"; 1016 reg = <0x0 0xfdf63000 0x0 0x20>; 1017 }; 1018 1019 qos_av1: qos@fdf64000 { 1020 compatible = "rockchip,rk3588-qos", "syscon"; 1021 reg = <0x0 0xfdf64000 0x0 0x20>; 1022 }; 1023 1024 qos_iep: qos@fdf66000 { 1025 compatible = "rockchip,rk3588-qos", "syscon"; 1026 reg = <0x0 0xfdf66000 0x0 0x20>; 1027 }; 1028 1029 qos_jpeg_dec: qos@fdf66200 { 1030 compatible = "rockchip,rk3588-qos", "syscon"; 1031 reg = <0x0 0xfdf66200 0x0 0x20>; 1032 }; 1033 1034 qos_jpeg_enc0: qos@fdf66400 { 1035 compatible = "rockchip,rk3588-qos", "syscon"; 1036 reg = <0x0 0xfdf66400 0x0 0x20>; 1037 }; 1038 1039 qos_jpeg_enc1: qos@fdf66600 { 1040 compatible = "rockchip,rk3588-qos", "syscon"; 1041 reg = <0x0 0xfdf66600 0x0 0x20>; 1042 }; 1043 1044 qos_jpeg_enc2: qos@fdf66800 { 1045 compatible = "rockchip,rk3588-qos", "syscon"; 1046 reg = <0x0 0xfdf66800 0x0 0x20>; 1047 }; 1048 1049 qos_jpeg_enc3: qos@fdf66a00 { 1050 compatible = "rockchip,rk3588-qos", "syscon"; 1051 reg = <0x0 0xfdf66a00 0x0 0x20>; 1052 }; 1053 1054 qos_rga2_mro: qos@fdf66c00 { 1055 compatible = "rockchip,rk3588-qos", "syscon"; 1056 reg = <0x0 0xfdf66c00 0x0 0x20>; 1057 }; 1058 1059 qos_rga2_mwo: qos@fdf66e00 { 1060 compatible = "rockchip,rk3588-qos", "syscon"; 1061 reg = <0x0 0xfdf66e00 0x0 0x20>; 1062 }; 1063 1064 qos_rga3_0: qos@fdf67000 { 1065 compatible = "rockchip,rk3588-qos", "syscon"; 1066 reg = <0x0 0xfdf67000 0x0 0x20>; 1067 }; 1068 1069 qos_vdpu: qos@fdf67200 { 1070 compatible = "rockchip,rk3588-qos", "syscon"; 1071 reg = <0x0 0xfdf67200 0x0 0x20>; 1072 }; 1073 1074 qos_npu1: qos@fdf70000 { 1075 compatible = "rockchip,rk3588-qos", "syscon"; 1076 reg = <0x0 0xfdf70000 0x0 0x20>; 1077 }; 1078 1079 qos_npu2: qos@fdf71000 { 1080 compatible = "rockchip,rk3588-qos", "syscon"; 1081 reg = <0x0 0xfdf71000 0x0 0x20>; 1082 }; 1083 1084 qos_npu0_mwr: qos@fdf72000 { 1085 compatible = "rockchip,rk3588-qos", "syscon"; 1086 reg = <0x0 0xfdf72000 0x0 0x20>; 1087 }; 1088 1089 qos_npu0_mro: qos@fdf72200 { 1090 compatible = "rockchip,rk3588-qos", "syscon"; 1091 reg = <0x0 0xfdf72200 0x0 0x20>; 1092 }; 1093 1094 qos_mcu_npu: qos@fdf72400 { 1095 compatible = "rockchip,rk3588-qos", "syscon"; 1096 reg = <0x0 0xfdf72400 0x0 0x20>; 1097 }; 1098 1099 qos_hdcp0: qos@fdf80000 { 1100 compatible = "rockchip,rk3588-qos", "syscon"; 1101 reg = <0x0 0xfdf80000 0x0 0x20>; 1102 }; 1103 1104 qos_hdcp1: qos@fdf81000 { 1105 compatible = "rockchip,rk3588-qos", "syscon"; 1106 reg = <0x0 0xfdf81000 0x0 0x20>; 1107 }; 1108 1109 qos_hdmirx: qos@fdf81200 { 1110 compatible = "rockchip,rk3588-qos", "syscon"; 1111 reg = <0x0 0xfdf81200 0x0 0x20>; 1112 }; 1113 1114 qos_vop_m0: qos@fdf82000 { 1115 compatible = "rockchip,rk3588-qos", "syscon"; 1116 reg = <0x0 0xfdf82000 0x0 0x20>; 1117 }; 1118 1119 qos_vop_m1: qos@fdf82200 { 1120 compatible = "rockchip,rk3588-qos", "syscon"; 1121 reg = <0x0 0xfdf82200 0x0 0x20>; 1122 }; 1123 1124 gmac1: ethernet@fe1c0000 { 1125 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1126 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1127 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1128 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1129 interrupt-names = "macirq", "eth_wake_irq"; 1130 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1131 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1132 <&cru CLK_GMAC1_PTP_REF>; 1133 clock-names = "stmmaceth", "clk_mac_ref", 1134 "pclk_mac", "aclk_mac", 1135 "ptp_ref"; 1136 power-domains = <&power RK3588_PD_GMAC>; 1137 resets = <&cru SRST_A_GMAC1>; 1138 reset-names = "stmmaceth"; 1139 rockchip,grf = <&sys_grf>; 1140 rockchip,php-grf = <&php_grf>; 1141 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1142 snps,mixed-burst; 1143 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1144 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1145 snps,tso; 1146 status = "disabled"; 1147 1148 mdio1: mdio { 1149 compatible = "snps,dwmac-mdio"; 1150 #address-cells = <0x1>; 1151 #size-cells = <0x0>; 1152 }; 1153 1154 gmac1_stmmac_axi_setup: stmmac-axi-config { 1155 snps,blen = <0 0 0 0 16 8 4>; 1156 snps,wr_osr_lmt = <4>; 1157 snps,rd_osr_lmt = <8>; 1158 }; 1159 1160 gmac1_mtl_rx_setup: rx-queues-config { 1161 snps,rx-queues-to-use = <2>; 1162 queue0 {}; 1163 queue1 {}; 1164 }; 1165 1166 gmac1_mtl_tx_setup: tx-queues-config { 1167 snps,tx-queues-to-use = <2>; 1168 queue0 {}; 1169 queue1 {}; 1170 }; 1171 }; 1172 1173 sdmmc: mmc@fe2c0000 { 1174 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1175 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1176 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1177 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1178 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1179 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1180 fifo-depth = <0x100>; 1181 max-frequency = <200000000>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1184 power-domains = <&power RK3588_PD_SDMMC>; 1185 status = "disabled"; 1186 }; 1187 1188 sdhci: mmc@fe2e0000 { 1189 compatible = "rockchip,rk3588-dwcmshc"; 1190 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1191 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1192 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1193 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1194 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1195 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1196 <&cru TMCLK_EMMC>; 1197 clock-names = "core", "bus", "axi", "block", "timer"; 1198 max-frequency = <200000000>; 1199 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1200 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1201 <&cru SRST_T_EMMC>; 1202 reset-names = "core", "bus", "axi", "block", "timer"; 1203 status = "disabled"; 1204 }; 1205 1206 i2s0_8ch: i2s@fe470000 { 1207 compatible = "rockchip,rk3588-i2s-tdm"; 1208 reg = <0x0 0xfe470000 0x0 0x1000>; 1209 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1210 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1211 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1212 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1213 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1214 dmas = <&dmac0 0>, <&dmac0 1>; 1215 dma-names = "tx", "rx"; 1216 power-domains = <&power RK3588_PD_AUDIO>; 1217 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1218 reset-names = "tx-m", "rx-m"; 1219 rockchip,trcm-sync-tx-only; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&i2s0_lrck 1222 &i2s0_sclk 1223 &i2s0_sdi0 1224 &i2s0_sdi1 1225 &i2s0_sdi2 1226 &i2s0_sdi3 1227 &i2s0_sdo0 1228 &i2s0_sdo1 1229 &i2s0_sdo2 1230 &i2s0_sdo3>; 1231 #sound-dai-cells = <0>; 1232 status = "disabled"; 1233 }; 1234 1235 i2s1_8ch: i2s@fe480000 { 1236 compatible = "rockchip,rk3588-i2s-tdm"; 1237 reg = <0x0 0xfe480000 0x0 0x1000>; 1238 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1239 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1240 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1241 dmas = <&dmac0 2>, <&dmac0 3>; 1242 dma-names = "tx", "rx"; 1243 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1244 reset-names = "tx-m", "rx-m"; 1245 rockchip,trcm-sync-tx-only; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&i2s1m0_lrck 1248 &i2s1m0_sclk 1249 &i2s1m0_sdi0 1250 &i2s1m0_sdi1 1251 &i2s1m0_sdi2 1252 &i2s1m0_sdi3 1253 &i2s1m0_sdo0 1254 &i2s1m0_sdo1 1255 &i2s1m0_sdo2 1256 &i2s1m0_sdo3>; 1257 #sound-dai-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 i2s2_2ch: i2s@fe490000 { 1262 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1263 reg = <0x0 0xfe490000 0x0 0x1000>; 1264 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1265 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1266 clock-names = "i2s_clk", "i2s_hclk"; 1267 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1268 assigned-clock-parents = <&cru PLL_AUPLL>; 1269 dmas = <&dmac1 0>, <&dmac1 1>; 1270 dma-names = "tx", "rx"; 1271 power-domains = <&power RK3588_PD_AUDIO>; 1272 rockchip,trcm-sync-tx-only; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&i2s2m1_lrck 1275 &i2s2m1_sclk 1276 &i2s2m1_sdi 1277 &i2s2m1_sdo>; 1278 #sound-dai-cells = <0>; 1279 status = "disabled"; 1280 }; 1281 1282 i2s3_2ch: i2s@fe4a0000 { 1283 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1284 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1285 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1286 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1287 clock-names = "i2s_clk", "i2s_hclk"; 1288 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1289 assigned-clock-parents = <&cru PLL_AUPLL>; 1290 dmas = <&dmac1 2>, <&dmac1 3>; 1291 dma-names = "tx", "rx"; 1292 power-domains = <&power RK3588_PD_AUDIO>; 1293 rockchip,trcm-sync-tx-only; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&i2s3_lrck 1296 &i2s3_sclk 1297 &i2s3_sdi 1298 &i2s3_sdo>; 1299 #sound-dai-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 gic: interrupt-controller@fe600000 { 1304 compatible = "arm,gic-v3"; 1305 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1306 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1307 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 1308 interrupt-controller; 1309 mbi-alias = <0x0 0xfe610000>; 1310 mbi-ranges = <424 56>; 1311 msi-controller; 1312 #interrupt-cells = <4>; 1313 1314 ppi-partitions { 1315 ppi_partition0: interrupt-partition-0 { 1316 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 1317 }; 1318 1319 ppi_partition1: interrupt-partition-1 { 1320 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 1321 }; 1322 }; 1323 }; 1324 1325 dmac0: dma-controller@fea10000 { 1326 compatible = "arm,pl330", "arm,primecell"; 1327 reg = <0x0 0xfea10000 0x0 0x4000>; 1328 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 1329 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 1330 arm,pl330-periph-burst; 1331 clocks = <&cru ACLK_DMAC0>; 1332 clock-names = "apb_pclk"; 1333 #dma-cells = <1>; 1334 }; 1335 1336 dmac1: dma-controller@fea30000 { 1337 compatible = "arm,pl330", "arm,primecell"; 1338 reg = <0x0 0xfea30000 0x0 0x4000>; 1339 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 1340 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 1341 arm,pl330-periph-burst; 1342 clocks = <&cru ACLK_DMAC1>; 1343 clock-names = "apb_pclk"; 1344 #dma-cells = <1>; 1345 }; 1346 1347 i2c1: i2c@fea90000 { 1348 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1349 reg = <0x0 0xfea90000 0x0 0x1000>; 1350 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1351 clock-names = "i2c", "pclk"; 1352 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 1353 pinctrl-0 = <&i2c1m0_xfer>; 1354 pinctrl-names = "default"; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 status = "disabled"; 1358 }; 1359 1360 i2c2: i2c@feaa0000 { 1361 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1362 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1363 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1364 clock-names = "i2c", "pclk"; 1365 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 1366 pinctrl-0 = <&i2c2m0_xfer>; 1367 pinctrl-names = "default"; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 i2c3: i2c@feab0000 { 1374 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1375 reg = <0x0 0xfeab0000 0x0 0x1000>; 1376 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1377 clock-names = "i2c", "pclk"; 1378 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 1379 pinctrl-0 = <&i2c3m0_xfer>; 1380 pinctrl-names = "default"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 i2c4: i2c@feac0000 { 1387 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1388 reg = <0x0 0xfeac0000 0x0 0x1000>; 1389 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1390 clock-names = "i2c", "pclk"; 1391 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 1392 pinctrl-0 = <&i2c4m0_xfer>; 1393 pinctrl-names = "default"; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 1399 i2c5: i2c@fead0000 { 1400 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1401 reg = <0x0 0xfead0000 0x0 0x1000>; 1402 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1403 clock-names = "i2c", "pclk"; 1404 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 1405 pinctrl-0 = <&i2c5m0_xfer>; 1406 pinctrl-names = "default"; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 status = "disabled"; 1410 }; 1411 1412 wdt: watchdog@feaf0000 { 1413 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 1414 reg = <0x0 0xfeaf0000 0x0 0x100>; 1415 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1416 clock-names = "tclk", "pclk"; 1417 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 1418 }; 1419 1420 spi0: spi@feb00000 { 1421 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1422 reg = <0x0 0xfeb00000 0x0 0x1000>; 1423 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 1424 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1425 clock-names = "spiclk", "apb_pclk"; 1426 dmas = <&dmac0 14>, <&dmac0 15>; 1427 dma-names = "tx", "rx"; 1428 num-cs = <2>; 1429 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1430 pinctrl-names = "default"; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 status = "disabled"; 1434 }; 1435 1436 spi1: spi@feb10000 { 1437 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1438 reg = <0x0 0xfeb10000 0x0 0x1000>; 1439 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 1440 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1441 clock-names = "spiclk", "apb_pclk"; 1442 dmas = <&dmac0 16>, <&dmac0 17>; 1443 dma-names = "tx", "rx"; 1444 num-cs = <2>; 1445 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1446 pinctrl-names = "default"; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 1452 spi2: spi@feb20000 { 1453 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1454 reg = <0x0 0xfeb20000 0x0 0x1000>; 1455 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 1456 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1457 clock-names = "spiclk", "apb_pclk"; 1458 dmas = <&dmac1 15>, <&dmac1 16>; 1459 dma-names = "tx", "rx"; 1460 num-cs = <2>; 1461 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 1462 pinctrl-names = "default"; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 spi3: spi@feb30000 { 1469 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1470 reg = <0x0 0xfeb30000 0x0 0x1000>; 1471 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 1472 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1473 clock-names = "spiclk", "apb_pclk"; 1474 dmas = <&dmac1 17>, <&dmac1 18>; 1475 dma-names = "tx", "rx"; 1476 num-cs = <2>; 1477 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1478 pinctrl-names = "default"; 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 status = "disabled"; 1482 }; 1483 1484 uart1: serial@feb40000 { 1485 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1486 reg = <0x0 0xfeb40000 0x0 0x100>; 1487 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 1488 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1489 clock-names = "baudclk", "apb_pclk"; 1490 dmas = <&dmac0 8>, <&dmac0 9>; 1491 dma-names = "tx", "rx"; 1492 pinctrl-0 = <&uart1m1_xfer>; 1493 pinctrl-names = "default"; 1494 reg-io-width = <4>; 1495 reg-shift = <2>; 1496 status = "disabled"; 1497 }; 1498 1499 uart2: serial@feb50000 { 1500 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1501 reg = <0x0 0xfeb50000 0x0 0x100>; 1502 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 1503 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1504 clock-names = "baudclk", "apb_pclk"; 1505 dmas = <&dmac0 10>, <&dmac0 11>; 1506 dma-names = "tx", "rx"; 1507 pinctrl-0 = <&uart2m1_xfer>; 1508 pinctrl-names = "default"; 1509 reg-io-width = <4>; 1510 reg-shift = <2>; 1511 status = "disabled"; 1512 }; 1513 1514 uart3: serial@feb60000 { 1515 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1516 reg = <0x0 0xfeb60000 0x0 0x100>; 1517 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 1518 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1519 clock-names = "baudclk", "apb_pclk"; 1520 dmas = <&dmac0 12>, <&dmac0 13>; 1521 dma-names = "tx", "rx"; 1522 pinctrl-0 = <&uart3m1_xfer>; 1523 pinctrl-names = "default"; 1524 reg-io-width = <4>; 1525 reg-shift = <2>; 1526 status = "disabled"; 1527 }; 1528 1529 uart4: serial@feb70000 { 1530 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1531 reg = <0x0 0xfeb70000 0x0 0x100>; 1532 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 1533 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1534 clock-names = "baudclk", "apb_pclk"; 1535 dmas = <&dmac1 9>, <&dmac1 10>; 1536 dma-names = "tx", "rx"; 1537 pinctrl-0 = <&uart4m1_xfer>; 1538 pinctrl-names = "default"; 1539 reg-io-width = <4>; 1540 reg-shift = <2>; 1541 status = "disabled"; 1542 }; 1543 1544 uart5: serial@feb80000 { 1545 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1546 reg = <0x0 0xfeb80000 0x0 0x100>; 1547 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 1548 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1549 clock-names = "baudclk", "apb_pclk"; 1550 dmas = <&dmac1 11>, <&dmac1 12>; 1551 dma-names = "tx", "rx"; 1552 pinctrl-0 = <&uart5m1_xfer>; 1553 pinctrl-names = "default"; 1554 reg-io-width = <4>; 1555 reg-shift = <2>; 1556 status = "disabled"; 1557 }; 1558 1559 uart6: serial@feb90000 { 1560 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1561 reg = <0x0 0xfeb90000 0x0 0x100>; 1562 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 1563 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1564 clock-names = "baudclk", "apb_pclk"; 1565 dmas = <&dmac1 13>, <&dmac1 14>; 1566 dma-names = "tx", "rx"; 1567 pinctrl-0 = <&uart6m1_xfer>; 1568 pinctrl-names = "default"; 1569 reg-io-width = <4>; 1570 reg-shift = <2>; 1571 status = "disabled"; 1572 }; 1573 1574 uart7: serial@feba0000 { 1575 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1576 reg = <0x0 0xfeba0000 0x0 0x100>; 1577 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 1578 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1579 clock-names = "baudclk", "apb_pclk"; 1580 dmas = <&dmac2 7>, <&dmac2 8>; 1581 dma-names = "tx", "rx"; 1582 pinctrl-0 = <&uart7m1_xfer>; 1583 pinctrl-names = "default"; 1584 reg-io-width = <4>; 1585 reg-shift = <2>; 1586 status = "disabled"; 1587 }; 1588 1589 uart8: serial@febb0000 { 1590 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1591 reg = <0x0 0xfebb0000 0x0 0x100>; 1592 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 1593 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1594 clock-names = "baudclk", "apb_pclk"; 1595 dmas = <&dmac2 9>, <&dmac2 10>; 1596 dma-names = "tx", "rx"; 1597 pinctrl-0 = <&uart8m1_xfer>; 1598 pinctrl-names = "default"; 1599 reg-io-width = <4>; 1600 reg-shift = <2>; 1601 status = "disabled"; 1602 }; 1603 1604 uart9: serial@febc0000 { 1605 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1606 reg = <0x0 0xfebc0000 0x0 0x100>; 1607 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 1608 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1609 clock-names = "baudclk", "apb_pclk"; 1610 dmas = <&dmac2 11>, <&dmac2 12>; 1611 dma-names = "tx", "rx"; 1612 pinctrl-0 = <&uart9m1_xfer>; 1613 pinctrl-names = "default"; 1614 reg-io-width = <4>; 1615 reg-shift = <2>; 1616 status = "disabled"; 1617 }; 1618 1619 pwm4: pwm@febd0000 { 1620 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1621 reg = <0x0 0xfebd0000 0x0 0x10>; 1622 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1623 clock-names = "pwm", "pclk"; 1624 pinctrl-0 = <&pwm4m0_pins>; 1625 pinctrl-names = "default"; 1626 #pwm-cells = <3>; 1627 status = "disabled"; 1628 }; 1629 1630 pwm5: pwm@febd0010 { 1631 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1632 reg = <0x0 0xfebd0010 0x0 0x10>; 1633 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1634 clock-names = "pwm", "pclk"; 1635 pinctrl-0 = <&pwm5m0_pins>; 1636 pinctrl-names = "default"; 1637 #pwm-cells = <3>; 1638 status = "disabled"; 1639 }; 1640 1641 pwm6: pwm@febd0020 { 1642 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1643 reg = <0x0 0xfebd0020 0x0 0x10>; 1644 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1645 clock-names = "pwm", "pclk"; 1646 pinctrl-0 = <&pwm6m0_pins>; 1647 pinctrl-names = "default"; 1648 #pwm-cells = <3>; 1649 status = "disabled"; 1650 }; 1651 1652 pwm7: pwm@febd0030 { 1653 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1654 reg = <0x0 0xfebd0030 0x0 0x10>; 1655 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1656 clock-names = "pwm", "pclk"; 1657 pinctrl-0 = <&pwm7m0_pins>; 1658 pinctrl-names = "default"; 1659 #pwm-cells = <3>; 1660 status = "disabled"; 1661 }; 1662 1663 pwm8: pwm@febe0000 { 1664 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1665 reg = <0x0 0xfebe0000 0x0 0x10>; 1666 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1667 clock-names = "pwm", "pclk"; 1668 pinctrl-0 = <&pwm8m0_pins>; 1669 pinctrl-names = "default"; 1670 #pwm-cells = <3>; 1671 status = "disabled"; 1672 }; 1673 1674 pwm9: pwm@febe0010 { 1675 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1676 reg = <0x0 0xfebe0010 0x0 0x10>; 1677 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1678 clock-names = "pwm", "pclk"; 1679 pinctrl-0 = <&pwm9m0_pins>; 1680 pinctrl-names = "default"; 1681 #pwm-cells = <3>; 1682 status = "disabled"; 1683 }; 1684 1685 pwm10: pwm@febe0020 { 1686 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1687 reg = <0x0 0xfebe0020 0x0 0x10>; 1688 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1689 clock-names = "pwm", "pclk"; 1690 pinctrl-0 = <&pwm10m0_pins>; 1691 pinctrl-names = "default"; 1692 #pwm-cells = <3>; 1693 status = "disabled"; 1694 }; 1695 1696 pwm11: pwm@febe0030 { 1697 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1698 reg = <0x0 0xfebe0030 0x0 0x10>; 1699 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1700 clock-names = "pwm", "pclk"; 1701 pinctrl-0 = <&pwm11m0_pins>; 1702 pinctrl-names = "default"; 1703 #pwm-cells = <3>; 1704 status = "disabled"; 1705 }; 1706 1707 pwm12: pwm@febf0000 { 1708 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1709 reg = <0x0 0xfebf0000 0x0 0x10>; 1710 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1711 clock-names = "pwm", "pclk"; 1712 pinctrl-0 = <&pwm12m0_pins>; 1713 pinctrl-names = "default"; 1714 #pwm-cells = <3>; 1715 status = "disabled"; 1716 }; 1717 1718 pwm13: pwm@febf0010 { 1719 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1720 reg = <0x0 0xfebf0010 0x0 0x10>; 1721 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1722 clock-names = "pwm", "pclk"; 1723 pinctrl-0 = <&pwm13m0_pins>; 1724 pinctrl-names = "default"; 1725 #pwm-cells = <3>; 1726 status = "disabled"; 1727 }; 1728 1729 pwm14: pwm@febf0020 { 1730 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1731 reg = <0x0 0xfebf0020 0x0 0x10>; 1732 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1733 clock-names = "pwm", "pclk"; 1734 pinctrl-0 = <&pwm14m0_pins>; 1735 pinctrl-names = "default"; 1736 #pwm-cells = <3>; 1737 status = "disabled"; 1738 }; 1739 1740 pwm15: pwm@febf0030 { 1741 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1742 reg = <0x0 0xfebf0030 0x0 0x10>; 1743 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1744 clock-names = "pwm", "pclk"; 1745 pinctrl-0 = <&pwm15m0_pins>; 1746 pinctrl-names = "default"; 1747 #pwm-cells = <3>; 1748 status = "disabled"; 1749 }; 1750 1751 tsadc: tsadc@fec00000 { 1752 compatible = "rockchip,rk3588-tsadc"; 1753 reg = <0x0 0xfec00000 0x0 0x400>; 1754 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 1755 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1756 clock-names = "tsadc", "apb_pclk"; 1757 assigned-clocks = <&cru CLK_TSADC>; 1758 assigned-clock-rates = <2000000>; 1759 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 1760 reset-names = "tsadc-apb", "tsadc"; 1761 rockchip,hw-tshut-temp = <120000>; 1762 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1763 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1764 pinctrl-0 = <&tsadc_gpio_func>; 1765 pinctrl-1 = <&tsadc_shut>; 1766 pinctrl-names = "gpio", "otpout"; 1767 #thermal-sensor-cells = <1>; 1768 status = "disabled"; 1769 }; 1770 1771 i2c6: i2c@fec80000 { 1772 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1773 reg = <0x0 0xfec80000 0x0 0x1000>; 1774 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1775 clock-names = "i2c", "pclk"; 1776 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 1777 pinctrl-0 = <&i2c6m0_xfer>; 1778 pinctrl-names = "default"; 1779 #address-cells = <1>; 1780 #size-cells = <0>; 1781 status = "disabled"; 1782 }; 1783 1784 i2c7: i2c@fec90000 { 1785 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1786 reg = <0x0 0xfec90000 0x0 0x1000>; 1787 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1788 clock-names = "i2c", "pclk"; 1789 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1790 pinctrl-0 = <&i2c7m0_xfer>; 1791 pinctrl-names = "default"; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 status = "disabled"; 1795 }; 1796 1797 i2c8: i2c@feca0000 { 1798 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1799 reg = <0x0 0xfeca0000 0x0 0x1000>; 1800 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 1801 clock-names = "i2c", "pclk"; 1802 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 1803 pinctrl-0 = <&i2c8m0_xfer>; 1804 pinctrl-names = "default"; 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 status = "disabled"; 1808 }; 1809 1810 spi4: spi@fecb0000 { 1811 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 1812 reg = <0x0 0xfecb0000 0x0 0x1000>; 1813 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 1814 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 1815 clock-names = "spiclk", "apb_pclk"; 1816 dmas = <&dmac2 13>, <&dmac2 14>; 1817 dma-names = "tx", "rx"; 1818 num-cs = <2>; 1819 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 1820 pinctrl-names = "default"; 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 status = "disabled"; 1824 }; 1825 1826 dmac2: dma-controller@fed10000 { 1827 compatible = "arm,pl330", "arm,primecell"; 1828 reg = <0x0 0xfed10000 0x0 0x4000>; 1829 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 1830 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 1831 arm,pl330-periph-burst; 1832 clocks = <&cru ACLK_DMAC2>; 1833 clock-names = "apb_pclk"; 1834 #dma-cells = <1>; 1835 }; 1836 1837 system_sram2: sram@ff001000 { 1838 compatible = "mmio-sram"; 1839 reg = <0x0 0xff001000 0x0 0xef000>; 1840 ranges = <0x0 0x0 0xff001000 0xef000>; 1841 #address-cells = <1>; 1842 #size-cells = <1>; 1843 }; 1844 1845 pinctrl: pinctrl { 1846 compatible = "rockchip,rk3588-pinctrl"; 1847 ranges; 1848 rockchip,grf = <&ioc>; 1849 #address-cells = <2>; 1850 #size-cells = <2>; 1851 1852 gpio0: gpio@fd8a0000 { 1853 compatible = "rockchip,gpio-bank"; 1854 reg = <0x0 0xfd8a0000 0x0 0x100>; 1855 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1856 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1857 gpio-controller; 1858 gpio-ranges = <&pinctrl 0 0 32>; 1859 interrupt-controller; 1860 #gpio-cells = <2>; 1861 #interrupt-cells = <2>; 1862 }; 1863 1864 gpio1: gpio@fec20000 { 1865 compatible = "rockchip,gpio-bank"; 1866 reg = <0x0 0xfec20000 0x0 0x100>; 1867 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 1868 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1869 gpio-controller; 1870 gpio-ranges = <&pinctrl 0 32 32>; 1871 interrupt-controller; 1872 #gpio-cells = <2>; 1873 #interrupt-cells = <2>; 1874 }; 1875 1876 gpio2: gpio@fec30000 { 1877 compatible = "rockchip,gpio-bank"; 1878 reg = <0x0 0xfec30000 0x0 0x100>; 1879 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 1880 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1881 gpio-controller; 1882 gpio-ranges = <&pinctrl 0 64 32>; 1883 interrupt-controller; 1884 #gpio-cells = <2>; 1885 #interrupt-cells = <2>; 1886 }; 1887 1888 gpio3: gpio@fec40000 { 1889 compatible = "rockchip,gpio-bank"; 1890 reg = <0x0 0xfec40000 0x0 0x100>; 1891 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 1892 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1893 gpio-controller; 1894 gpio-ranges = <&pinctrl 0 96 32>; 1895 interrupt-controller; 1896 #gpio-cells = <2>; 1897 #interrupt-cells = <2>; 1898 }; 1899 1900 gpio4: gpio@fec50000 { 1901 compatible = "rockchip,gpio-bank"; 1902 reg = <0x0 0xfec50000 0x0 0x100>; 1903 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 1904 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1905 gpio-controller; 1906 gpio-ranges = <&pinctrl 0 128 32>; 1907 interrupt-controller; 1908 #gpio-cells = <2>; 1909 #interrupt-cells = <2>; 1910 }; 1911 }; 1912}; 1913 1914#include "rk3588s-pinctrl.dtsi" 1915