1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 27 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 28 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 29 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x0 0x00 0x00100000 0x20000>; 51 52 phy_gmii_sel: phy@4044 { 53 compatible = "ti,am654-phy-gmii-sel"; 54 reg = <0x4044 0x8>; 55 #phy-cells = <1>; 56 }; 57 58 epwm_tbclk: clock@4130 { 59 compatible = "ti,am62-epwm-tbclk", "syscon"; 60 reg = <0x4130 0x4>; 61 #clock-cells = <1>; 62 }; 63 }; 64 65 dmss: bus@48000000 { 66 compatible = "simple-mfd"; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 dma-ranges; 70 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 71 72 ti,sci-dev-id = <25>; 73 74 secure_proxy_main: mailbox@4d000000 { 75 compatible = "ti,am654-secure-proxy"; 76 #mbox-cells = <1>; 77 reg-names = "target_data", "rt", "scfg"; 78 reg = <0x00 0x4d000000 0x00 0x80000>, 79 <0x00 0x4a600000 0x00 0x80000>, 80 <0x00 0x4a400000 0x00 0x80000>; 81 interrupt-names = "rx_012"; 82 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 83 }; 84 85 inta_main_dmss: interrupt-controller@48000000 { 86 compatible = "ti,sci-inta"; 87 reg = <0x00 0x48000000 0x00 0x100000>; 88 #interrupt-cells = <0>; 89 interrupt-controller; 90 interrupt-parent = <&gic500>; 91 msi-controller; 92 ti,sci = <&dmsc>; 93 ti,sci-dev-id = <28>; 94 ti,interrupt-ranges = <4 68 36>; 95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 96 }; 97 98 main_bcdma: dma-controller@485c0100 { 99 compatible = "ti,am64-dmss-bcdma"; 100 reg = <0x00 0x485c0100 0x00 0x100>, 101 <0x00 0x4c000000 0x00 0x20000>, 102 <0x00 0x4a820000 0x00 0x20000>, 103 <0x00 0x4aa40000 0x00 0x20000>, 104 <0x00 0x4bc00000 0x00 0x100000>; 105 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 106 msi-parent = <&inta_main_dmss>; 107 #dma-cells = <3>; 108 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <26>; 111 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 112 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 113 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 114 }; 115 116 main_pktdma: dma-controller@485c0000 { 117 compatible = "ti,am64-dmss-pktdma"; 118 reg = <0x00 0x485c0000 0x00 0x100>, 119 <0x00 0x4a800000 0x00 0x20000>, 120 <0x00 0x4aa00000 0x00 0x40000>, 121 <0x00 0x4b800000 0x00 0x400000>; 122 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 123 msi-parent = <&inta_main_dmss>; 124 #dma-cells = <2>; 125 126 ti,sci = <&dmsc>; 127 ti,sci-dev-id = <30>; 128 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 129 <0x24>, /* CPSW_TX_CHAN */ 130 <0x25>, /* SAUL_TX_0_CHAN */ 131 <0x26>; /* SAUL_TX_1_CHAN */ 132 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 133 <0x11>, /* RING_CPSW_TX_CHAN */ 134 <0x12>, /* RING_SAUL_TX_0_CHAN */ 135 <0x13>; /* RING_SAUL_TX_1_CHAN */ 136 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 137 <0x2b>, /* CPSW_RX_CHAN */ 138 <0x2d>, /* SAUL_RX_0_CHAN */ 139 <0x2f>, /* SAUL_RX_1_CHAN */ 140 <0x31>, /* SAUL_RX_2_CHAN */ 141 <0x33>; /* SAUL_RX_3_CHAN */ 142 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 143 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 144 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 145 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 146 }; 147 }; 148 149 dmsc: system-controller@44043000 { 150 compatible = "ti,k2g-sci"; 151 ti,host-id = <12>; 152 mbox-names = "rx", "tx"; 153 mboxes = <&secure_proxy_main 12>, 154 <&secure_proxy_main 13>; 155 reg-names = "debug_messages"; 156 reg = <0x00 0x44043000 0x00 0xfe0>; 157 158 k3_pds: power-controller { 159 compatible = "ti,sci-pm-domain"; 160 #power-domain-cells = <2>; 161 }; 162 163 k3_clks: clock-controller { 164 compatible = "ti,k2g-sci-clk"; 165 #clock-cells = <2>; 166 }; 167 168 k3_reset: reset-controller { 169 compatible = "ti,sci-reset"; 170 #reset-cells = <2>; 171 }; 172 }; 173 174 crypto: crypto@40900000 { 175 compatible = "ti,am62-sa3ul"; 176 reg = <0x00 0x40900000 0x00 0x1200>; 177 power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 181 182 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 183 <&main_pktdma 0x7507 0>; 184 dma-names = "tx", "rx1", "rx2"; 185 }; 186 187 main_pmx0: pinctrl@f4000 { 188 compatible = "pinctrl-single"; 189 reg = <0x00 0xf4000 0x00 0x2ac>; 190 #pinctrl-cells = <1>; 191 pinctrl-single,register-width = <32>; 192 pinctrl-single,function-mask = <0xffffffff>; 193 }; 194 195 main_timer0: timer@2400000 { 196 compatible = "ti,am654-timer"; 197 reg = <0x00 0x2400000 0x00 0x400>; 198 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&k3_clks 36 2>; 200 clock-names = "fck"; 201 assigned-clocks = <&k3_clks 36 2>; 202 assigned-clock-parents = <&k3_clks 36 3>; 203 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 204 ti,timer-pwm; 205 }; 206 207 main_timer1: timer@2410000 { 208 compatible = "ti,am654-timer"; 209 reg = <0x00 0x2410000 0x00 0x400>; 210 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&k3_clks 37 2>; 212 clock-names = "fck"; 213 assigned-clocks = <&k3_clks 37 2>; 214 assigned-clock-parents = <&k3_clks 37 3>; 215 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 216 ti,timer-pwm; 217 }; 218 219 main_timer2: timer@2420000 { 220 compatible = "ti,am654-timer"; 221 reg = <0x00 0x2420000 0x00 0x400>; 222 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&k3_clks 38 2>; 224 clock-names = "fck"; 225 assigned-clocks = <&k3_clks 38 2>; 226 assigned-clock-parents = <&k3_clks 38 3>; 227 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 228 ti,timer-pwm; 229 }; 230 231 main_timer3: timer@2430000 { 232 compatible = "ti,am654-timer"; 233 reg = <0x00 0x2430000 0x00 0x400>; 234 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&k3_clks 39 2>; 236 clock-names = "fck"; 237 assigned-clocks = <&k3_clks 39 2>; 238 assigned-clock-parents = <&k3_clks 39 3>; 239 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 240 ti,timer-pwm; 241 }; 242 243 main_timer4: timer@2440000 { 244 compatible = "ti,am654-timer"; 245 reg = <0x00 0x2440000 0x00 0x400>; 246 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&k3_clks 40 2>; 248 clock-names = "fck"; 249 assigned-clocks = <&k3_clks 40 2>; 250 assigned-clock-parents = <&k3_clks 40 3>; 251 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 252 ti,timer-pwm; 253 }; 254 255 main_timer5: timer@2450000 { 256 compatible = "ti,am654-timer"; 257 reg = <0x00 0x2450000 0x00 0x400>; 258 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&k3_clks 41 2>; 260 clock-names = "fck"; 261 assigned-clocks = <&k3_clks 41 2>; 262 assigned-clock-parents = <&k3_clks 41 3>; 263 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 264 ti,timer-pwm; 265 }; 266 267 main_timer6: timer@2460000 { 268 compatible = "ti,am654-timer"; 269 reg = <0x00 0x2460000 0x00 0x400>; 270 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&k3_clks 42 2>; 272 clock-names = "fck"; 273 assigned-clocks = <&k3_clks 42 2>; 274 assigned-clock-parents = <&k3_clks 42 3>; 275 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 276 ti,timer-pwm; 277 }; 278 279 main_timer7: timer@2470000 { 280 compatible = "ti,am654-timer"; 281 reg = <0x00 0x2470000 0x00 0x400>; 282 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&k3_clks 43 2>; 284 clock-names = "fck"; 285 assigned-clocks = <&k3_clks 43 2>; 286 assigned-clock-parents = <&k3_clks 43 3>; 287 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 288 ti,timer-pwm; 289 }; 290 291 main_uart0: serial@2800000 { 292 compatible = "ti,am64-uart", "ti,am654-uart"; 293 reg = <0x00 0x02800000 0x00 0x100>; 294 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 295 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 296 clocks = <&k3_clks 146 0>; 297 clock-names = "fclk"; 298 status = "disabled"; 299 }; 300 301 main_uart1: serial@2810000 { 302 compatible = "ti,am64-uart", "ti,am654-uart"; 303 reg = <0x00 0x02810000 0x00 0x100>; 304 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 305 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 306 clocks = <&k3_clks 152 0>; 307 clock-names = "fclk"; 308 status = "disabled"; 309 }; 310 311 main_uart2: serial@2820000 { 312 compatible = "ti,am64-uart", "ti,am654-uart"; 313 reg = <0x00 0x02820000 0x00 0x100>; 314 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 315 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 316 clocks = <&k3_clks 153 0>; 317 clock-names = "fclk"; 318 status = "disabled"; 319 }; 320 321 main_uart3: serial@2830000 { 322 compatible = "ti,am64-uart", "ti,am654-uart"; 323 reg = <0x00 0x02830000 0x00 0x100>; 324 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 325 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 326 clocks = <&k3_clks 154 0>; 327 clock-names = "fclk"; 328 status = "disabled"; 329 }; 330 331 main_uart4: serial@2840000 { 332 compatible = "ti,am64-uart", "ti,am654-uart"; 333 reg = <0x00 0x02840000 0x00 0x100>; 334 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 335 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 336 clocks = <&k3_clks 155 0>; 337 clock-names = "fclk"; 338 status = "disabled"; 339 }; 340 341 main_uart5: serial@2850000 { 342 compatible = "ti,am64-uart", "ti,am654-uart"; 343 reg = <0x00 0x02850000 0x00 0x100>; 344 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 345 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 346 clocks = <&k3_clks 156 0>; 347 clock-names = "fclk"; 348 status = "disabled"; 349 }; 350 351 main_uart6: serial@2860000 { 352 compatible = "ti,am64-uart", "ti,am654-uart"; 353 reg = <0x00 0x02860000 0x00 0x100>; 354 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 355 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 158 0>; 357 clock-names = "fclk"; 358 status = "disabled"; 359 }; 360 361 main_i2c0: i2c@20000000 { 362 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 363 reg = <0x00 0x20000000 0x00 0x100>; 364 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 368 clocks = <&k3_clks 102 2>; 369 clock-names = "fck"; 370 status = "disabled"; 371 }; 372 373 main_i2c1: i2c@20010000 { 374 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 375 reg = <0x00 0x20010000 0x00 0x100>; 376 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 380 clocks = <&k3_clks 103 2>; 381 clock-names = "fck"; 382 status = "disabled"; 383 }; 384 385 main_i2c2: i2c@20020000 { 386 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 387 reg = <0x00 0x20020000 0x00 0x100>; 388 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 392 clocks = <&k3_clks 104 2>; 393 clock-names = "fck"; 394 status = "disabled"; 395 }; 396 397 main_i2c3: i2c@20030000 { 398 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 399 reg = <0x00 0x20030000 0x00 0x100>; 400 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 404 clocks = <&k3_clks 105 2>; 405 clock-names = "fck"; 406 status = "disabled"; 407 }; 408 409 main_spi0: spi@20100000 { 410 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 411 reg = <0x00 0x20100000 0x00 0x400>; 412 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 141 0>; 417 status = "disabled"; 418 }; 419 420 main_spi1: spi@20110000 { 421 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 422 reg = <0x00 0x20110000 0x00 0x400>; 423 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 427 clocks = <&k3_clks 142 0>; 428 status = "disabled"; 429 }; 430 431 main_spi2: spi@20120000 { 432 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 433 reg = <0x00 0x20120000 0x00 0x400>; 434 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 438 clocks = <&k3_clks 143 0>; 439 status = "disabled"; 440 }; 441 442 main_gpio_intr: interrupt-controller@a00000 { 443 compatible = "ti,sci-intr"; 444 reg = <0x00 0x00a00000 0x00 0x800>; 445 ti,intr-trigger-type = <1>; 446 interrupt-controller; 447 interrupt-parent = <&gic500>; 448 #interrupt-cells = <1>; 449 ti,sci = <&dmsc>; 450 ti,sci-dev-id = <3>; 451 ti,interrupt-ranges = <0 32 16>; 452 }; 453 454 main_gpio0: gpio@600000 { 455 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 456 reg = <0x0 0x00600000 0x0 0x100>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 interrupt-parent = <&main_gpio_intr>; 460 interrupts = <190>, <191>, <192>, 461 <193>, <194>, <195>; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 ti,ngpio = <92>; 465 ti,davinci-gpio-unbanked = <0>; 466 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 467 clocks = <&k3_clks 77 0>; 468 clock-names = "gpio"; 469 }; 470 471 main_gpio1: gpio@601000 { 472 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 473 reg = <0x0 0x00601000 0x0 0x100>; 474 gpio-controller; 475 #gpio-cells = <2>; 476 interrupt-parent = <&main_gpio_intr>; 477 interrupts = <180>, <181>, <182>, 478 <183>, <184>, <185>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 ti,ngpio = <52>; 482 ti,davinci-gpio-unbanked = <0>; 483 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 484 clocks = <&k3_clks 78 0>; 485 clock-names = "gpio"; 486 }; 487 488 sdhci0: mmc@fa10000 { 489 compatible = "ti,am62-sdhci"; 490 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 491 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 492 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 493 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 494 clock-names = "clk_ahb", "clk_xin"; 495 assigned-clocks = <&k3_clks 57 6>; 496 assigned-clock-parents = <&k3_clks 57 8>; 497 mmc-ddr-1_8v; 498 mmc-hs200-1_8v; 499 ti,trm-icp = <0x2>; 500 bus-width = <8>; 501 ti,clkbuf-sel = <0x7>; 502 ti,otap-del-sel-legacy = <0x0>; 503 ti,otap-del-sel-mmc-hs = <0x0>; 504 ti,otap-del-sel-ddr52 = <0x5>; 505 ti,otap-del-sel-hs200 = <0x5>; 506 ti,itap-del-sel-legacy = <0xa>; 507 ti,itap-del-sel-mmc-hs = <0x1>; 508 status = "disabled"; 509 }; 510 511 sdhci1: mmc@fa00000 { 512 compatible = "ti,am62-sdhci"; 513 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 514 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 515 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 516 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 517 clock-names = "clk_ahb", "clk_xin"; 518 ti,trm-icp = <0x2>; 519 ti,otap-del-sel-legacy = <0x8>; 520 ti,otap-del-sel-sd-hs = <0x0>; 521 ti,otap-del-sel-sdr12 = <0x0>; 522 ti,otap-del-sel-sdr25 = <0x0>; 523 ti,otap-del-sel-sdr50 = <0x8>; 524 ti,otap-del-sel-sdr104 = <0x7>; 525 ti,otap-del-sel-ddr50 = <0x4>; 526 ti,itap-del-sel-legacy = <0xa>; 527 ti,itap-del-sel-sd-hs = <0x1>; 528 ti,itap-del-sel-sdr12 = <0xa>; 529 ti,itap-del-sel-sdr25 = <0x1>; 530 ti,clkbuf-sel = <0x7>; 531 bus-width = <4>; 532 status = "disabled"; 533 }; 534 535 sdhci2: mmc@fa20000 { 536 compatible = "ti,am62-sdhci"; 537 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 538 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 539 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 541 clock-names = "clk_ahb", "clk_xin"; 542 ti,trm-icp = <0x2>; 543 ti,otap-del-sel-legacy = <0x8>; 544 ti,otap-del-sel-sd-hs = <0x0>; 545 ti,otap-del-sel-sdr12 = <0x0>; 546 ti,otap-del-sel-sdr25 = <0x0>; 547 ti,otap-del-sel-sdr50 = <0x8>; 548 ti,otap-del-sel-sdr104 = <0x7>; 549 ti,otap-del-sel-ddr50 = <0x8>; 550 ti,itap-del-sel-legacy = <0xa>; 551 ti,itap-del-sel-sd-hs = <0xa>; 552 ti,itap-del-sel-sdr12 = <0xa>; 553 ti,itap-del-sel-sdr25 = <0x1>; 554 ti,clkbuf-sel = <0x7>; 555 status = "disabled"; 556 }; 557 558 usbss0: dwc3-usb@f900000 { 559 compatible = "ti,am62-usb"; 560 reg = <0x00 0x0f900000 0x00 0x800>; 561 clocks = <&k3_clks 161 3>; 562 clock-names = "ref"; 563 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; 564 #address-cells = <2>; 565 #size-cells = <2>; 566 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 567 ranges; 568 status = "disabled"; 569 570 usb0: usb@31000000 { 571 compatible = "snps,dwc3"; 572 reg =<0x00 0x31000000 0x00 0x50000>; 573 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 574 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 575 interrupt-names = "host", "peripheral"; 576 maximum-speed = "high-speed"; 577 dr_mode = "otg"; 578 }; 579 }; 580 581 usbss1: dwc3-usb@f910000 { 582 compatible = "ti,am62-usb"; 583 reg = <0x00 0x0f910000 0x00 0x800>; 584 clocks = <&k3_clks 162 3>; 585 clock-names = "ref"; 586 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; 587 #address-cells = <2>; 588 #size-cells = <2>; 589 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 590 ranges; 591 status = "disabled"; 592 593 usb1: usb@31100000 { 594 compatible = "snps,dwc3"; 595 reg =<0x00 0x31100000 0x00 0x50000>; 596 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 597 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 598 interrupt-names = "host", "peripheral"; 599 maximum-speed = "high-speed"; 600 dr_mode = "otg"; 601 }; 602 }; 603 604 fss: bus@fc00000 { 605 compatible = "simple-bus"; 606 reg = <0x00 0x0fc00000 0x00 0x70000>; 607 #address-cells = <2>; 608 #size-cells = <2>; 609 ranges; 610 611 ospi0: spi@fc40000 { 612 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 613 reg = <0x00 0x0fc40000 0x00 0x100>, 614 <0x05 0x00000000 0x01 0x00000000>; 615 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 616 cdns,fifo-depth = <256>; 617 cdns,fifo-width = <4>; 618 cdns,trigger-address = <0x0>; 619 clocks = <&k3_clks 75 7>; 620 assigned-clocks = <&k3_clks 75 7>; 621 assigned-clock-parents = <&k3_clks 75 8>; 622 assigned-clock-rates = <166666666>; 623 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 status = "disabled"; 627 }; 628 }; 629 630 cpsw3g: ethernet@8000000 { 631 compatible = "ti,am642-cpsw-nuss"; 632 #address-cells = <2>; 633 #size-cells = <2>; 634 reg = <0x00 0x08000000 0x00 0x200000>; 635 reg-names = "cpsw_nuss"; 636 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 637 clocks = <&k3_clks 13 0>; 638 assigned-clocks = <&k3_clks 13 3>; 639 assigned-clock-parents = <&k3_clks 13 11>; 640 clock-names = "fck"; 641 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 642 643 dmas = <&main_pktdma 0xc600 15>, 644 <&main_pktdma 0xc601 15>, 645 <&main_pktdma 0xc602 15>, 646 <&main_pktdma 0xc603 15>, 647 <&main_pktdma 0xc604 15>, 648 <&main_pktdma 0xc605 15>, 649 <&main_pktdma 0xc606 15>, 650 <&main_pktdma 0xc607 15>, 651 <&main_pktdma 0x4600 15>; 652 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 653 "tx7", "rx"; 654 655 ethernet-ports { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 659 cpsw_port1: port@1 { 660 reg = <1>; 661 ti,mac-only; 662 label = "port1"; 663 phys = <&phy_gmii_sel 1>; 664 mac-address = [00 00 00 00 00 00]; 665 ti,syscon-efuse = <&wkup_conf 0x200>; 666 }; 667 668 cpsw_port2: port@2 { 669 reg = <2>; 670 ti,mac-only; 671 label = "port2"; 672 phys = <&phy_gmii_sel 2>; 673 mac-address = [00 00 00 00 00 00]; 674 }; 675 }; 676 677 cpsw3g_mdio: mdio@f00 { 678 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 679 reg = <0x00 0xf00 0x00 0x100>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 clocks = <&k3_clks 13 0>; 683 clock-names = "fck"; 684 bus_freq = <1000000>; 685 status = "disabled"; 686 }; 687 688 cpts@3d000 { 689 compatible = "ti,j721e-cpts"; 690 reg = <0x00 0x3d000 0x00 0x400>; 691 clocks = <&k3_clks 13 3>; 692 clock-names = "cpts"; 693 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 694 interrupt-names = "cpts"; 695 ti,cpts-ext-ts-inputs = <4>; 696 ti,cpts-periodic-outputs = <2>; 697 }; 698 }; 699 700 hwspinlock: spinlock@2a000000 { 701 compatible = "ti,am64-hwspinlock"; 702 reg = <0x00 0x2a000000 0x00 0x1000>; 703 #hwlock-cells = <1>; 704 }; 705 706 mailbox0_cluster0: mailbox@29000000 { 707 compatible = "ti,am64-mailbox"; 708 reg = <0x00 0x29000000 0x00 0x200>; 709 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 711 #mbox-cells = <1>; 712 ti,mbox-num-users = <4>; 713 ti,mbox-num-fifos = <16>; 714 }; 715 716 ecap0: pwm@23100000 { 717 compatible = "ti,am3352-ecap"; 718 #pwm-cells = <3>; 719 reg = <0x00 0x23100000 0x00 0x100>; 720 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 721 clocks = <&k3_clks 51 0>; 722 clock-names = "fck"; 723 status = "disabled"; 724 }; 725 726 ecap1: pwm@23110000 { 727 compatible = "ti,am3352-ecap"; 728 #pwm-cells = <3>; 729 reg = <0x00 0x23110000 0x00 0x100>; 730 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 731 clocks = <&k3_clks 52 0>; 732 clock-names = "fck"; 733 status = "disabled"; 734 }; 735 736 ecap2: pwm@23120000 { 737 compatible = "ti,am3352-ecap"; 738 #pwm-cells = <3>; 739 reg = <0x00 0x23120000 0x00 0x100>; 740 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 741 clocks = <&k3_clks 53 0>; 742 clock-names = "fck"; 743 status = "disabled"; 744 }; 745 746 main_mcan0: can@20701000 { 747 compatible = "bosch,m_can"; 748 reg = <0x00 0x20701000 0x00 0x200>, 749 <0x00 0x20708000 0x00 0x8000>; 750 reg-names = "m_can", "message_ram"; 751 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 752 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 753 clock-names = "hclk", "cclk"; 754 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 756 interrupt-names = "int0", "int1"; 757 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 758 status = "disabled"; 759 }; 760 761 main_rti0: watchdog@e000000 { 762 compatible = "ti,j7-rti-wdt"; 763 reg = <0x00 0x0e000000 0x00 0x100>; 764 clocks = <&k3_clks 125 0>; 765 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 766 assigned-clocks = <&k3_clks 125 0>; 767 assigned-clock-parents = <&k3_clks 125 2>; 768 }; 769 770 main_rti1: watchdog@e010000 { 771 compatible = "ti,j7-rti-wdt"; 772 reg = <0x00 0x0e010000 0x00 0x100>; 773 clocks = <&k3_clks 126 0>; 774 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 775 assigned-clocks = <&k3_clks 126 0>; 776 assigned-clock-parents = <&k3_clks 126 2>; 777 }; 778 779 main_rti2: watchdog@e020000 { 780 compatible = "ti,j7-rti-wdt"; 781 reg = <0x00 0x0e020000 0x00 0x100>; 782 clocks = <&k3_clks 127 0>; 783 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 784 assigned-clocks = <&k3_clks 127 0>; 785 assigned-clock-parents = <&k3_clks 127 2>; 786 }; 787 788 main_rti3: watchdog@e030000 { 789 compatible = "ti,j7-rti-wdt"; 790 reg = <0x00 0x0e030000 0x00 0x100>; 791 clocks = <&k3_clks 128 0>; 792 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 793 assigned-clocks = <&k3_clks 128 0>; 794 assigned-clock-parents = <&k3_clks 128 2>; 795 }; 796 797 main_rti15: watchdog@e0f0000 { 798 compatible = "ti,j7-rti-wdt"; 799 reg = <0x00 0x0e0f0000 0x00 0x100>; 800 clocks = <&k3_clks 130 0>; 801 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 802 assigned-clocks = <&k3_clks 130 0>; 803 assigned-clock-parents = <&k3_clks 130 2>; 804 }; 805 806 epwm0: pwm@23000000 { 807 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 808 #pwm-cells = <3>; 809 reg = <0x00 0x23000000 0x00 0x100>; 810 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 811 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 812 clock-names = "tbclk", "fck"; 813 status = "disabled"; 814 }; 815 816 epwm1: pwm@23010000 { 817 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 818 #pwm-cells = <3>; 819 reg = <0x00 0x23010000 0x00 0x100>; 820 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 821 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 822 clock-names = "tbclk", "fck"; 823 status = "disabled"; 824 }; 825 826 epwm2: pwm@23020000 { 827 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 828 #pwm-cells = <3>; 829 reg = <0x00 0x23020000 0x00 0x100>; 830 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 831 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 832 clock-names = "tbclk", "fck"; 833 status = "disabled"; 834 }; 835 836 mcasp0: audio-controller@2b00000 { 837 compatible = "ti,am33xx-mcasp-audio"; 838 reg = <0x00 0x02b00000 0x00 0x2000>, 839 <0x00 0x02b08000 0x00 0x400>; 840 reg-names = "mpu", "dat"; 841 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "tx", "rx"; 844 845 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 846 dma-names = "tx", "rx"; 847 848 clocks = <&k3_clks 190 0>; 849 clock-names = "fck"; 850 assigned-clocks = <&k3_clks 190 0>; 851 assigned-clock-parents = <&k3_clks 190 2>; 852 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 853 status = "disabled"; 854 }; 855 856 mcasp1: audio-controller@2b10000 { 857 compatible = "ti,am33xx-mcasp-audio"; 858 reg = <0x00 0x02b10000 0x00 0x2000>, 859 <0x00 0x02b18000 0x00 0x400>; 860 reg-names = "mpu", "dat"; 861 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "tx", "rx"; 864 865 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 866 dma-names = "tx", "rx"; 867 868 clocks = <&k3_clks 191 0>; 869 clock-names = "fck"; 870 assigned-clocks = <&k3_clks 191 0>; 871 assigned-clock-parents = <&k3_clks 191 2>; 872 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 873 status = "disabled"; 874 }; 875 876 mcasp2: audio-controller@2b20000 { 877 compatible = "ti,am33xx-mcasp-audio"; 878 reg = <0x00 0x02b20000 0x00 0x2000>, 879 <0x00 0x02b28000 0x00 0x400>; 880 reg-names = "mpu", "dat"; 881 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "tx", "rx"; 884 885 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 886 dma-names = "tx", "rx"; 887 888 clocks = <&k3_clks 192 0>; 889 clock-names = "fck"; 890 assigned-clocks = <&k3_clks 192 0>; 891 assigned-clock-parents = <&k3_clks 192 2>; 892 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 893 status = "disabled"; 894 }; 895}; 896