1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM625 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu {
9	mcu_pmx0: pinctrl@4084000 {
10		compatible = "pinctrl-single";
11		reg = <0x00 0x04084000 0x00 0x88>;
12		#pinctrl-cells = <1>;
13		pinctrl-single,register-width = <32>;
14		pinctrl-single,function-mask = <0xffffffff>;
15	};
16
17	mcu_uart0: serial@4a00000 {
18		compatible = "ti,am64-uart", "ti,am654-uart";
19		reg = <0x00 0x04a00000 0x00 0x100>;
20		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
21		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
22		clocks = <&k3_clks 149 0>;
23		clock-names = "fclk";
24	};
25
26	mcu_i2c0: i2c@4900000 {
27		compatible = "ti,am64-i2c", "ti,omap4-i2c";
28		reg = <0x00 0x04900000 0x00 0x100>;
29		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
30		#address-cells = <1>;
31		#size-cells = <0>;
32		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
33		clocks = <&k3_clks 106 2>;
34		clock-names = "fck";
35	};
36
37	mcu_spi0: spi@4b00000 {
38		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
39		reg = <0x00 0x04b00000 0x00 0x400>;
40		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
41		#address-cells = <1>;
42		#size-cells = <0>;
43		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
44		clocks = <&k3_clks 147 0>;
45	};
46
47	mcu_spi1: spi@4b10000 {
48		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
49		reg = <0x00 0x04b10000 0x00 0x400>;
50		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
51		#address-cells = <1>;
52		#size-cells = <0>;
53		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
54		clocks = <&k3_clks 148 0>;
55	};
56
57	mcu_gpio_intr: interrupt-controller@4210000 {
58		compatible = "ti,sci-intr";
59		reg = <0x00 0x04210000 0x00 0x200>;
60		ti,intr-trigger-type = <1>;
61		interrupt-controller;
62		interrupt-parent = <&gic500>;
63		#interrupt-cells = <1>;
64		ti,sci = <&dmsc>;
65		ti,sci-dev-id = <5>;
66		ti,interrupt-ranges = <0 104 4>;
67	};
68
69	mcu_gpio0: gpio@4201000 {
70		compatible = "ti,am64-gpio", "ti,keystone-gpio";
71		reg = <0x00 0x4201000 0x00 0x100>;
72		gpio-controller;
73		#gpio-cells = <2>;
74		interrupt-parent = <&mcu_gpio_intr>;
75		interrupts = <30>, <31>;
76		interrupt-controller;
77		#interrupt-cells = <2>;
78		ti,ngpio = <24>;
79		ti,davinci-gpio-unbanked = <0>;
80		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
81		clocks = <&k3_clks 79 0>;
82		clock-names = "gpio";
83	};
84};
85