1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy.h>
9#include <dt-bindings/mux/ti-serdes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/net/ti-dp83867.h>
13#include "k3-am642.dtsi"
14
15/ {
16	compatible = "ti,am642-evm", "ti,am642";
17	model = "Texas Instruments AM642 EVM";
18
19	chosen {
20		stdout-path = "serial2:115200n8";
21		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
22	};
23
24	memory@80000000 {
25		device_type = "memory";
26		/* 2G RAM */
27		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
28
29	};
30
31	reserved-memory {
32		#address-cells = <2>;
33		#size-cells = <2>;
34		ranges;
35
36		secure_ddr: optee@9e800000 {
37			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
38			alignment = <0x1000>;
39			no-map;
40		};
41
42		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
43			compatible = "shared-dma-pool";
44			reg = <0x00 0xa0000000 0x00 0x100000>;
45			no-map;
46		};
47
48		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
49			compatible = "shared-dma-pool";
50			reg = <0x00 0xa0100000 0x00 0xf00000>;
51			no-map;
52		};
53
54		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
55			compatible = "shared-dma-pool";
56			reg = <0x00 0xa1000000 0x00 0x100000>;
57			no-map;
58		};
59
60		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
61			compatible = "shared-dma-pool";
62			reg = <0x00 0xa1100000 0x00 0xf00000>;
63			no-map;
64		};
65
66		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
67			compatible = "shared-dma-pool";
68			reg = <0x00 0xa2000000 0x00 0x100000>;
69			no-map;
70		};
71
72		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
73			compatible = "shared-dma-pool";
74			reg = <0x00 0xa2100000 0x00 0xf00000>;
75			no-map;
76		};
77
78		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
79			compatible = "shared-dma-pool";
80			reg = <0x00 0xa3000000 0x00 0x100000>;
81			no-map;
82		};
83
84		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
85			compatible = "shared-dma-pool";
86			reg = <0x00 0xa3100000 0x00 0xf00000>;
87			no-map;
88		};
89
90		rtos_ipc_memory_region: ipc-memories@a5000000 {
91			reg = <0x00 0xa5000000 0x00 0x00800000>;
92			alignment = <0x1000>;
93			no-map;
94		};
95	};
96
97	evm_12v0: fixedregulator-evm12v0 {
98		/* main DC jack */
99		compatible = "regulator-fixed";
100		regulator-name = "evm_12v0";
101		regulator-min-microvolt = <12000000>;
102		regulator-max-microvolt = <12000000>;
103		regulator-always-on;
104		regulator-boot-on;
105	};
106
107	vsys_5v0: fixedregulator-vsys5v0 {
108		/* output of LM5140 */
109		compatible = "regulator-fixed";
110		regulator-name = "vsys_5v0";
111		regulator-min-microvolt = <5000000>;
112		regulator-max-microvolt = <5000000>;
113		vin-supply = <&evm_12v0>;
114		regulator-always-on;
115		regulator-boot-on;
116	};
117
118	vsys_3v3: fixedregulator-vsys3v3 {
119		/* output of LM5140 */
120		compatible = "regulator-fixed";
121		regulator-name = "vsys_3v3";
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124		vin-supply = <&evm_12v0>;
125		regulator-always-on;
126		regulator-boot-on;
127	};
128
129	vdd_mmc1: fixed-regulator-sd {
130		/* TPS2051BD */
131		compatible = "regulator-fixed";
132		regulator-name = "vdd_mmc1";
133		regulator-min-microvolt = <3300000>;
134		regulator-max-microvolt = <3300000>;
135		regulator-boot-on;
136		enable-active-high;
137		vin-supply = <&vsys_3v3>;
138		gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
139	};
140
141	vddb: fixedregulator-vddb {
142		compatible = "regulator-fixed";
143		regulator-name = "vddb_3v3_display";
144		regulator-min-microvolt = <3300000>;
145		regulator-max-microvolt = <3300000>;
146		vin-supply = <&vsys_3v3>;
147		regulator-always-on;
148		regulator-boot-on;
149	};
150
151	leds {
152		compatible = "gpio-leds";
153
154		led-0 {
155			label = "am64-evm:red:heartbeat";
156			gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
157			linux,default-trigger = "heartbeat";
158			function = LED_FUNCTION_HEARTBEAT;
159			default-state = "off";
160		};
161	};
162
163	mdio_mux: mux-controller {
164		compatible = "gpio-mux";
165		#mux-control-cells = <0>;
166
167		mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
168	};
169
170	mdio-mux-1 {
171		compatible = "mdio-mux-multiplexer";
172		mux-controls = <&mdio_mux>;
173		mdio-parent-bus = <&cpsw3g_mdio>;
174		#address-cells = <1>;
175		#size-cells = <0>;
176
177		mdio@1 {
178			reg = <0x1>;
179			#address-cells = <1>;
180			#size-cells = <0>;
181
182			cpsw3g_phy3: ethernet-phy@3 {
183				reg = <3>;
184			};
185		};
186	};
187
188	transceiver1: can-phy0 {
189		compatible = "ti,tcan1042";
190		#phy-cells = <0>;
191		max-bitrate = <5000000>;
192		standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
193	};
194
195	transceiver2: can-phy1 {
196		compatible = "ti,tcan1042";
197		#phy-cells = <0>;
198		max-bitrate = <5000000>;
199		standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
200	};
201};
202
203&main_pmx0 {
204	main_mmc1_pins_default: main-mmc1-pins-default {
205		pinctrl-single,pins = <
206			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
207			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
208			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
209			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
210			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
211			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
212			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
213			AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
214			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
215		>;
216	};
217
218	main_uart0_pins_default: main-uart0-pins-default {
219		pinctrl-single,pins = <
220			AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
221			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
222			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
223			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
224		>;
225	};
226
227	main_spi0_pins_default: main-spi0-pins-default {
228		pinctrl-single,pins = <
229			AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
230			AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
231			AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
232			AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
233		>;
234	};
235
236	main_i2c1_pins_default: main-i2c1-pins-default {
237		pinctrl-single,pins = <
238			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
239			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
240		>;
241	};
242
243	mdio1_pins_default: mdio1-pins-default {
244		pinctrl-single,pins = <
245			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
246			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
247		>;
248	};
249
250	rgmii1_pins_default: rgmii1-pins-default {
251		pinctrl-single,pins = <
252			AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
253			AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
254			AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
255			AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
256			AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
257			AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
258			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
259			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
260			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
261			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
262			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
263			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
264		>;
265	};
266
267       rgmii2_pins_default: rgmii2-pins-default {
268		pinctrl-single,pins = <
269			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
270			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
271			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
272			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
273			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
274			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
275			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
276			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
277			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
278			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
279			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
280			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
281		>;
282	};
283
284	main_usb0_pins_default: main-usb0-pins-default {
285		pinctrl-single,pins = <
286			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
287		>;
288	};
289
290	ospi0_pins_default: ospi0-pins-default {
291		pinctrl-single,pins = <
292			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
293			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
294			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
295			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
296			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
297			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
298			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
299			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
300			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
301			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
302			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
303		>;
304	};
305
306	main_ecap0_pins_default: main-ecap0-pins-default {
307		pinctrl-single,pins = <
308			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
309		>;
310	};
311
312	main_mcan0_pins_default: main-mcan0-pins-default {
313		pinctrl-single,pins = <
314			AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
315			AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
316		>;
317	};
318
319	main_mcan1_pins_default: main-mcan1-pins-default {
320		pinctrl-single,pins = <
321			AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
322			AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
323		>;
324	};
325};
326
327&main_uart0 {
328	status = "okay";
329	pinctrl-names = "default";
330	pinctrl-0 = <&main_uart0_pins_default>;
331};
332
333/* main_uart1 is reserved for firmware usage */
334&main_uart1 {
335	status = "reserved";
336};
337
338&main_i2c1 {
339	status = "okay";
340	pinctrl-names = "default";
341	pinctrl-0 = <&main_i2c1_pins_default>;
342	clock-frequency = <400000>;
343
344	exp1: gpio@22 {
345		compatible = "ti,tca6424";
346		reg = <0x22>;
347		gpio-controller;
348		#gpio-cells = <2>;
349		gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
350				  "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
351				  "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
352				  "MMC1_SD_EN", "FSI_FET_SEL",
353				  "MCAN0_STB_3V3", "MCAN1_STB_3V3",
354				  "CPSW_FET_SEL", "CPSW_FET2_SEL",
355				  "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
356				  "GPIO_OLED_RESETn", "VPP_LDO_EN",
357				  "TEST_LED1", "TP92", "TP90", "TP88",
358				  "TP87", "TP86", "TP89", "TP91";
359	};
360
361	/* osd9616p0899-10 */
362	display@3c {
363		compatible = "solomon,ssd1306fb-i2c";
364		reg = <0x3c>;
365		reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
366		vbat-supply = <&vddb>;
367		solomon,height = <16>;
368		solomon,width = <96>;
369		solomon,com-seq;
370		solomon,com-invdir;
371		solomon,page-offset = <0>;
372		solomon,prechargep1 = <2>;
373		solomon,prechargep2 = <13>;
374	};
375};
376
377/* mcu_gpio0 is reserved for mcu firmware usage */
378&mcu_gpio0 {
379	status = "reserved";
380};
381
382&main_spi0 {
383	status = "okay";
384	pinctrl-names = "default";
385	pinctrl-0 = <&main_spi0_pins_default>;
386	ti,pindir-d0-out-d1-in;
387	eeprom@0 {
388		compatible = "microchip,93lc46b";
389		reg = <0>;
390		spi-max-frequency = <1000000>;
391		spi-cs-high;
392		data-size = <16>;
393	};
394};
395
396&sdhci0 {
397	/* emmc */
398	bus-width = <8>;
399	non-removable;
400	ti,driver-strength-ohm = <50>;
401	disable-wp;
402};
403
404&sdhci1 {
405	/* SD/MMC */
406	vmmc-supply = <&vdd_mmc1>;
407	pinctrl-names = "default";
408	bus-width = <4>;
409	pinctrl-0 = <&main_mmc1_pins_default>;
410	ti,driver-strength-ohm = <50>;
411	disable-wp;
412};
413
414&usbss0 {
415	ti,vbus-divider;
416	ti,usb2-only;
417};
418
419&usb0 {
420	dr_mode = "otg";
421	maximum-speed = "high-speed";
422	pinctrl-names = "default";
423	pinctrl-0 = <&main_usb0_pins_default>;
424};
425
426&cpsw3g {
427	pinctrl-names = "default";
428	pinctrl-0 = <&rgmii1_pins_default
429		     &rgmii2_pins_default>;
430};
431
432&cpsw_port1 {
433	phy-mode = "rgmii-rxid";
434	phy-handle = <&cpsw3g_phy0>;
435};
436
437&cpsw_port2 {
438	phy-mode = "rgmii-rxid";
439	phy-handle = <&cpsw3g_phy3>;
440};
441
442&cpsw3g_mdio {
443	status = "okay";
444	pinctrl-names = "default";
445	pinctrl-0 = <&mdio1_pins_default>;
446
447	cpsw3g_phy0: ethernet-phy@0 {
448		reg = <0>;
449		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
450		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
451	};
452};
453
454&tscadc0 {
455	/* ADC is reserved for R5 usage */
456	status = "reserved";
457};
458
459&ospi0 {
460	pinctrl-names = "default";
461	pinctrl-0 = <&ospi0_pins_default>;
462
463	flash@0 {
464		compatible = "jedec,spi-nor";
465		reg = <0x0>;
466		spi-tx-bus-width = <8>;
467		spi-rx-bus-width = <8>;
468		spi-max-frequency = <25000000>;
469		cdns,tshsl-ns = <60>;
470		cdns,tsd2d-ns = <60>;
471		cdns,tchsh-ns = <60>;
472		cdns,tslch-ns = <60>;
473		cdns,read-delay = <4>;
474	};
475};
476
477&mailbox0_cluster2 {
478	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
479		ti,mbox-rx = <0 0 2>;
480		ti,mbox-tx = <1 0 2>;
481	};
482
483	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
484		ti,mbox-rx = <2 0 2>;
485		ti,mbox-tx = <3 0 2>;
486	};
487};
488
489&mailbox0_cluster3 {
490	status = "disabled";
491};
492
493&mailbox0_cluster4 {
494	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
495		ti,mbox-rx = <0 0 2>;
496		ti,mbox-tx = <1 0 2>;
497	};
498
499	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
500		ti,mbox-rx = <2 0 2>;
501		ti,mbox-tx = <3 0 2>;
502	};
503};
504
505&mailbox0_cluster5 {
506	status = "disabled";
507};
508
509&mailbox0_cluster6 {
510	mbox_m4_0: mbox-m4-0 {
511		ti,mbox-rx = <0 0 2>;
512		ti,mbox-tx = <1 0 2>;
513	};
514};
515
516&mailbox0_cluster7 {
517	status = "disabled";
518};
519
520&main_r5fss0_core0 {
521	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
522	memory-region = <&main_r5fss0_core0_dma_memory_region>,
523			<&main_r5fss0_core0_memory_region>;
524};
525
526&main_r5fss0_core1 {
527	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
528	memory-region = <&main_r5fss0_core1_dma_memory_region>,
529			<&main_r5fss0_core1_memory_region>;
530};
531
532&main_r5fss1_core0 {
533	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
534	memory-region = <&main_r5fss1_core0_dma_memory_region>,
535			<&main_r5fss1_core0_memory_region>;
536};
537
538&main_r5fss1_core1 {
539	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
540	memory-region = <&main_r5fss1_core1_dma_memory_region>,
541			<&main_r5fss1_core1_memory_region>;
542};
543
544&serdes_ln_ctrl {
545	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
546};
547
548&serdes0 {
549	serdes0_pcie_link: phy@0 {
550		reg = <0>;
551		cdns,num-lanes = <1>;
552		#phy-cells = <0>;
553		cdns,phy-type = <PHY_TYPE_PCIE>;
554		resets = <&serdes_wiz0 1>;
555	};
556};
557
558&pcie0_rc {
559	status = "okay";
560	reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
561	phys = <&serdes0_pcie_link>;
562	phy-names = "pcie-phy";
563	num-lanes = <1>;
564};
565
566&pcie0_ep {
567	phys = <&serdes0_pcie_link>;
568	phy-names = "pcie-phy";
569	num-lanes = <1>;
570};
571
572&ecap0 {
573	status = "okay";
574	/* PWM is available on Pin 1 of header J12 */
575	pinctrl-names = "default";
576	pinctrl-0 = <&main_ecap0_pins_default>;
577};
578
579&main_mcan0 {
580	status = "okay";
581	pinctrl-names = "default";
582	pinctrl-0 = <&main_mcan0_pins_default>;
583	phys = <&transceiver1>;
584};
585
586&main_mcan1 {
587	status = "okay";
588	pinctrl-names = "default";
589	pinctrl-0 = <&main_mcan1_pins_default>;
590	phys = <&transceiver2>;
591};
592