1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/soc/ti,sci_pm_domain.h>
12
13#include "k3-pinctrl.h"
14
15/ {
16	model = "Texas Instruments K3 AM654 SoC";
17	compatible = "ti,am654";
18	interrupt-parent = <&gic500>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		serial0 = &wkup_uart0;
24		serial1 = &mcu_uart0;
25		serial2 = &main_uart0;
26		serial3 = &main_uart1;
27		serial4 = &main_uart2;
28		i2c0 = &wkup_i2c0;
29		i2c1 = &mcu_i2c0;
30		i2c2 = &main_i2c0;
31		i2c3 = &main_i2c1;
32		i2c4 = &main_i2c2;
33		i2c5 = &main_i2c3;
34		ethernet0 = &cpsw_port1;
35		mmc0 = &sdhci0;
36		mmc1 = &sdhci1;
37	};
38
39	chosen { };
40
41	firmware {
42		optee {
43			compatible = "linaro,optee-tz";
44			method = "smc";
45		};
46
47		psci: psci {
48			compatible = "arm,psci-1.0";
49			method = "smc";
50		};
51	};
52
53	a53_timer0: timer-cl0-cpu0 {
54		compatible = "arm,armv8-timer";
55		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
56			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
57			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
58			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
59	};
60
61	pmu: pmu {
62		compatible = "arm,cortex-a53-pmu";
63		/* Recommendation from GIC500 TRM Table A.3 */
64		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
65	};
66
67	cbass_main: bus@100000 {
68		compatible = "simple-bus";
69		#address-cells = <2>;
70		#size-cells = <2>;
71		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
72			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
73			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
74			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
75			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
76			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
77			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
78			 /* MCUSS Range */
79			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
80			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
81			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
82			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
83			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
84			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
85			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
86			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
87			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
88			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
89			 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
90			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
91			 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
92			 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
93			 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
94
95		cbass_mcu: bus@28380000 {
96			compatible = "simple-bus";
97			#address-cells = <2>;
98			#size-cells = <2>;
99			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
100				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
101				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
102				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
103				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
104				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
105				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
106				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
107				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
108				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
109				 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /*  FSS OSPI0 data region 1 */
110				 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
111				 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
112
113			cbass_wakeup: bus@42040000 {
114				compatible = "simple-bus";
115				#address-cells = <1>;
116				#size-cells = <1>;
117				/* WKUP  Basic peripherals */
118				ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
119			};
120		};
121	};
122};
123
124/* Now include the peripherals for each bus segments */
125#include "k3-am65-main.dtsi"
126#include "k3-am65-mcu.dtsi"
127#include "k3-am65-wakeup.dtsi"
128