xref: /freebsd/sys/contrib/device-tree/src/arm64/ti/k3-j7200-evm-quad-port-eth-exp.dtso (revision aa1a8ff2)

// SPDX-License-Identifier: GPL-2.0
/**
 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
 * J7200 board.
 *
 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>

#include "k3-pinctrl.h"
#include "k3-serdes.h"

&{/} {
	aliases {
		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
		ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
		ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
	};
};

&cpsw0 {
	status = "okay";
};

&cpsw0_port1 {
	status = "okay";
	phy-handle = <&cpsw5g_phy0>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 1>;
};

&cpsw0_port2 {
	status = "okay";
	phy-handle = <&cpsw5g_phy1>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 2>;
};

&cpsw0_port3 {
	status = "okay";
	phy-handle = <&cpsw5g_phy2>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 3>;
};

&cpsw0_port4 {
	status = "okay";
	phy-handle = <&cpsw5g_phy3>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 4>;
};

&cpsw5g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins_default>;
	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw5g_phy0: ethernet-phy@16 {
		reg = <16>;
	};
	cpsw5g_phy1: ethernet-phy@17 {
		reg = <17>;
	};
	cpsw5g_phy2: ethernet-phy@18 {
		reg = <18>;
	};
	cpsw5g_phy3: ethernet-phy@19 {
		reg = <19>;
	};
};

&exp2 {
	qsgmii-line-hog {
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "qsgmii-pwrdn-line";
	};
};

&main_pmx0 {
	mdio0_pins_default: mdio0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
			J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
		>;
	};
};