1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200.dtsi"
9
10/ {
11	memory@80000000 {
12		device_type = "memory";
13		/* 4G RAM */
14		reg = <0x00 0x80000000 0x00 0x80000000>,
15		      <0x08 0x80000000 0x00 0x80000000>;
16	};
17
18	reserved_memory: reserved-memory {
19		#address-cells = <2>;
20		#size-cells = <2>;
21		ranges;
22
23		secure_ddr: optee@9e800000 {
24			reg = <0x00 0x9e800000 0x00 0x01800000>;
25			alignment = <0x1000>;
26			no-map;
27		};
28
29		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
30			compatible = "shared-dma-pool";
31			reg = <0x00 0xa0000000 0x00 0x100000>;
32			no-map;
33		};
34
35		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
36			compatible = "shared-dma-pool";
37			reg = <0x00 0xa0100000 0x00 0xf00000>;
38			no-map;
39		};
40
41		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
42			compatible = "shared-dma-pool";
43			reg = <0x00 0xa1000000 0x00 0x100000>;
44			no-map;
45		};
46
47		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
48			compatible = "shared-dma-pool";
49			reg = <0x00 0xa1100000 0x00 0xf00000>;
50			no-map;
51		};
52
53		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
54			compatible = "shared-dma-pool";
55			reg = <0x00 0xa2000000 0x00 0x100000>;
56			no-map;
57		};
58
59		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
60			compatible = "shared-dma-pool";
61			reg = <0x00 0xa2100000 0x00 0xf00000>;
62			no-map;
63		};
64
65		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
66			compatible = "shared-dma-pool";
67			reg = <0x00 0xa3000000 0x00 0x100000>;
68			no-map;
69		};
70
71		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
72			compatible = "shared-dma-pool";
73			reg = <0x00 0xa3100000 0x00 0xf00000>;
74			no-map;
75		};
76
77		rtos_ipc_memory_region: ipc-memories@a4000000 {
78			reg = <0x00 0xa4000000 0x00 0x00800000>;
79			alignment = <0x1000>;
80			no-map;
81		};
82	};
83};
84
85&wkup_pmx0 {
86	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
87		pinctrl-single,pins = <
88			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
89			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
90			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
91			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
92			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
93			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
94			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
95			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
96			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
97			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
98			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
99			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
100			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
101		>;
102	};
103
104	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
105		pinctrl-single,pins = <
106			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
107			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
108			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
109			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
110			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
111			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
112			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
113			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
114			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
115			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
116			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
117		>;
118	};
119};
120
121&main_pmx0 {
122	main_i2c0_pins_default: main-i2c0-pins-default {
123		pinctrl-single,pins = <
124			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
125			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
126		>;
127	};
128};
129
130&hbmc {
131	/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
132	 * appropriate node based on board detection
133	 */
134	status = "disabled";
135	pinctrl-names = "default";
136	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
137	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
138		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
139
140	flash@0,0 {
141		compatible = "cypress,hyperflash", "cfi-flash";
142		reg = <0x00 0x00 0x4000000>;
143	};
144};
145
146&mailbox0_cluster0 {
147	interrupts = <436>;
148
149	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
150		ti,mbox-rx = <0 0 0>;
151		ti,mbox-tx = <1 0 0>;
152	};
153
154	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
155		ti,mbox-rx = <2 0 0>;
156		ti,mbox-tx = <3 0 0>;
157	};
158};
159
160&mailbox0_cluster1 {
161	interrupts = <432>;
162
163	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
164		ti,mbox-rx = <0 0 0>;
165		ti,mbox-tx = <1 0 0>;
166	};
167
168	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
169		ti,mbox-rx = <2 0 0>;
170		ti,mbox-tx = <3 0 0>;
171	};
172};
173
174&mailbox0_cluster2 {
175	status = "disabled";
176};
177
178&mailbox0_cluster3 {
179	status = "disabled";
180};
181
182&mailbox0_cluster4 {
183	status = "disabled";
184};
185
186&mailbox0_cluster5 {
187	status = "disabled";
188};
189
190&mailbox0_cluster6 {
191	status = "disabled";
192};
193
194&mailbox0_cluster7 {
195	status = "disabled";
196};
197
198&mailbox0_cluster8 {
199	status = "disabled";
200};
201
202&mailbox0_cluster9 {
203	status = "disabled";
204};
205
206&mailbox0_cluster10 {
207	status = "disabled";
208};
209
210&mailbox0_cluster11 {
211	status = "disabled";
212};
213
214&mcu_r5fss0_core0 {
215	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
216	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
217			<&mcu_r5fss0_core0_memory_region>;
218};
219
220&mcu_r5fss0_core1 {
221	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
222	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
223			<&mcu_r5fss0_core1_memory_region>;
224};
225
226&main_r5fss0_core0 {
227	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
228	memory-region = <&main_r5fss0_core0_dma_memory_region>,
229			<&main_r5fss0_core0_memory_region>;
230};
231
232&main_r5fss0_core1 {
233	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
234	memory-region = <&main_r5fss0_core1_dma_memory_region>,
235			<&main_r5fss0_core1_memory_region>;
236};
237
238&main_i2c0 {
239	pinctrl-names = "default";
240	pinctrl-0 = <&main_i2c0_pins_default>;
241	clock-frequency = <400000>;
242
243	exp_som: gpio@21 {
244		compatible = "ti,tca6408";
245		reg = <0x21>;
246		gpio-controller;
247		#gpio-cells = <2>;
248		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
249				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
250				  "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
251				  "GPIO_LIN_EN", "CAN_STB";
252	};
253};
254
255&ospi0 {
256	pinctrl-names = "default";
257	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
258
259	flash@0{
260		compatible = "jedec,spi-nor";
261		reg = <0x0>;
262		spi-tx-bus-width = <8>;
263		spi-rx-bus-width = <8>;
264		spi-max-frequency = <25000000>;
265		cdns,tshsl-ns = <60>;
266		cdns,tsd2d-ns = <60>;
267		cdns,tchsh-ns = <60>;
268		cdns,tslch-ns = <60>;
269		cdns,read-delay = <4>;
270		#address-cells = <1>;
271		#size-cells = <1>;
272	};
273};
274