1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721e-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy-cadence.h> 13 14/ { 15 compatible = "ti,j721e-evm", "ti,j721e"; 16 model = "Texas Instruments J721e EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 21 }; 22 23 gpio_keys: gpio-keys { 24 compatible = "gpio-keys"; 25 autorepeat; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; 28 29 sw10: switch-10 { 30 label = "GPIO Key USER1"; 31 linux,code = <BTN_0>; 32 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; 33 }; 34 35 sw11: switch-11 { 36 label = "GPIO Key USER2"; 37 linux,code = <BTN_1>; 38 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; 39 }; 40 }; 41 42 evm_12v0: fixedregulator-evm12v0 { 43 /* main supply */ 44 compatible = "regulator-fixed"; 45 regulator-name = "evm_12v0"; 46 regulator-min-microvolt = <12000000>; 47 regulator-max-microvolt = <12000000>; 48 regulator-always-on; 49 regulator-boot-on; 50 }; 51 52 vsys_3v3: fixedregulator-vsys3v3 { 53 /* Output of LMS140 */ 54 compatible = "regulator-fixed"; 55 regulator-name = "vsys_3v3"; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 vin-supply = <&evm_12v0>; 59 regulator-always-on; 60 regulator-boot-on; 61 }; 62 63 vsys_5v0: fixedregulator-vsys5v0 { 64 /* Output of LM5140 */ 65 compatible = "regulator-fixed"; 66 regulator-name = "vsys_5v0"; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 vin-supply = <&evm_12v0>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 vdd_mmc1: fixedregulator-sd { 75 compatible = "regulator-fixed"; 76 regulator-name = "vdd_mmc1"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 regulator-boot-on; 80 enable-active-high; 81 vin-supply = <&vsys_3v3>; 82 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 83 }; 84 85 vdd_sd_dv_alt: gpio-regulator-TLV71033 { 86 compatible = "regulator-gpio"; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 89 regulator-name = "tlv71033"; 90 regulator-min-microvolt = <1800000>; 91 regulator-max-microvolt = <3300000>; 92 regulator-boot-on; 93 vin-supply = <&vsys_5v0>; 94 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 95 states = <1800000 0x0>, 96 <3300000 0x1>; 97 }; 98 99 sound0: sound-0 { 100 compatible = "ti,j721e-cpb-audio"; 101 model = "j721e-cpb"; 102 103 ti,cpb-mcasp = <&mcasp10>; 104 ti,cpb-codec = <&pcm3168a_1>; 105 106 clocks = <&k3_clks 184 1>, 107 <&k3_clks 184 2>, <&k3_clks 184 4>, 108 <&k3_clks 157 371>, 109 <&k3_clks 157 400>, <&k3_clks 157 401>; 110 clock-names = "cpb-mcasp-auxclk", 111 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", 112 "cpb-codec-scki", 113 "cpb-codec-scki-48000", "cpb-codec-scki-44100"; 114 }; 115 116 transceiver1: can-phy0 { 117 compatible = "ti,tcan1043"; 118 #phy-cells = <0>; 119 max-bitrate = <5000000>; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 122 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; 123 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 124 }; 125 126 transceiver2: can-phy1 { 127 compatible = "ti,tcan1042"; 128 #phy-cells = <0>; 129 max-bitrate = <5000000>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 132 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 133 }; 134 135 transceiver3: can-phy2 { 136 compatible = "ti,tcan1043"; 137 #phy-cells = <0>; 138 max-bitrate = <5000000>; 139 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; 140 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 141 }; 142 143 transceiver4: can-phy3 { 144 compatible = "ti,tcan1042"; 145 #phy-cells = <0>; 146 max-bitrate = <5000000>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&main_mcan2_gpio_pins_default>; 149 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; 150 }; 151 152 dp_pwr_3v3: regulator-dp-pwr { 153 compatible = "regulator-fixed"; 154 regulator-name = "dp-pwr"; 155 regulator-min-microvolt = <3300000>; 156 regulator-max-microvolt = <3300000>; 157 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ 158 enable-active-high; 159 }; 160 161 dp0: connector { 162 compatible = "dp-connector"; 163 label = "DP0"; 164 type = "full-size"; 165 dp-pwr-supply = <&dp_pwr_3v3>; 166 167 port { 168 dp_connector_in: endpoint { 169 remote-endpoint = <&dp0_out>; 170 }; 171 }; 172 }; 173}; 174 175&main_pmx0 { 176 sw10_button_pins_default: sw10-button-pins-default { 177 pinctrl-single,pins = < 178 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ 179 >; 180 }; 181 182 main_mmc1_pins_default: main-mmc1-pins-default { 183 pinctrl-single,pins = < 184 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 185 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 186 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 187 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 188 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 189 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 190 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 191 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 192 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 193 >; 194 }; 195 196 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 197 pinctrl-single,pins = < 198 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 199 >; 200 }; 201 202 main_usbss0_pins_default: main-usbss0-pins-default { 203 pinctrl-single,pins = < 204 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 205 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 206 >; 207 }; 208 209 main_usbss1_pins_default: main-usbss1-pins-default { 210 pinctrl-single,pins = < 211 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 212 >; 213 }; 214 215 dp0_pins_default: dp0-pins-default { 216 pinctrl-single,pins = < 217 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 218 >; 219 }; 220 221 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { 222 pinctrl-single,pins = < 223 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ 224 >; 225 }; 226 227 main_i2c0_pins_default: main-i2c0-pins-default { 228 pinctrl-single,pins = < 229 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 230 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 231 >; 232 }; 233 234 main_i2c1_pins_default: main-i2c1-pins-default { 235 pinctrl-single,pins = < 236 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 237 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 238 >; 239 }; 240 241 main_i2c3_pins_default: main-i2c3-pins-default { 242 pinctrl-single,pins = < 243 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 244 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 245 >; 246 }; 247 248 main_i2c6_pins_default: main-i2c6-pins-default { 249 pinctrl-single,pins = < 250 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 251 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 252 >; 253 }; 254 255 mcasp10_pins_default: mcasp10-pins-default { 256 pinctrl-single,pins = < 257 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ 258 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ 259 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ 260 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ 261 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ 262 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ 263 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ 264 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ 265 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ 266 >; 267 }; 268 269 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { 270 pinctrl-single,pins = < 271 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ 272 >; 273 }; 274 275 main_mcan0_pins_default: main-mcan0-pins-default { 276 pinctrl-single,pins = < 277 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ 278 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ 279 >; 280 }; 281 282 main_mcan2_pins_default: main-mcan2-pins-default { 283 pinctrl-single,pins = < 284 J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ 285 J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ 286 >; 287 }; 288 289 main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default { 290 pinctrl-single,pins = < 291 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 292 >; 293 }; 294}; 295 296&wkup_pmx0 { 297 sw11_button_pins_default: sw11-button-pins-default { 298 pinctrl-single,pins = < 299 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 300 >; 301 }; 302 303 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { 304 pinctrl-single,pins = < 305 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 306 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 307 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 308 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 309 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 310 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 311 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 312 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 313 >; 314 }; 315 316 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 317 pinctrl-single,pins = < 318 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 319 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 320 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 321 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 322 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 323 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 324 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 325 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 326 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 327 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 328 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 329 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 330 >; 331 }; 332 333 mcu_mdio_pins_default: mcu-mdio1-pins-default { 334 pinctrl-single,pins = < 335 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ 336 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ 337 >; 338 }; 339 340 mcu_mcan0_pins_default: mcu-mcan0-pins-default { 341 pinctrl-single,pins = < 342 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ 343 J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ 344 >; 345 }; 346 347 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { 348 pinctrl-single,pins = < 349 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ 350 J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ 351 >; 352 }; 353 354 mcu_mcan1_pins_default: mcu-mcan1-pins-default { 355 pinctrl-single,pins = < 356 J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ 357 J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ 358 >; 359 }; 360 361 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { 362 pinctrl-single,pins = < 363 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ 364 >; 365 }; 366}; 367 368&wkup_uart0 { 369 /* Wakeup UART is used by System firmware */ 370 status = "reserved"; 371}; 372 373&mcu_uart0 { 374 status = "okay"; 375 /* Default pinmux */ 376}; 377 378&main_uart0 { 379 status = "okay"; 380 /* Shared with ATF on this platform */ 381 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 382}; 383 384&main_uart1 { 385 status = "okay"; 386 /* Default pinmux */ 387}; 388 389&main_uart2 { 390 status = "okay"; 391 /* Default pinmux */ 392}; 393 394&main_uart4 { 395 status = "okay"; 396 /* Default pinmux */ 397}; 398 399&main_gpio2 { 400 status = "disabled"; 401}; 402 403&main_gpio3 { 404 status = "disabled"; 405}; 406 407&main_gpio4 { 408 status = "disabled"; 409}; 410 411&main_gpio5 { 412 status = "disabled"; 413}; 414 415&main_gpio6 { 416 status = "disabled"; 417}; 418 419&main_gpio7 { 420 status = "disabled"; 421}; 422 423&wkup_gpio1 { 424 status = "disabled"; 425}; 426 427&main_sdhci0 { 428 /* eMMC */ 429 non-removable; 430 ti,driver-strength-ohm = <50>; 431 disable-wp; 432}; 433 434&main_sdhci1 { 435 /* SD/MMC */ 436 vmmc-supply = <&vdd_mmc1>; 437 vqmmc-supply = <&vdd_sd_dv_alt>; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&main_mmc1_pins_default>; 440 ti,driver-strength-ohm = <50>; 441 disable-wp; 442}; 443 444&main_sdhci2 { 445 /* Unused */ 446 status = "disabled"; 447}; 448 449&usb_serdes_mux { 450 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ 451}; 452 453&serdes_ln_ctrl { 454 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 455 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 456 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 457 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 458 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 459 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 460}; 461 462&serdes_wiz3 { 463 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 464 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 465}; 466 467&serdes3 { 468 serdes3_usb_link: phy@0 { 469 reg = <0>; 470 cdns,num-lanes = <2>; 471 #phy-cells = <0>; 472 cdns,phy-type = <PHY_TYPE_USB3>; 473 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 474 }; 475}; 476 477&usbss0 { 478 pinctrl-names = "default"; 479 pinctrl-0 = <&main_usbss0_pins_default>; 480 ti,vbus-divider; 481}; 482 483&usb0 { 484 dr_mode = "otg"; 485 maximum-speed = "super-speed"; 486 phys = <&serdes3_usb_link>; 487 phy-names = "cdns3,usb3-phy"; 488}; 489 490&usbss1 { 491 pinctrl-names = "default"; 492 pinctrl-0 = <&main_usbss1_pins_default>; 493 ti,usb2-only; 494}; 495 496&usb1 { 497 dr_mode = "host"; 498 maximum-speed = "high-speed"; 499}; 500 501&ospi1 { 502 pinctrl-names = "default"; 503 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 504 505 flash@0 { 506 compatible = "jedec,spi-nor"; 507 reg = <0x0>; 508 spi-tx-bus-width = <1>; 509 spi-rx-bus-width = <4>; 510 spi-max-frequency = <40000000>; 511 cdns,tshsl-ns = <60>; 512 cdns,tsd2d-ns = <60>; 513 cdns,tchsh-ns = <60>; 514 cdns,tslch-ns = <60>; 515 cdns,read-delay = <2>; 516 }; 517}; 518 519&tscadc0 { 520 adc { 521 ti,adc-channels = <0 1 2 3 4 5 6 7>; 522 }; 523}; 524 525&tscadc1 { 526 adc { 527 ti,adc-channels = <0 1 2 3 4 5 6 7>; 528 }; 529}; 530 531&main_i2c0 { 532 status = "okay"; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&main_i2c0_pins_default>; 535 clock-frequency = <400000>; 536 537 exp1: gpio@20 { 538 compatible = "ti,tca6416"; 539 reg = <0x20>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 }; 543 544 exp2: gpio@22 { 545 compatible = "ti,tca6424"; 546 reg = <0x22>; 547 gpio-controller; 548 #gpio-cells = <2>; 549 550 p09-hog { 551 /* P11 - MCASP/TRACE_MUX_S0 */ 552 gpio-hog; 553 gpios = <9 GPIO_ACTIVE_HIGH>; 554 output-low; 555 line-name = "MCASP/TRACE_MUX_S0"; 556 }; 557 558 p10-hog { 559 /* P12 - MCASP/TRACE_MUX_S1 */ 560 gpio-hog; 561 gpios = <10 GPIO_ACTIVE_HIGH>; 562 output-high; 563 line-name = "MCASP/TRACE_MUX_S1"; 564 }; 565 }; 566}; 567 568&main_i2c1 { 569 status = "okay"; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&main_i2c1_pins_default>; 572 clock-frequency = <400000>; 573 574 exp4: gpio@20 { 575 compatible = "ti,tca6408"; 576 reg = <0x20>; 577 gpio-controller; 578 #gpio-cells = <2>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&main_i2c1_exp4_pins_default>; 581 interrupt-parent = <&main_gpio1>; 582 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586}; 587 588&k3_clks { 589 /* Confiure AUDIO_EXT_REFCLK2 pin as output */ 590 pinctrl-names = "default"; 591 pinctrl-0 = <&audi_ext_refclk2_pins_default>; 592}; 593 594&main_i2c3 { 595 status = "okay"; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&main_i2c3_pins_default>; 598 clock-frequency = <400000>; 599 600 exp3: gpio@20 { 601 compatible = "ti,tca6408"; 602 reg = <0x20>; 603 gpio-controller; 604 #gpio-cells = <2>; 605 }; 606 607 pcm3168a_1: audio-codec@44 { 608 compatible = "ti,pcm3168a"; 609 reg = <0x44>; 610 611 #sound-dai-cells = <1>; 612 613 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 614 615 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ 616 clocks = <&k3_clks 157 371>; 617 clock-names = "scki"; 618 619 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ 620 assigned-clocks = <&k3_clks 157 371>; 621 assigned-clock-parents = <&k3_clks 157 400>; 622 assigned-clock-rates = <24576000>; /* for 48KHz */ 623 624 VDD1-supply = <&vsys_3v3>; 625 VDD2-supply = <&vsys_3v3>; 626 VCCAD1-supply = <&vsys_5v0>; 627 VCCAD2-supply = <&vsys_5v0>; 628 VCCDA1-supply = <&vsys_5v0>; 629 VCCDA2-supply = <&vsys_5v0>; 630 }; 631}; 632 633&main_i2c6 { 634 status = "okay"; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&main_i2c6_pins_default>; 637 clock-frequency = <400000>; 638 639 exp5: gpio@20 { 640 compatible = "ti,tca6408"; 641 reg = <0x20>; 642 gpio-controller; 643 #gpio-cells = <2>; 644 }; 645}; 646 647&mcu_cpsw { 648 pinctrl-names = "default"; 649 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 650}; 651 652&davinci_mdio { 653 phy0: ethernet-phy@0 { 654 reg = <0>; 655 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 656 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 657 }; 658}; 659 660&cpsw_port1 { 661 phy-mode = "rgmii-rxid"; 662 phy-handle = <&phy0>; 663}; 664 665&dss { 666 /* 667 * These clock assignments are chosen to enable the following outputs: 668 * 669 * VP0 - DisplayPort SST 670 * VP1 - DPI0 671 * VP2 - DSI 672 * VP3 - DPI1 673 */ 674 675 assigned-clocks = <&k3_clks 152 1>, 676 <&k3_clks 152 4>, 677 <&k3_clks 152 9>, 678 <&k3_clks 152 13>; 679 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 680 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 681 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 682 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 683}; 684 685&dss_ports { 686 port { 687 dpi0_out: endpoint { 688 remote-endpoint = <&dp0_in>; 689 }; 690 }; 691}; 692 693&dp0_ports { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 port@0 { 698 reg = <0>; 699 dp0_in: endpoint { 700 remote-endpoint = <&dpi0_out>; 701 }; 702 }; 703 704 port@4 { 705 reg = <4>; 706 dp0_out: endpoint { 707 remote-endpoint = <&dp_connector_in>; 708 }; 709 }; 710}; 711 712&mcasp10 { 713 status = "okay"; 714 #sound-dai-cells = <0>; 715 716 pinctrl-names = "default"; 717 pinctrl-0 = <&mcasp10_pins_default>; 718 719 op-mode = <0>; /* MCASP_IIS_MODE */ 720 tdm-slots = <2>; 721 auxclk-fs-ratio = <256>; 722 723 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 724 1 1 1 1 725 2 2 2 0 726 >; 727 tx-num-evt = <0>; 728 rx-num-evt = <0>; 729}; 730 731&cmn_refclk1 { 732 clock-frequency = <100000000>; 733}; 734 735&wiz0_pll1_refclk { 736 assigned-clocks = <&wiz0_pll1_refclk>; 737 assigned-clock-parents = <&cmn_refclk1>; 738}; 739 740&wiz0_refclk_dig { 741 assigned-clocks = <&wiz0_refclk_dig>; 742 assigned-clock-parents = <&cmn_refclk1>; 743}; 744 745&wiz1_pll1_refclk { 746 assigned-clocks = <&wiz1_pll1_refclk>; 747 assigned-clock-parents = <&cmn_refclk1>; 748}; 749 750&wiz1_refclk_dig { 751 assigned-clocks = <&wiz1_refclk_dig>; 752 assigned-clock-parents = <&cmn_refclk1>; 753}; 754 755&wiz2_pll1_refclk { 756 assigned-clocks = <&wiz2_pll1_refclk>; 757 assigned-clock-parents = <&cmn_refclk1>; 758}; 759 760&wiz2_refclk_dig { 761 assigned-clocks = <&wiz2_refclk_dig>; 762 assigned-clock-parents = <&cmn_refclk1>; 763}; 764 765&serdes0 { 766 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; 767 assigned-clock-parents = <&wiz0_pll1_refclk>; 768 769 serdes0_pcie_link: phy@0 { 770 reg = <0>; 771 cdns,num-lanes = <1>; 772 #phy-cells = <0>; 773 cdns,phy-type = <PHY_TYPE_PCIE>; 774 resets = <&serdes_wiz0 1>; 775 }; 776}; 777 778&serdes1 { 779 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; 780 assigned-clock-parents = <&wiz1_pll1_refclk>; 781 782 serdes1_pcie_link: phy@0 { 783 reg = <0>; 784 cdns,num-lanes = <2>; 785 #phy-cells = <0>; 786 cdns,phy-type = <PHY_TYPE_PCIE>; 787 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 788 }; 789}; 790 791&serdes2 { 792 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; 793 assigned-clock-parents = <&wiz2_pll1_refclk>; 794 795 serdes2_pcie_link: phy@0 { 796 reg = <0>; 797 cdns,num-lanes = <2>; 798 #phy-cells = <0>; 799 cdns,phy-type = <PHY_TYPE_PCIE>; 800 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; 801 }; 802}; 803 804&serdes4 { 805 torrent_phy_dp: phy@0 { 806 reg = <0>; 807 resets = <&serdes_wiz4 1>; 808 cdns,phy-type = <PHY_TYPE_DP>; 809 cdns,num-lanes = <4>; 810 cdns,max-bit-rate = <5400>; 811 #phy-cells = <0>; 812 }; 813}; 814 815&mhdp { 816 phys = <&torrent_phy_dp>; 817 phy-names = "dpphy"; 818 pinctrl-names = "default"; 819 pinctrl-0 = <&dp0_pins_default>; 820}; 821 822&pcie0_rc { 823 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 824 phys = <&serdes0_pcie_link>; 825 phy-names = "pcie-phy"; 826 num-lanes = <1>; 827}; 828 829&pcie1_rc { 830 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 831 phys = <&serdes1_pcie_link>; 832 phy-names = "pcie-phy"; 833 num-lanes = <2>; 834}; 835 836&pcie2_rc { 837 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; 838 phys = <&serdes2_pcie_link>; 839 phy-names = "pcie-phy"; 840 num-lanes = <2>; 841}; 842 843&pcie0_ep { 844 phys = <&serdes0_pcie_link>; 845 phy-names = "pcie-phy"; 846 num-lanes = <1>; 847 status = "disabled"; 848}; 849 850&pcie1_ep { 851 phys = <&serdes1_pcie_link>; 852 phy-names = "pcie-phy"; 853 num-lanes = <2>; 854 status = "disabled"; 855}; 856 857&pcie2_ep { 858 phys = <&serdes2_pcie_link>; 859 phy-names = "pcie-phy"; 860 num-lanes = <2>; 861 status = "disabled"; 862}; 863 864&pcie3_rc { 865 status = "disabled"; 866}; 867 868&pcie3_ep { 869 status = "disabled"; 870}; 871 872&icssg0_mdio { 873 status = "disabled"; 874}; 875 876&icssg1_mdio { 877 status = "disabled"; 878}; 879 880&mcu_mcan0 { 881 status = "okay"; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&mcu_mcan0_pins_default>; 884 phys = <&transceiver1>; 885}; 886 887&mcu_mcan1 { 888 status = "okay"; 889 pinctrl-names = "default"; 890 pinctrl-0 = <&mcu_mcan1_pins_default>; 891 phys = <&transceiver2>; 892}; 893 894&main_mcan0 { 895 status = "okay"; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&main_mcan0_pins_default>; 898 phys = <&transceiver3>; 899}; 900 901&main_mcan2 { 902 status = "okay"; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&main_mcan2_pins_default>; 905 phys = <&transceiver4>; 906}; 907