1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Product Link: https://www.ti.com/tool/J721EXCPXEVM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e-som-p0.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14#include <dt-bindings/phy/phy-cadence.h> 15 16/ { 17 compatible = "ti,j721e-evm", "ti,j721e"; 18 model = "Texas Instruments J721e EVM"; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial1 = &mcu_uart0; 23 serial2 = &main_uart0; 24 serial3 = &main_uart1; 25 serial4 = &main_uart2; 26 serial6 = &main_uart4; 27 ethernet0 = &cpsw_port1; 28 mmc0 = &main_sdhci0; 29 mmc1 = &main_sdhci1; 30 }; 31 32 chosen { 33 stdout-path = "serial2:115200n8"; 34 }; 35 36 gpio_keys: gpio-keys { 37 compatible = "gpio-keys"; 38 autorepeat; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; 41 42 sw10: switch-10 { 43 label = "GPIO Key USER1"; 44 linux,code = <BTN_0>; 45 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; 46 }; 47 48 sw11: switch-11 { 49 label = "GPIO Key USER2"; 50 linux,code = <BTN_1>; 51 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; 52 }; 53 }; 54 55 evm_12v0: fixedregulator-evm12v0 { 56 /* main supply */ 57 compatible = "regulator-fixed"; 58 regulator-name = "evm_12v0"; 59 regulator-min-microvolt = <12000000>; 60 regulator-max-microvolt = <12000000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 vsys_3v3: fixedregulator-vsys3v3 { 66 /* Output of LMS140 */ 67 compatible = "regulator-fixed"; 68 regulator-name = "vsys_3v3"; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 vin-supply = <&evm_12v0>; 72 regulator-always-on; 73 regulator-boot-on; 74 }; 75 76 vsys_5v0: fixedregulator-vsys5v0 { 77 /* Output of LM5140 */ 78 compatible = "regulator-fixed"; 79 regulator-name = "vsys_5v0"; 80 regulator-min-microvolt = <5000000>; 81 regulator-max-microvolt = <5000000>; 82 vin-supply = <&evm_12v0>; 83 regulator-always-on; 84 regulator-boot-on; 85 }; 86 87 vdd_mmc1: fixedregulator-sd { 88 compatible = "regulator-fixed"; 89 regulator-name = "vdd_mmc1"; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 regulator-boot-on; 93 enable-active-high; 94 vin-supply = <&vsys_3v3>; 95 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 96 }; 97 98 vdd_sd_dv_alt: gpio-regulator-TLV71033 { 99 compatible = "regulator-gpio"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 102 regulator-name = "tlv71033"; 103 regulator-min-microvolt = <1800000>; 104 regulator-max-microvolt = <3300000>; 105 regulator-boot-on; 106 vin-supply = <&vsys_5v0>; 107 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 108 states = <1800000 0x0>, 109 <3300000 0x1>; 110 }; 111 112 sound0: sound-0 { 113 compatible = "ti,j721e-cpb-audio"; 114 model = "j721e-cpb"; 115 116 ti,cpb-mcasp = <&mcasp10>; 117 ti,cpb-codec = <&pcm3168a_1>; 118 119 clocks = <&k3_clks 184 1>, 120 <&k3_clks 184 2>, <&k3_clks 184 4>, 121 <&k3_clks 157 371>, 122 <&k3_clks 157 400>, <&k3_clks 157 401>; 123 clock-names = "cpb-mcasp-auxclk", 124 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", 125 "cpb-codec-scki", 126 "cpb-codec-scki-48000", "cpb-codec-scki-44100"; 127 }; 128 129 transceiver1: can-phy0 { 130 compatible = "ti,tcan1043"; 131 #phy-cells = <0>; 132 max-bitrate = <5000000>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 135 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>; 136 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>; 137 }; 138 139 transceiver2: can-phy1 { 140 compatible = "ti,tcan1042"; 141 #phy-cells = <0>; 142 max-bitrate = <5000000>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 145 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 146 }; 147 148 transceiver3: can-phy2 { 149 compatible = "ti,tcan1043"; 150 #phy-cells = <0>; 151 max-bitrate = <5000000>; 152 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; 153 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 154 }; 155 156 transceiver4: can-phy3 { 157 compatible = "ti,tcan1042"; 158 #phy-cells = <0>; 159 max-bitrate = <5000000>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&main_mcan2_gpio_pins_default>; 162 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; 163 }; 164 165 dp_pwr_3v3: regulator-dp-pwr { 166 compatible = "regulator-fixed"; 167 regulator-name = "dp-pwr"; 168 regulator-min-microvolt = <3300000>; 169 regulator-max-microvolt = <3300000>; 170 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ 171 enable-active-high; 172 }; 173 174 dp0: connector { 175 compatible = "dp-connector"; 176 label = "DP0"; 177 type = "full-size"; 178 dp-pwr-supply = <&dp_pwr_3v3>; 179 180 port { 181 dp_connector_in: endpoint { 182 remote-endpoint = <&dp0_out>; 183 }; 184 }; 185 }; 186}; 187 188&main_pmx0 { 189 main_uart0_pins_default: main-uart0-default-pins { 190 pinctrl-single,pins = < 191 J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ 192 J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ 193 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 194 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 195 >; 196 }; 197 198 main_uart1_pins_default: main-uart1-default-pins { 199 pinctrl-single,pins = < 200 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ 201 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ 202 >; 203 }; 204 205 main_uart2_pins_default: main-uart2-default-pins { 206 pinctrl-single,pins = < 207 J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ 208 J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ 209 >; 210 }; 211 212 main_uart4_pins_default: main-uart4-default-pins { 213 pinctrl-single,pins = < 214 J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ 215 J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ 216 >; 217 }; 218 219 sw10_button_pins_default: sw10-button-default-pins { 220 pinctrl-single,pins = < 221 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ 222 >; 223 }; 224 225 main_mmc1_pins_default: main-mmc1-default-pins { 226 pinctrl-single,pins = < 227 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 228 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 229 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 230 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 231 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 232 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 233 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 234 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 235 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 236 >; 237 }; 238 239 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 240 pinctrl-single,pins = < 241 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 242 >; 243 }; 244 245 main_usbss0_pins_default: main-usbss0-default-pins { 246 pinctrl-single,pins = < 247 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 248 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 249 >; 250 }; 251 252 main_usbss1_pins_default: main-usbss1-default-pins { 253 pinctrl-single,pins = < 254 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 255 >; 256 }; 257 258 dp0_pins_default: dp0-default-pins { 259 pinctrl-single,pins = < 260 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 261 >; 262 }; 263 264 main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { 265 pinctrl-single,pins = < 266 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ 267 >; 268 }; 269 270 main_i2c0_pins_default: main-i2c0-default-pins { 271 pinctrl-single,pins = < 272 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 273 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 274 >; 275 }; 276 277 main_i2c1_pins_default: main-i2c1-default-pins { 278 pinctrl-single,pins = < 279 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 280 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 281 >; 282 }; 283 284 main_i2c3_pins_default: main-i2c3-default-pins { 285 pinctrl-single,pins = < 286 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 287 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 288 >; 289 }; 290 291 main_i2c6_pins_default: main-i2c6-default-pins { 292 pinctrl-single,pins = < 293 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 294 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 295 >; 296 }; 297 298 mcasp10_pins_default: mcasp10-default-pins { 299 pinctrl-single,pins = < 300 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ 301 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ 302 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ 303 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ 304 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ 305 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ 306 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ 307 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ 308 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ 309 >; 310 }; 311 312 audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { 313 pinctrl-single,pins = < 314 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ 315 >; 316 }; 317 318 main_mcan0_pins_default: main-mcan0-default-pins { 319 pinctrl-single,pins = < 320 J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ 321 J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ 322 >; 323 }; 324 325 main_mcan2_pins_default: main-mcan2-default-pins { 326 pinctrl-single,pins = < 327 J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ 328 J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ 329 >; 330 }; 331 332 main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { 333 pinctrl-single,pins = < 334 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 335 >; 336 }; 337}; 338 339&wkup_pmx0 { 340 wkup_uart0_pins_default: wkup-uart0-default-pins { 341 pinctrl-single,pins = < 342 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 343 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 344 >; 345 }; 346 347 mcu_uart0_pins_default: mcu-uart0-default-pins { 348 pinctrl-single,pins = < 349 J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ 350 J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ 351 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 352 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 353 >; 354 }; 355 356 sw11_button_pins_default: sw11-button-default-pins { 357 pinctrl-single,pins = < 358 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 359 >; 360 }; 361 362 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 363 pinctrl-single,pins = < 364 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 365 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 366 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 367 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 368 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 369 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 370 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 371 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 372 >; 373 }; 374 375 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 376 pinctrl-single,pins = < 377 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 378 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 379 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 380 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 381 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 382 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 383 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 384 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 385 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 386 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 387 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 388 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 389 >; 390 }; 391 392 mcu_mdio_pins_default: mcu-mdio1-default-pins { 393 pinctrl-single,pins = < 394 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ 395 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ 396 >; 397 }; 398 399 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 400 pinctrl-single,pins = < 401 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ 402 J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ 403 >; 404 }; 405 406 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 407 pinctrl-single,pins = < 408 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ 409 J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ 410 >; 411 }; 412 413 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 414 pinctrl-single,pins = < 415 J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ 416 J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ 417 >; 418 }; 419 420 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 421 pinctrl-single,pins = < 422 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ 423 >; 424 }; 425 426 wkup_gpio_pins_default: wkup-gpio-default-pins { 427 pinctrl-single,pins = < 428 J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ 429 >; 430 }; 431}; 432 433&wkup_uart0 { 434 /* Wakeup UART is used by System firmware */ 435 status = "reserved"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&wkup_uart0_pins_default>; 438}; 439 440&mcu_uart0 { 441 status = "okay"; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&mcu_uart0_pins_default>; 444}; 445 446&main_uart0 { 447 status = "okay"; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&main_uart0_pins_default>; 450 /* Shared with ATF on this platform */ 451 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 452}; 453 454&main_uart1 { 455 status = "okay"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&main_uart1_pins_default>; 458}; 459 460&main_uart2 { 461 status = "okay"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&main_uart2_pins_default>; 464}; 465 466&main_uart4 { 467 status = "okay"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&main_uart4_pins_default>; 470}; 471 472&main_gpio2 { 473 status = "disabled"; 474}; 475 476&main_gpio3 { 477 status = "disabled"; 478}; 479 480&main_gpio4 { 481 status = "disabled"; 482}; 483 484&main_gpio5 { 485 status = "disabled"; 486}; 487 488&main_gpio6 { 489 status = "disabled"; 490}; 491 492&main_gpio7 { 493 status = "disabled"; 494}; 495 496&wkup_gpio0 { 497 pinctrl-names = "default"; 498 pinctrl-0 = <&wkup_gpio_pins_default>; 499}; 500 501&wkup_gpio1 { 502 status = "disabled"; 503}; 504 505&main_sdhci0 { 506 /* eMMC */ 507 non-removable; 508 ti,driver-strength-ohm = <50>; 509 disable-wp; 510}; 511 512&main_sdhci1 { 513 /* SD/MMC */ 514 vmmc-supply = <&vdd_mmc1>; 515 vqmmc-supply = <&vdd_sd_dv_alt>; 516 pinctrl-names = "default"; 517 pinctrl-0 = <&main_mmc1_pins_default>; 518 ti,driver-strength-ohm = <50>; 519 disable-wp; 520}; 521 522&main_sdhci2 { 523 /* Unused */ 524 status = "disabled"; 525}; 526 527&usb_serdes_mux { 528 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ 529}; 530 531&serdes_ln_ctrl { 532 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 533 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 534 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 535 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 536 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 537 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 538}; 539 540&serdes_wiz3 { 541 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 542 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 543}; 544 545&serdes3 { 546 serdes3_usb_link: phy@0 { 547 reg = <0>; 548 cdns,num-lanes = <2>; 549 #phy-cells = <0>; 550 cdns,phy-type = <PHY_TYPE_USB3>; 551 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 552 }; 553}; 554 555&usbss0 { 556 pinctrl-names = "default"; 557 pinctrl-0 = <&main_usbss0_pins_default>; 558 ti,vbus-divider; 559}; 560 561&usb0 { 562 dr_mode = "otg"; 563 maximum-speed = "super-speed"; 564 phys = <&serdes3_usb_link>; 565 phy-names = "cdns3,usb3-phy"; 566}; 567 568&usbss1 { 569 pinctrl-names = "default"; 570 pinctrl-0 = <&main_usbss1_pins_default>; 571 ti,usb2-only; 572}; 573 574&usb1 { 575 dr_mode = "host"; 576 maximum-speed = "high-speed"; 577}; 578 579&ospi1 { 580 pinctrl-names = "default"; 581 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 582 583 flash@0 { 584 compatible = "jedec,spi-nor"; 585 reg = <0x0>; 586 spi-tx-bus-width = <1>; 587 spi-rx-bus-width = <4>; 588 spi-max-frequency = <40000000>; 589 cdns,tshsl-ns = <60>; 590 cdns,tsd2d-ns = <60>; 591 cdns,tchsh-ns = <60>; 592 cdns,tslch-ns = <60>; 593 cdns,read-delay = <2>; 594 595 partitions { 596 compatible = "fixed-partitions"; 597 #address-cells = <1>; 598 #size-cells = <1>; 599 600 partition@0 { 601 label = "qspi.tiboot3"; 602 reg = <0x0 0x80000>; 603 }; 604 605 partition@80000 { 606 label = "qspi.tispl"; 607 reg = <0x80000 0x200000>; 608 }; 609 610 partition@280000 { 611 label = "qspi.u-boot"; 612 reg = <0x280000 0x400000>; 613 }; 614 615 partition@680000 { 616 label = "qspi.env"; 617 reg = <0x680000 0x20000>; 618 }; 619 620 partition@6a0000 { 621 label = "qspi.env.backup"; 622 reg = <0x6a0000 0x20000>; 623 }; 624 625 partition@6c0000 { 626 label = "qspi.sysfw"; 627 reg = <0x6c0000 0x100000>; 628 }; 629 630 partition@800000 { 631 label = "qspi.rootfs"; 632 reg = <0x800000 0x37c0000>; 633 }; 634 635 partition@3fe0000 { 636 label = "qspi.phypattern"; 637 reg = <0x3fe0000 0x20000>; 638 }; 639 }; 640 }; 641}; 642 643&tscadc0 { 644 adc { 645 ti,adc-channels = <0 1 2 3 4 5 6 7>; 646 }; 647}; 648 649&tscadc1 { 650 adc { 651 ti,adc-channels = <0 1 2 3 4 5 6 7>; 652 }; 653}; 654 655&main_i2c0 { 656 status = "okay"; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&main_i2c0_pins_default>; 659 clock-frequency = <400000>; 660 661 exp1: gpio@20 { 662 compatible = "ti,tca6416"; 663 reg = <0x20>; 664 gpio-controller; 665 #gpio-cells = <2>; 666 }; 667 668 exp2: gpio@22 { 669 compatible = "ti,tca6424"; 670 reg = <0x22>; 671 gpio-controller; 672 #gpio-cells = <2>; 673 674 p09-hog { 675 /* P11 - MCASP/TRACE_MUX_S0 */ 676 gpio-hog; 677 gpios = <9 GPIO_ACTIVE_HIGH>; 678 output-low; 679 line-name = "MCASP/TRACE_MUX_S0"; 680 }; 681 682 p10-hog { 683 /* P12 - MCASP/TRACE_MUX_S1 */ 684 gpio-hog; 685 gpios = <10 GPIO_ACTIVE_HIGH>; 686 output-high; 687 line-name = "MCASP/TRACE_MUX_S1"; 688 }; 689 }; 690}; 691 692&main_i2c1 { 693 status = "okay"; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&main_i2c1_pins_default>; 696 clock-frequency = <400000>; 697 698 exp4: gpio@20 { 699 compatible = "ti,tca6408"; 700 reg = <0x20>; 701 gpio-controller; 702 #gpio-cells = <2>; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&main_i2c1_exp4_pins_default>; 705 interrupt-parent = <&main_gpio1>; 706 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 707 interrupt-controller; 708 #interrupt-cells = <2>; 709 }; 710}; 711 712&k3_clks { 713 /* Confiure AUDIO_EXT_REFCLK2 pin as output */ 714 pinctrl-names = "default"; 715 pinctrl-0 = <&audi_ext_refclk2_pins_default>; 716}; 717 718&main_i2c3 { 719 status = "okay"; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&main_i2c3_pins_default>; 722 clock-frequency = <400000>; 723 724 exp3: gpio@20 { 725 compatible = "ti,tca6408"; 726 reg = <0x20>; 727 gpio-controller; 728 #gpio-cells = <2>; 729 }; 730 731 pcm3168a_1: audio-codec@44 { 732 compatible = "ti,pcm3168a"; 733 reg = <0x44>; 734 735 #sound-dai-cells = <1>; 736 737 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 738 739 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ 740 clocks = <&k3_clks 157 371>; 741 clock-names = "scki"; 742 743 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ 744 assigned-clocks = <&k3_clks 157 371>; 745 assigned-clock-parents = <&k3_clks 157 400>; 746 assigned-clock-rates = <24576000>; /* for 48KHz */ 747 748 VDD1-supply = <&vsys_3v3>; 749 VDD2-supply = <&vsys_3v3>; 750 VCCAD1-supply = <&vsys_5v0>; 751 VCCAD2-supply = <&vsys_5v0>; 752 VCCDA1-supply = <&vsys_5v0>; 753 VCCDA2-supply = <&vsys_5v0>; 754 }; 755}; 756 757&main_i2c6 { 758 status = "okay"; 759 pinctrl-names = "default"; 760 pinctrl-0 = <&main_i2c6_pins_default>; 761 clock-frequency = <400000>; 762 763 exp5: gpio@20 { 764 compatible = "ti,tca6408"; 765 reg = <0x20>; 766 gpio-controller; 767 #gpio-cells = <2>; 768 }; 769}; 770 771&mcu_cpsw { 772 pinctrl-names = "default"; 773 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 774}; 775 776&davinci_mdio { 777 phy0: ethernet-phy@0 { 778 reg = <0>; 779 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 780 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 781 }; 782}; 783 784&cpsw_port1 { 785 phy-mode = "rgmii-rxid"; 786 phy-handle = <&phy0>; 787}; 788 789&dss { 790 /* 791 * These clock assignments are chosen to enable the following outputs: 792 * 793 * VP0 - DisplayPort SST 794 * VP1 - DPI0 795 * VP2 - DSI 796 * VP3 - DPI1 797 */ 798 799 assigned-clocks = <&k3_clks 152 1>, 800 <&k3_clks 152 4>, 801 <&k3_clks 152 9>, 802 <&k3_clks 152 13>; 803 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 804 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 805 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 806 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 807}; 808 809&dss_ports { 810 port { 811 dpi0_out: endpoint { 812 remote-endpoint = <&dp0_in>; 813 }; 814 }; 815}; 816 817&dp0_ports { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 821 port@0 { 822 reg = <0>; 823 dp0_in: endpoint { 824 remote-endpoint = <&dpi0_out>; 825 }; 826 }; 827 828 port@4 { 829 reg = <4>; 830 dp0_out: endpoint { 831 remote-endpoint = <&dp_connector_in>; 832 }; 833 }; 834}; 835 836&mcasp10 { 837 status = "okay"; 838 #sound-dai-cells = <0>; 839 840 pinctrl-names = "default"; 841 pinctrl-0 = <&mcasp10_pins_default>; 842 843 op-mode = <0>; /* MCASP_IIS_MODE */ 844 tdm-slots = <2>; 845 auxclk-fs-ratio = <256>; 846 847 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 848 1 1 1 1 849 2 2 2 0 850 >; 851 tx-num-evt = <0>; 852 rx-num-evt = <0>; 853}; 854 855&cmn_refclk1 { 856 clock-frequency = <100000000>; 857}; 858 859&wiz0_pll1_refclk { 860 assigned-clocks = <&wiz0_pll1_refclk>; 861 assigned-clock-parents = <&cmn_refclk1>; 862}; 863 864&wiz0_refclk_dig { 865 assigned-clocks = <&wiz0_refclk_dig>; 866 assigned-clock-parents = <&cmn_refclk1>; 867}; 868 869&wiz1_pll1_refclk { 870 assigned-clocks = <&wiz1_pll1_refclk>; 871 assigned-clock-parents = <&cmn_refclk1>; 872}; 873 874&wiz1_refclk_dig { 875 assigned-clocks = <&wiz1_refclk_dig>; 876 assigned-clock-parents = <&cmn_refclk1>; 877}; 878 879&wiz2_pll1_refclk { 880 assigned-clocks = <&wiz2_pll1_refclk>; 881 assigned-clock-parents = <&cmn_refclk1>; 882}; 883 884&wiz2_refclk_dig { 885 assigned-clocks = <&wiz2_refclk_dig>; 886 assigned-clock-parents = <&cmn_refclk1>; 887}; 888 889&serdes0 { 890 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; 891 assigned-clock-parents = <&wiz0_pll1_refclk>; 892 893 serdes0_pcie_link: phy@0 { 894 reg = <0>; 895 cdns,num-lanes = <1>; 896 #phy-cells = <0>; 897 cdns,phy-type = <PHY_TYPE_PCIE>; 898 resets = <&serdes_wiz0 1>; 899 }; 900}; 901 902&serdes1 { 903 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; 904 assigned-clock-parents = <&wiz1_pll1_refclk>; 905 906 serdes1_pcie_link: phy@0 { 907 reg = <0>; 908 cdns,num-lanes = <2>; 909 #phy-cells = <0>; 910 cdns,phy-type = <PHY_TYPE_PCIE>; 911 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 912 }; 913}; 914 915&serdes2 { 916 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; 917 assigned-clock-parents = <&wiz2_pll1_refclk>; 918 919 serdes2_pcie_link: phy@0 { 920 reg = <0>; 921 cdns,num-lanes = <2>; 922 #phy-cells = <0>; 923 cdns,phy-type = <PHY_TYPE_PCIE>; 924 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; 925 }; 926}; 927 928&serdes4 { 929 torrent_phy_dp: phy@0 { 930 reg = <0>; 931 resets = <&serdes_wiz4 1>; 932 cdns,phy-type = <PHY_TYPE_DP>; 933 cdns,num-lanes = <4>; 934 cdns,max-bit-rate = <5400>; 935 #phy-cells = <0>; 936 }; 937}; 938 939&mhdp { 940 phys = <&torrent_phy_dp>; 941 phy-names = "dpphy"; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&dp0_pins_default>; 944}; 945 946&pcie0_rc { 947 status = "okay"; 948 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 949 phys = <&serdes0_pcie_link>; 950 phy-names = "pcie-phy"; 951 num-lanes = <1>; 952}; 953 954&pcie1_rc { 955 status = "okay"; 956 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 957 phys = <&serdes1_pcie_link>; 958 phy-names = "pcie-phy"; 959 num-lanes = <2>; 960}; 961 962&pcie2_rc { 963 status = "okay"; 964 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; 965 phys = <&serdes2_pcie_link>; 966 phy-names = "pcie-phy"; 967 num-lanes = <2>; 968}; 969 970&mcu_mcan0 { 971 status = "okay"; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&mcu_mcan0_pins_default>; 974 phys = <&transceiver1>; 975}; 976 977&mcu_mcan1 { 978 status = "okay"; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&mcu_mcan1_pins_default>; 981 phys = <&transceiver2>; 982}; 983 984&main_mcan0 { 985 status = "okay"; 986 pinctrl-names = "default"; 987 pinctrl-0 = <&main_mcan0_pins_default>; 988 phys = <&transceiver3>; 989}; 990 991&main_mcan2 { 992 status = "okay"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&main_mcan2_pins_default>; 995 phys = <&transceiver4>; 996}; 997