1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_main {
9	msmc_ram: sram@70000000 {
10		compatible = "mmio-sram";
11		reg = <0x00 0x70000000 0x00 0x800000>;
12		#address-cells = <1>;
13		#size-cells = <1>;
14		ranges = <0x00 0x00 0x70000000 0x800000>;
15
16		atf-sram@0 {
17			reg = <0x00 0x20000>;
18		};
19
20		tifs-sram@1f0000 {
21			reg = <0x1f0000 0x10000>;
22		};
23
24		l3cache-sram@200000 {
25			reg = <0x200000 0x200000>;
26		};
27	};
28
29	gic500: interrupt-controller@1800000 {
30		compatible = "arm,gic-v3";
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34		#interrupt-cells = <3>;
35		interrupt-controller;
36		reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
37		      <0x00 0x01900000 0x00 0x100000>, /* GICR */
38		      <0x00 0x6f000000 0x00 0x2000>,   /* GICC */
39		      <0x00 0x6f010000 0x00 0x1000>,   /* GICH */
40		      <0x00 0x6f020000 0x00 0x2000>;   /* GICV */
41
42		/* vcpumntirq: virtual CPU interface maintenance interrupt */
43		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
44
45		gic_its: msi-controller@1820000 {
46			compatible = "arm,gic-v3-its";
47			reg = <0x00 0x01820000 0x00 0x10000>;
48			socionext,synquacer-pre-its = <0x1000000 0x400000>;
49			msi-controller;
50			#msi-cells = <1>;
51		};
52	};
53
54	main_gpio_intr: interrupt-controller@a00000 {
55		compatible = "ti,sci-intr";
56		reg = <0x00 0x00a00000 0x00 0x800>;
57		ti,intr-trigger-type = <1>;
58		interrupt-controller;
59		interrupt-parent = <&gic500>;
60		#interrupt-cells = <1>;
61		ti,sci = <&sms>;
62		ti,sci-dev-id = <10>;
63		ti,interrupt-ranges = <8 360 56>;
64	};
65
66	main_pmx0: pinctrl@11c000 {
67		compatible = "pinctrl-single";
68		/* Proxy 0 addressing */
69		reg = <0x00 0x11c000 0x00 0x120>;
70		#pinctrl-cells = <1>;
71		pinctrl-single,register-width = <32>;
72		pinctrl-single,function-mask = <0xffffffff>;
73	};
74
75	main_crypto: crypto@4e00000 {
76		compatible = "ti,j721e-sa2ul";
77		reg = <0x00 0x4e00000 0x00 0x1200>;
78		power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>;
79		#address-cells = <2>;
80		#size-cells = <2>;
81		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
82
83		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
84				<&main_udmap 0x4a41>;
85		dma-names = "tx", "rx1", "rx2";
86
87		rng: rng@4e10000 {
88			compatible = "inside-secure,safexcel-eip76";
89			reg = <0x00 0x4e10000 0x00 0x7d>;
90			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
91		};
92	};
93
94	main_uart0: serial@2800000 {
95		compatible = "ti,j721e-uart", "ti,am654-uart";
96		reg = <0x00 0x02800000 0x00 0x200>;
97		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
98		current-speed = <115200>;
99		clocks = <&k3_clks 146 0>;
100		clock-names = "fclk";
101		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
102		status = "disabled";
103	};
104
105	main_uart1: serial@2810000 {
106		compatible = "ti,j721e-uart", "ti,am654-uart";
107		reg = <0x00 0x02810000 0x00 0x200>;
108		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
109		current-speed = <115200>;
110		clocks = <&k3_clks 388 0>;
111		clock-names = "fclk";
112		power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>;
113		status = "disabled";
114	};
115
116	main_uart2: serial@2820000 {
117		compatible = "ti,j721e-uart", "ti,am654-uart";
118		reg = <0x00 0x02820000 0x00 0x200>;
119		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
120		current-speed = <115200>;
121		clocks = <&k3_clks 389 0>;
122		clock-names = "fclk";
123		power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>;
124		status = "disabled";
125	};
126
127	main_uart3: serial@2830000 {
128		compatible = "ti,j721e-uart", "ti,am654-uart";
129		reg = <0x00 0x02830000 0x00 0x200>;
130		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
131		current-speed = <115200>;
132		clocks = <&k3_clks 390 0>;
133		clock-names = "fclk";
134		power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>;
135		status = "disabled";
136	};
137
138	main_uart4: serial@2840000 {
139		compatible = "ti,j721e-uart", "ti,am654-uart";
140		reg = <0x00 0x02840000 0x00 0x200>;
141		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
142		current-speed = <115200>;
143		clocks = <&k3_clks 391 0>;
144		clock-names = "fclk";
145		power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>;
146		status = "disabled";
147	};
148
149	main_uart5: serial@2850000 {
150		compatible = "ti,j721e-uart", "ti,am654-uart";
151		reg = <0x00 0x02850000 0x00 0x200>;
152		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
153		current-speed = <115200>;
154		clocks = <&k3_clks 392 0>;
155		clock-names = "fclk";
156		power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>;
157		status = "disabled";
158	};
159
160	main_uart6: serial@2860000 {
161		compatible = "ti,j721e-uart", "ti,am654-uart";
162		reg = <0x00 0x02860000 0x00 0x200>;
163		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
164		current-speed = <115200>;
165		clocks = <&k3_clks 393 0>;
166		clock-names = "fclk";
167		power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>;
168		status = "disabled";
169	};
170
171	main_uart7: serial@2870000 {
172		compatible = "ti,j721e-uart", "ti,am654-uart";
173		reg = <0x00 0x02870000 0x00 0x200>;
174		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
175		current-speed = <115200>;
176		clocks = <&k3_clks 394 0>;
177		clock-names = "fclk";
178		power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>;
179		status = "disabled";
180	};
181
182	main_uart8: serial@2880000 {
183		compatible = "ti,j721e-uart", "ti,am654-uart";
184		reg = <0x00 0x02880000 0x00 0x200>;
185		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
186		current-speed = <115200>;
187		clocks = <&k3_clks 395 0>;
188		clock-names = "fclk";
189		power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>;
190		status = "disabled";
191	};
192
193	main_uart9: serial@2890000 {
194		compatible = "ti,j721e-uart", "ti,am654-uart";
195		reg = <0x00 0x02890000 0x00 0x200>;
196		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
197		current-speed = <115200>;
198		clocks = <&k3_clks 396 0>;
199		clock-names = "fclk";
200		power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>;
201		status = "disabled";
202	};
203
204	main_gpio0: gpio@600000 {
205		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
206		reg = <0x00 0x00600000 0x00 0x100>;
207		gpio-controller;
208		#gpio-cells = <2>;
209		interrupt-parent = <&main_gpio_intr>;
210		interrupts = <145>, <146>, <147>, <148>, <149>;
211		interrupt-controller;
212		#interrupt-cells = <2>;
213		ti,ngpio = <66>;
214		ti,davinci-gpio-unbanked = <0>;
215		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
216		clocks = <&k3_clks 163 0>;
217		clock-names = "gpio";
218		status = "disabled";
219	};
220
221	main_gpio2: gpio@610000 {
222		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
223		reg = <0x00 0x00610000 0x00 0x100>;
224		gpio-controller;
225		#gpio-cells = <2>;
226		interrupt-parent = <&main_gpio_intr>;
227		interrupts = <154>, <155>, <156>, <157>, <158>;
228		interrupt-controller;
229		#interrupt-cells = <2>;
230		ti,ngpio = <66>;
231		ti,davinci-gpio-unbanked = <0>;
232		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
233		clocks = <&k3_clks 164 0>;
234		clock-names = "gpio";
235		status = "disabled";
236	};
237
238	main_gpio4: gpio@620000 {
239		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
240		reg = <0x00 0x00620000 0x00 0x100>;
241		gpio-controller;
242		#gpio-cells = <2>;
243		interrupt-parent = <&main_gpio_intr>;
244		interrupts = <163>, <164>, <165>, <166>, <167>;
245		interrupt-controller;
246		#interrupt-cells = <2>;
247		ti,ngpio = <66>;
248		ti,davinci-gpio-unbanked = <0>;
249		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
250		clocks = <&k3_clks 165 0>;
251		clock-names = "gpio";
252		status = "disabled";
253	};
254
255	main_gpio6: gpio@630000 {
256		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
257		reg = <0x00 0x00630000 0x00 0x100>;
258		gpio-controller;
259		#gpio-cells = <2>;
260		interrupt-parent = <&main_gpio_intr>;
261		interrupts = <172>, <173>, <174>, <175>, <176>;
262		interrupt-controller;
263		#interrupt-cells = <2>;
264		ti,ngpio = <66>;
265		ti,davinci-gpio-unbanked = <0>;
266		power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
267		clocks = <&k3_clks 166 0>;
268		clock-names = "gpio";
269		status = "disabled";
270	};
271
272	main_i2c0: i2c@2000000 {
273		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
274		reg = <0x00 0x02000000 0x00 0x100>;
275		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
276		#address-cells = <1>;
277		#size-cells = <0>;
278		clocks = <&k3_clks 270 2>;
279		clock-names = "fck";
280		power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
281		status = "disabled";
282	};
283
284	main_i2c1: i2c@2010000 {
285		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
286		reg = <0x00 0x02010000 0x00 0x100>;
287		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
288		#address-cells = <1>;
289		#size-cells = <0>;
290		clocks = <&k3_clks 271 2>;
291		clock-names = "fck";
292		power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
293		status = "disabled";
294	};
295
296	main_i2c2: i2c@2020000 {
297		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
298		reg = <0x00 0x02020000 0x00 0x100>;
299		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
300		#address-cells = <1>;
301		#size-cells = <0>;
302		clocks = <&k3_clks 272 2>;
303		clock-names = "fck";
304		power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
305		status = "disabled";
306	};
307
308	main_i2c3: i2c@2030000 {
309		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
310		reg = <0x00 0x02030000 0x00 0x100>;
311		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
312		#address-cells = <1>;
313		#size-cells = <0>;
314		clocks = <&k3_clks 273 2>;
315		clock-names = "fck";
316		power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
317		status = "disabled";
318	};
319
320	main_i2c4: i2c@2040000 {
321		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
322		reg = <0x00 0x02040000 0x00 0x100>;
323		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
324		#address-cells = <1>;
325		#size-cells = <0>;
326		clocks = <&k3_clks 274 2>;
327		clock-names = "fck";
328		power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
329		status = "disabled";
330	};
331
332	main_i2c5: i2c@2050000 {
333		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
334		reg = <0x00 0x02050000 0x00 0x100>;
335		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
336		#address-cells = <1>;
337		#size-cells = <0>;
338		clocks = <&k3_clks 275 2>;
339		clock-names = "fck";
340		power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
341		status = "disabled";
342	};
343
344	main_i2c6: i2c@2060000 {
345		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
346		reg = <0x00 0x02060000 0x00 0x100>;
347		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
348		#address-cells = <1>;
349		#size-cells = <0>;
350		clocks = <&k3_clks 276 2>;
351		clock-names = "fck";
352		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
353		status = "disabled";
354	};
355
356	main_sdhci0: mmc@4f80000 {
357		compatible = "ti,j721e-sdhci-8bit";
358		reg = <0x00 0x04f80000 0x00 0x1000>,
359		      <0x00 0x04f88000 0x00 0x400>;
360		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
361		power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
362		clocks = <&k3_clks 140 1>, <&k3_clks 140 2>;
363		clock-names =  "clk_ahb", "clk_xin";
364		assigned-clocks = <&k3_clks 140 2>;
365		assigned-clock-parents = <&k3_clks 140 3>;
366		bus-width = <8>;
367		ti,otap-del-sel-legacy = <0x0>;
368		ti,otap-del-sel-mmc-hs = <0x0>;
369		ti,otap-del-sel-ddr52 = <0x6>;
370		ti,otap-del-sel-hs200 = <0x8>;
371		ti,otap-del-sel-hs400 = <0x5>;
372		ti,itap-del-sel-legacy = <0x10>;
373		ti,itap-del-sel-mmc-hs = <0xa>;
374		ti,strobe-sel = <0x77>;
375		ti,clkbuf-sel = <0x7>;
376		ti,trm-icp = <0x8>;
377		mmc-ddr-1_8v;
378		mmc-hs200-1_8v;
379		mmc-hs400-1_8v;
380		dma-coherent;
381		no-1-8-v;
382		status = "disabled";
383	};
384
385	main_sdhci1: mmc@4fb0000 {
386		compatible = "ti,j721e-sdhci-4bit";
387		reg = <0x00 0x04fb0000 0x00 0x1000>,
388		      <0x00 0x04fb8000 0x00 0x400>;
389		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
390		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
391		clocks = <&k3_clks 141 3>, <&k3_clks 141 4>;
392		clock-names =  "clk_ahb", "clk_xin";
393		assigned-clocks = <&k3_clks 141 4>;
394		assigned-clock-parents = <&k3_clks 141 5>;
395		bus-width = <4>;
396		ti,otap-del-sel-legacy = <0x0>;
397		ti,otap-del-sel-sd-hs = <0x0>;
398		ti,otap-del-sel-sdr12 = <0xf>;
399		ti,otap-del-sel-sdr25 = <0xf>;
400		ti,otap-del-sel-sdr50 = <0xc>;
401		ti,otap-del-sel-sdr104 = <0x5>;
402		ti,otap-del-sel-ddr50 = <0xc>;
403		ti,itap-del-sel-legacy = <0x0>;
404		ti,itap-del-sel-sd-hs = <0x0>;
405		ti,itap-del-sel-sdr12 = <0x0>;
406		ti,itap-del-sel-sdr25 = <0x0>;
407		ti,clkbuf-sel = <0x7>;
408		ti,trm-icp = <0x8>;
409		dma-coherent;
410		sdhci-caps-mask = <0x00000003 0x00000000>;
411		no-1-8-v;
412		status = "disabled";
413	};
414
415	main_navss: bus@30000000 {
416		compatible = "simple-bus";
417		#address-cells = <2>;
418		#size-cells = <2>;
419		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
420		ti,sci-dev-id = <280>;
421		dma-coherent;
422		dma-ranges;
423
424		main_navss_intr: interrupt-controller@310e0000 {
425			compatible = "ti,sci-intr";
426			reg = <0x00 0x310e0000 0x00 0x4000>;
427			ti,intr-trigger-type = <4>;
428			interrupt-controller;
429			interrupt-parent = <&gic500>;
430			#interrupt-cells = <1>;
431			ti,sci = <&sms>;
432			ti,sci-dev-id = <283>;
433			ti,interrupt-ranges = <0 64 64>,
434					      <64 448 64>,
435					      <128 672 64>;
436		};
437
438		main_udmass_inta: msi-controller@33d00000 {
439			compatible = "ti,sci-inta";
440			reg = <0x00 0x33d00000 0x00 0x100000>;
441			interrupt-controller;
442			#interrupt-cells = <0>;
443			interrupt-parent = <&main_navss_intr>;
444			msi-controller;
445			ti,sci = <&sms>;
446			ti,sci-dev-id = <321>;
447			ti,interrupt-ranges = <0 0 256>;
448		};
449
450		secure_proxy_main: mailbox@32c00000 {
451			compatible = "ti,am654-secure-proxy";
452			#mbox-cells = <1>;
453			reg-names = "target_data", "rt", "scfg";
454			reg = <0x00 0x32c00000 0x00 0x100000>,
455			      <0x00 0x32400000 0x00 0x100000>,
456			      <0x00 0x32800000 0x00 0x100000>;
457			interrupt-names = "rx_011";
458			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
459		};
460
461		hwspinlock: hwlock@30e00000 {
462			compatible = "ti,am654-hwspinlock";
463			reg = <0x00 0x30e00000 0x00 0x1000>;
464			#hwlock-cells = <1>;
465		};
466
467		mailbox0_cluster0: mailbox@31f80000 {
468			compatible = "ti,am654-mailbox";
469			reg = <0x00 0x31f80000 0x00 0x200>;
470			#mbox-cells = <1>;
471			ti,mbox-num-users = <4>;
472			ti,mbox-num-fifos = <16>;
473			interrupt-parent = <&main_navss_intr>;
474			status = "disabled";
475		};
476
477		mailbox0_cluster1: mailbox@31f81000 {
478			compatible = "ti,am654-mailbox";
479			reg = <0x00 0x31f81000 0x00 0x200>;
480			#mbox-cells = <1>;
481			ti,mbox-num-users = <4>;
482			ti,mbox-num-fifos = <16>;
483			interrupt-parent = <&main_navss_intr>;
484			status = "disabled";
485		};
486
487		mailbox0_cluster2: mailbox@31f82000 {
488			compatible = "ti,am654-mailbox";
489			reg = <0x00 0x31f82000 0x00 0x200>;
490			#mbox-cells = <1>;
491			ti,mbox-num-users = <4>;
492			ti,mbox-num-fifos = <16>;
493			interrupt-parent = <&main_navss_intr>;
494			status = "disabled";
495		};
496
497		mailbox0_cluster3: mailbox@31f83000 {
498			compatible = "ti,am654-mailbox";
499			reg = <0x00 0x31f83000 0x00 0x200>;
500			#mbox-cells = <1>;
501			ti,mbox-num-users = <4>;
502			ti,mbox-num-fifos = <16>;
503			interrupt-parent = <&main_navss_intr>;
504			status = "disabled";
505		};
506
507		mailbox0_cluster4: mailbox@31f84000 {
508			compatible = "ti,am654-mailbox";
509			reg = <0x00 0x31f84000 0x00 0x200>;
510			#mbox-cells = <1>;
511			ti,mbox-num-users = <4>;
512			ti,mbox-num-fifos = <16>;
513			interrupt-parent = <&main_navss_intr>;
514			status = "disabled";
515		};
516
517		mailbox0_cluster5: mailbox@31f85000 {
518			compatible = "ti,am654-mailbox";
519			reg = <0x00 0x31f85000 0x00 0x200>;
520			#mbox-cells = <1>;
521			ti,mbox-num-users = <4>;
522			ti,mbox-num-fifos = <16>;
523			interrupt-parent = <&main_navss_intr>;
524			status = "disabled";
525		};
526
527		mailbox0_cluster6: mailbox@31f86000 {
528			compatible = "ti,am654-mailbox";
529			reg = <0x00 0x31f86000 0x00 0x200>;
530			#mbox-cells = <1>;
531			ti,mbox-num-users = <4>;
532			ti,mbox-num-fifos = <16>;
533			interrupt-parent = <&main_navss_intr>;
534			status = "disabled";
535		};
536
537		mailbox0_cluster7: mailbox@31f87000 {
538			compatible = "ti,am654-mailbox";
539			reg = <0x00 0x31f87000 0x00 0x200>;
540			#mbox-cells = <1>;
541			ti,mbox-num-users = <4>;
542			ti,mbox-num-fifos = <16>;
543			interrupt-parent = <&main_navss_intr>;
544			status = "disabled";
545		};
546
547		mailbox0_cluster8: mailbox@31f88000 {
548			compatible = "ti,am654-mailbox";
549			reg = <0x00 0x31f88000 0x00 0x200>;
550			#mbox-cells = <1>;
551			ti,mbox-num-users = <4>;
552			ti,mbox-num-fifos = <16>;
553			interrupt-parent = <&main_navss_intr>;
554			status = "disabled";
555		};
556
557		mailbox0_cluster9: mailbox@31f89000 {
558			compatible = "ti,am654-mailbox";
559			reg = <0x00 0x31f89000 0x00 0x200>;
560			#mbox-cells = <1>;
561			ti,mbox-num-users = <4>;
562			ti,mbox-num-fifos = <16>;
563			interrupt-parent = <&main_navss_intr>;
564			status = "disabled";
565		};
566
567		mailbox0_cluster10: mailbox@31f8a000 {
568			compatible = "ti,am654-mailbox";
569			reg = <0x00 0x31f8a000 0x00 0x200>;
570			#mbox-cells = <1>;
571			ti,mbox-num-users = <4>;
572			ti,mbox-num-fifos = <16>;
573			interrupt-parent = <&main_navss_intr>;
574			status = "disabled";
575		};
576
577		mailbox0_cluster11: mailbox@31f8b000 {
578			compatible = "ti,am654-mailbox";
579			reg = <0x00 0x31f8b000 0x00 0x200>;
580			#mbox-cells = <1>;
581			ti,mbox-num-users = <4>;
582			ti,mbox-num-fifos = <16>;
583			interrupt-parent = <&main_navss_intr>;
584			status = "disabled";
585		};
586
587		mailbox1_cluster0: mailbox@31f90000 {
588			compatible = "ti,am654-mailbox";
589			reg = <0x00 0x31f90000 0x00 0x200>;
590			#mbox-cells = <1>;
591			ti,mbox-num-users = <4>;
592			ti,mbox-num-fifos = <16>;
593			interrupt-parent = <&main_navss_intr>;
594			status = "disabled";
595		};
596
597		mailbox1_cluster1: mailbox@31f91000 {
598			compatible = "ti,am654-mailbox";
599			reg = <0x00 0x31f91000 0x00 0x200>;
600			#mbox-cells = <1>;
601			ti,mbox-num-users = <4>;
602			ti,mbox-num-fifos = <16>;
603			interrupt-parent = <&main_navss_intr>;
604			status = "disabled";
605		};
606
607		mailbox1_cluster2: mailbox@31f92000 {
608			compatible = "ti,am654-mailbox";
609			reg = <0x00 0x31f92000 0x00 0x200>;
610			#mbox-cells = <1>;
611			ti,mbox-num-users = <4>;
612			ti,mbox-num-fifos = <16>;
613			interrupt-parent = <&main_navss_intr>;
614			status = "disabled";
615		};
616
617		mailbox1_cluster3: mailbox@31f93000 {
618			compatible = "ti,am654-mailbox";
619			reg = <0x00 0x31f93000 0x00 0x200>;
620			#mbox-cells = <1>;
621			ti,mbox-num-users = <4>;
622			ti,mbox-num-fifos = <16>;
623			interrupt-parent = <&main_navss_intr>;
624			status = "disabled";
625		};
626
627		mailbox1_cluster4: mailbox@31f94000 {
628			compatible = "ti,am654-mailbox";
629			reg = <0x00 0x31f94000 0x00 0x200>;
630			#mbox-cells = <1>;
631			ti,mbox-num-users = <4>;
632			ti,mbox-num-fifos = <16>;
633			interrupt-parent = <&main_navss_intr>;
634			status = "disabled";
635		};
636
637		mailbox1_cluster5: mailbox@31f95000 {
638			compatible = "ti,am654-mailbox";
639			reg = <0x00 0x31f95000 0x00 0x200>;
640			#mbox-cells = <1>;
641			ti,mbox-num-users = <4>;
642			ti,mbox-num-fifos = <16>;
643			interrupt-parent = <&main_navss_intr>;
644			status = "disabled";
645		};
646
647		mailbox1_cluster6: mailbox@31f96000 {
648			compatible = "ti,am654-mailbox";
649			reg = <0x00 0x31f96000 0x00 0x200>;
650			#mbox-cells = <1>;
651			ti,mbox-num-users = <4>;
652			ti,mbox-num-fifos = <16>;
653			interrupt-parent = <&main_navss_intr>;
654			status = "disabled";
655		};
656
657		mailbox1_cluster7: mailbox@31f97000 {
658			compatible = "ti,am654-mailbox";
659			reg = <0x00 0x31f97000 0x00 0x200>;
660			#mbox-cells = <1>;
661			ti,mbox-num-users = <4>;
662			ti,mbox-num-fifos = <16>;
663			interrupt-parent = <&main_navss_intr>;
664			status = "disabled";
665		};
666
667		mailbox1_cluster8: mailbox@31f98000 {
668			compatible = "ti,am654-mailbox";
669			reg = <0x00 0x31f98000 0x00 0x200>;
670			#mbox-cells = <1>;
671			ti,mbox-num-users = <4>;
672			ti,mbox-num-fifos = <16>;
673			interrupt-parent = <&main_navss_intr>;
674			status = "disabled";
675		};
676
677		mailbox1_cluster9: mailbox@31f99000 {
678			compatible = "ti,am654-mailbox";
679			reg = <0x00 0x31f99000 0x00 0x200>;
680			#mbox-cells = <1>;
681			ti,mbox-num-users = <4>;
682			ti,mbox-num-fifos = <16>;
683			interrupt-parent = <&main_navss_intr>;
684			status = "disabled";
685		};
686
687		mailbox1_cluster10: mailbox@31f9a000 {
688			compatible = "ti,am654-mailbox";
689			reg = <0x00 0x31f9a000 0x00 0x200>;
690			#mbox-cells = <1>;
691			ti,mbox-num-users = <4>;
692			ti,mbox-num-fifos = <16>;
693			interrupt-parent = <&main_navss_intr>;
694			status = "disabled";
695		};
696
697		mailbox1_cluster11: mailbox@31f9b000 {
698			compatible = "ti,am654-mailbox";
699			reg = <0x00 0x31f9b000 0x00 0x200>;
700			#mbox-cells = <1>;
701			ti,mbox-num-users = <4>;
702			ti,mbox-num-fifos = <16>;
703			interrupt-parent = <&main_navss_intr>;
704			status = "disabled";
705		};
706
707		main_ringacc: ringacc@3c000000 {
708			compatible = "ti,am654-navss-ringacc";
709			reg = <0x00 0x3c000000 0x00 0x400000>,
710			      <0x00 0x38000000 0x00 0x400000>,
711			      <0x00 0x31120000 0x00 0x100>,
712			      <0x00 0x33000000 0x00 0x40000>;
713			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
714			ti,num-rings = <1024>;
715			ti,sci-rm-range-gp-rings = <0x1>;
716			ti,sci = <&sms>;
717			ti,sci-dev-id = <315>;
718			msi-parent = <&main_udmass_inta>;
719		};
720
721		main_udmap: dma-controller@31150000 {
722			compatible = "ti,j721e-navss-main-udmap";
723			reg = <0x00 0x31150000 0x00 0x100>,
724			      <0x00 0x34000000 0x00 0x80000>,
725			      <0x00 0x35000000 0x00 0x200000>;
726			reg-names = "gcfg", "rchanrt", "tchanrt";
727			msi-parent = <&main_udmass_inta>;
728			#dma-cells = <1>;
729
730			ti,sci = <&sms>;
731			ti,sci-dev-id = <319>;
732			ti,ringacc = <&main_ringacc>;
733
734			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
735						<0x0f>, /* TX_HCHAN */
736						<0x10>; /* TX_UHCHAN */
737			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
738						<0x0b>, /* RX_HCHAN */
739						<0x0c>; /* RX_UHCHAN */
740			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
741		};
742
743		cpts@310d0000 {
744			compatible = "ti,j721e-cpts";
745			reg = <0x00 0x310d0000 0x00 0x400>;
746			reg-names = "cpts";
747			clocks = <&k3_clks 282 0>;
748			clock-names = "cpts";
749			assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */
750			assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */
751			interrupts-extended = <&main_navss_intr 391>;
752			interrupt-names = "cpts";
753			ti,cpts-periodic-outputs = <6>;
754			ti,cpts-ext-ts-inputs = <8>;
755		};
756	};
757
758	main_mcan0: can@2701000 {
759		compatible = "bosch,m_can";
760		reg = <0x00 0x02701000 0x00 0x200>,
761		      <0x00 0x02708000 0x00 0x8000>;
762		reg-names = "m_can", "message_ram";
763		power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>;
764		clocks = <&k3_clks 245 6>, <&k3_clks 245 1>;
765		clock-names = "hclk", "cclk";
766		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
767			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
768		interrupt-names = "int0", "int1";
769		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
770		status = "disabled";
771	};
772
773	main_mcan1: can@2711000 {
774		compatible = "bosch,m_can";
775		reg = <0x00 0x02711000 0x00 0x200>,
776		      <0x00 0x02718000 0x00 0x8000>;
777		reg-names = "m_can", "message_ram";
778		power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>;
779		clocks = <&k3_clks 246 6>, <&k3_clks 246 1>;
780		clock-names = "hclk", "cclk";
781		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
782			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
783		interrupt-names = "int0", "int1";
784		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
785		status = "disabled";
786	};
787
788	main_mcan2: can@2721000 {
789		compatible = "bosch,m_can";
790		reg = <0x00 0x02721000 0x00 0x200>,
791		      <0x00 0x02728000 0x00 0x8000>;
792		reg-names = "m_can", "message_ram";
793		power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
794		clocks = <&k3_clks 247 6>, <&k3_clks 247 1>;
795		clock-names = "hclk", "cclk";
796		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
797			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
798		interrupt-names = "int0", "int1";
799		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
800		status = "disabled";
801	};
802
803	main_mcan3: can@2731000 {
804		compatible = "bosch,m_can";
805		reg = <0x00 0x02731000 0x00 0x200>,
806		      <0x00 0x02738000 0x00 0x8000>;
807		reg-names = "m_can", "message_ram";
808		power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
809		clocks = <&k3_clks 248 6>, <&k3_clks 248 1>;
810		clock-names = "hclk", "cclk";
811		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
812			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
813		interrupt-names = "int0", "int1";
814		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
815		status = "disabled";
816	};
817
818	main_mcan4: can@2741000 {
819		compatible = "bosch,m_can";
820		reg = <0x00 0x02741000 0x00 0x200>,
821		      <0x00 0x02748000 0x00 0x8000>;
822		reg-names = "m_can", "message_ram";
823		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
824		clocks = <&k3_clks 249 6>, <&k3_clks 249 1>;
825		clock-names = "hclk", "cclk";
826		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
827			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
828		interrupt-names = "int0", "int1";
829		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
830		status = "disabled";
831	};
832
833	main_mcan5: can@2751000 {
834		compatible = "bosch,m_can";
835		reg = <0x00 0x02751000 0x00 0x200>,
836		      <0x00 0x02758000 0x00 0x8000>;
837		reg-names = "m_can", "message_ram";
838		power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>;
839		clocks = <&k3_clks 250 6>, <&k3_clks 250 1>;
840		clock-names = "hclk", "cclk";
841		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
842			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
843		interrupt-names = "int0", "int1";
844		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
845		status = "disabled";
846	};
847
848	main_mcan6: can@2761000 {
849		compatible = "bosch,m_can";
850		reg = <0x00 0x02761000 0x00 0x200>,
851		      <0x00 0x02768000 0x00 0x8000>;
852		reg-names = "m_can", "message_ram";
853		power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
854		clocks = <&k3_clks 251 6>, <&k3_clks 251 1>;
855		clock-names = "hclk", "cclk";
856		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
857			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
858		interrupt-names = "int0", "int1";
859		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
860		status = "disabled";
861	};
862
863	main_mcan7: can@2771000 {
864		compatible = "bosch,m_can";
865		reg = <0x00 0x02771000 0x00 0x200>,
866		      <0x00 0x02778000 0x00 0x8000>;
867		reg-names = "m_can", "message_ram";
868		power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
869		clocks = <&k3_clks 252 6>, <&k3_clks 252 1>;
870		clock-names = "hclk", "cclk";
871		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
872			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
873		interrupt-names = "int0", "int1";
874		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
875		status = "disabled";
876	};
877
878	main_mcan8: can@2781000 {
879		compatible = "bosch,m_can";
880		reg = <0x00 0x02781000 0x00 0x200>,
881		      <0x00 0x02788000 0x00 0x8000>;
882		reg-names = "m_can", "message_ram";
883		power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
884		clocks = <&k3_clks 253 6>, <&k3_clks 253 1>;
885		clock-names = "hclk", "cclk";
886		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
887			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
888		interrupt-names = "int0", "int1";
889		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
890		status = "disabled";
891	};
892
893	main_mcan9: can@2791000 {
894		compatible = "bosch,m_can";
895		reg = <0x00 0x02791000 0x00 0x200>,
896		      <0x00 0x02798000 0x00 0x8000>;
897		reg-names = "m_can", "message_ram";
898		power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
899		clocks = <&k3_clks 254 6>, <&k3_clks 254 1>;
900		clock-names = "hclk", "cclk";
901		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
902			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
903		interrupt-names = "int0", "int1";
904		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
905		status = "disabled";
906	};
907
908	main_mcan10: can@27a1000 {
909		compatible = "bosch,m_can";
910		reg = <0x00 0x027a1000 0x00 0x200>,
911		      <0x00 0x027a8000 0x00 0x8000>;
912		reg-names = "m_can", "message_ram";
913		power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
914		clocks = <&k3_clks 255 6>, <&k3_clks 255 1>;
915		clock-names = "hclk", "cclk";
916		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
917			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
918		interrupt-names = "int0", "int1";
919		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
920		status = "disabled";
921	};
922
923	main_mcan11: can@27b1000 {
924		compatible = "bosch,m_can";
925		reg = <0x00 0x027b1000 0x00 0x200>,
926		      <0x00 0x027b8000 0x00 0x8000>;
927		reg-names = "m_can", "message_ram";
928		power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
929		clocks = <&k3_clks 256 6>, <&k3_clks 256 1>;
930		clock-names = "hclk", "cclk";
931		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
932			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
933		interrupt-names = "int0", "int1";
934		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
935		status = "disabled";
936	};
937
938	main_mcan12: can@27c1000 {
939		compatible = "bosch,m_can";
940		reg = <0x00 0x027c1000 0x00 0x200>,
941		      <0x00 0x027c8000 0x00 0x8000>;
942		reg-names = "m_can", "message_ram";
943		power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
944		clocks = <&k3_clks 257 6>, <&k3_clks 257 1>;
945		clock-names = "hclk", "cclk";
946		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
947			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
948		interrupt-names = "int0", "int1";
949		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
950		status = "disabled";
951	};
952
953	main_mcan13: can@27d1000 {
954		compatible = "bosch,m_can";
955		reg = <0x00 0x027d1000 0x00 0x200>,
956		      <0x00 0x027d8000 0x00 0x8000>;
957		reg-names = "m_can", "message_ram";
958		power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
959		clocks = <&k3_clks 258 6>, <&k3_clks 258 1>;
960		clock-names = "hclk", "cclk";
961		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
962			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
963		interrupt-names = "int0", "int1";
964		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
965		status = "disabled";
966	};
967
968	main_mcan14: can@2681000 {
969		compatible = "bosch,m_can";
970		reg = <0x00 0x02681000 0x00 0x200>,
971		      <0x00 0x02688000 0x00 0x8000>;
972		reg-names = "m_can", "message_ram";
973		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
974		clocks = <&k3_clks 259 6>, <&k3_clks 259 1>;
975		clock-names = "hclk", "cclk";
976		interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
977			     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
978		interrupt-names = "int0", "int1";
979		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
980		status = "disabled";
981	};
982
983	main_mcan15: can@2691000 {
984		compatible = "bosch,m_can";
985		reg = <0x00 0x02691000 0x00 0x200>,
986		      <0x00 0x02698000 0x00 0x8000>;
987		reg-names = "m_can", "message_ram";
988		power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
989		clocks = <&k3_clks 260 6>, <&k3_clks 260 1>;
990		clock-names = "hclk", "cclk";
991		interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
992			     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
993		interrupt-names = "int0", "int1";
994		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
995		status = "disabled";
996	};
997
998	main_mcan16: can@26a1000 {
999		compatible = "bosch,m_can";
1000		reg = <0x00 0x026a1000 0x00 0x200>,
1001		      <0x00 0x026a8000 0x00 0x8000>;
1002		reg-names = "m_can", "message_ram";
1003		power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
1004		clocks = <&k3_clks 261 6>, <&k3_clks 261 1>;
1005		clock-names = "hclk", "cclk";
1006		interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1007			     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1008		interrupt-names = "int0", "int1";
1009		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1010		status = "disabled";
1011	};
1012
1013	main_mcan17: can@26b1000 {
1014		compatible = "bosch,m_can";
1015		reg = <0x00 0x026b1000 0x00 0x200>,
1016		      <0x00 0x026b8000 0x00 0x8000>;
1017		reg-names = "m_can", "message_ram";
1018		power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
1019		clocks = <&k3_clks 262 6>, <&k3_clks 262 1>;
1020		clock-names = "hclk", "cclk";
1021		interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1022			     <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1023		interrupt-names = "int0", "int1";
1024		bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1025		status = "disabled";
1026	};
1027
1028	main_spi0: spi@2100000 {
1029		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1030		reg = <0x00 0x02100000 0x00 0x400>;
1031		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1032		#address-cells = <1>;
1033		#size-cells = <0>;
1034		power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
1035		clocks = <&k3_clks 376 1>;
1036		status = "disabled";
1037	};
1038
1039	main_spi1: spi@2110000 {
1040		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1041		reg = <0x00 0x02110000 0x00 0x400>;
1042		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1043		#address-cells = <1>;
1044		#size-cells = <0>;
1045		power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
1046		clocks = <&k3_clks 377 1>;
1047		status = "disabled";
1048	};
1049
1050	main_spi2: spi@2120000 {
1051		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1052		reg = <0x00 0x02120000 0x00 0x400>;
1053		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1054		#address-cells = <1>;
1055		#size-cells = <0>;
1056		power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
1057		clocks = <&k3_clks 378 1>;
1058		status = "disabled";
1059	};
1060
1061	main_spi3: spi@2130000 {
1062		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1063		reg = <0x00 0x02130000 0x00 0x400>;
1064		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1065		#address-cells = <1>;
1066		#size-cells = <0>;
1067		power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
1068		clocks = <&k3_clks 379 1>;
1069		status = "disabled";
1070	};
1071
1072	main_spi4: spi@2140000 {
1073		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1074		reg = <0x00 0x02140000 0x00 0x400>;
1075		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1076		#address-cells = <1>;
1077		#size-cells = <0>;
1078		power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
1079		clocks = <&k3_clks 380 1>;
1080		status = "disabled";
1081	};
1082
1083	main_spi5: spi@2150000 {
1084		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1085		reg = <0x00 0x02150000 0x00 0x400>;
1086		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1087		#address-cells = <1>;
1088		#size-cells = <0>;
1089		power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
1090		clocks = <&k3_clks 381 1>;
1091		status = "disabled";
1092	};
1093
1094	main_spi6: spi@2160000 {
1095		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1096		reg = <0x00 0x02160000 0x00 0x400>;
1097		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1098		#address-cells = <1>;
1099		#size-cells = <0>;
1100		power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
1101		clocks = <&k3_clks 382 1>;
1102		status = "disabled";
1103	};
1104
1105	main_spi7: spi@2170000 {
1106		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1107		reg = <0x00 0x02170000 0x00 0x400>;
1108		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1109		#address-cells = <1>;
1110		#size-cells = <0>;
1111		power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
1112		clocks = <&k3_clks 383 1>;
1113		status = "disabled";
1114	};
1115};
1116