1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 msmc_ram: sram@70000000 { 25 compatible = "mmio-sram"; 26 reg = <0x00 0x70000000 0x00 0x800000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0x00 0x00 0x70000000 0x800000>; 30 31 atf-sram@0 { 32 reg = <0x00 0x20000>; 33 }; 34 35 tifs-sram@1f0000 { 36 reg = <0x1f0000 0x10000>; 37 }; 38 39 l3cache-sram@200000 { 40 reg = <0x200000 0x200000>; 41 }; 42 }; 43 44 scm_conf: bus@100000 { 45 compatible = "simple-bus"; 46 reg = <0x00 0x00100000 0x00 0x1c000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x00 0x00 0x00100000 0x1c000>; 50 51 serdes_ln_ctrl: mux-controller@4080 { 52 compatible = "reg-mux"; 53 reg = <0x00004080 0x30>; 54 #mux-control-cells = <1>; 55 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 56 <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ 57 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 58 <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ 59 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 60 <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ 61 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 62 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 63 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 64 <J784S4_SERDES0_LANE3_USB>, 65 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 66 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 67 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 68 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 69 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 70 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 71 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 72 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 73 <J784S4_SERDES4_LANE0_EDP_LANE0>, 74 <J784S4_SERDES4_LANE1_EDP_LANE1>, 75 <J784S4_SERDES4_LANE2_EDP_LANE2>, 76 <J784S4_SERDES4_LANE3_EDP_LANE3>; 77 }; 78 }; 79 80 gic500: interrupt-controller@1800000 { 81 compatible = "arm,gic-v3"; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 #interrupt-cells = <3>; 86 interrupt-controller; 87 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 88 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 89 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 90 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 91 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 92 93 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 94 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 95 96 gic_its: msi-controller@1820000 { 97 compatible = "arm,gic-v3-its"; 98 reg = <0x00 0x01820000 0x00 0x10000>; 99 socionext,synquacer-pre-its = <0x1000000 0x400000>; 100 msi-controller; 101 #msi-cells = <1>; 102 }; 103 }; 104 105 main_gpio_intr: interrupt-controller@a00000 { 106 compatible = "ti,sci-intr"; 107 reg = <0x00 0x00a00000 0x00 0x800>; 108 ti,intr-trigger-type = <1>; 109 interrupt-controller; 110 interrupt-parent = <&gic500>; 111 #interrupt-cells = <1>; 112 ti,sci = <&sms>; 113 ti,sci-dev-id = <10>; 114 ti,interrupt-ranges = <8 392 56>; 115 }; 116 117 main_pmx0: pinctrl@11c000 { 118 compatible = "pinctrl-single"; 119 /* Proxy 0 addressing */ 120 reg = <0x00 0x11c000 0x00 0x120>; 121 #pinctrl-cells = <1>; 122 pinctrl-single,register-width = <32>; 123 pinctrl-single,function-mask = <0xffffffff>; 124 }; 125 126 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 127 main_timerio_input: pinctrl@104200 { 128 compatible = "pinctrl-single"; 129 reg = <0x00 0x104200 0x00 0x50>; 130 #pinctrl-cells = <1>; 131 pinctrl-single,register-width = <32>; 132 pinctrl-single,function-mask = <0x00000007>; 133 }; 134 135 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 136 main_timerio_output: pinctrl@104280 { 137 compatible = "pinctrl-single"; 138 reg = <0x00 0x104280 0x00 0x20>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0x0000001f>; 142 }; 143 144 main_crypto: crypto@4e00000 { 145 compatible = "ti,j721e-sa2ul"; 146 reg = <0x00 0x4e00000 0x00 0x1200>; 147 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 151 152 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 153 <&main_udmap 0x4a41>; 154 dma-names = "tx", "rx1", "rx2"; 155 156 rng: rng@4e10000 { 157 compatible = "inside-secure,safexcel-eip76"; 158 reg = <0x00 0x4e10000 0x00 0x7d>; 159 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 }; 162 163 main_timer0: timer@2400000 { 164 compatible = "ti,am654-timer"; 165 reg = <0x00 0x2400000 0x00 0x400>; 166 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&k3_clks 97 2>; 168 clock-names = "fck"; 169 assigned-clocks = <&k3_clks 97 2>; 170 assigned-clock-parents = <&k3_clks 97 3>; 171 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 172 ti,timer-pwm; 173 }; 174 175 main_timer1: timer@2410000 { 176 compatible = "ti,am654-timer"; 177 reg = <0x00 0x2410000 0x00 0x400>; 178 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&k3_clks 98 2>; 180 clock-names = "fck"; 181 assigned-clocks = <&k3_clks 98 2>; 182 assigned-clock-parents = <&k3_clks 98 3>; 183 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 184 ti,timer-pwm; 185 }; 186 187 main_timer2: timer@2420000 { 188 compatible = "ti,am654-timer"; 189 reg = <0x00 0x2420000 0x00 0x400>; 190 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&k3_clks 99 2>; 192 clock-names = "fck"; 193 assigned-clocks = <&k3_clks 99 2>; 194 assigned-clock-parents = <&k3_clks 99 3>; 195 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 196 ti,timer-pwm; 197 }; 198 199 main_timer3: timer@2430000 { 200 compatible = "ti,am654-timer"; 201 reg = <0x00 0x2430000 0x00 0x400>; 202 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&k3_clks 100 2>; 204 clock-names = "fck"; 205 assigned-clocks = <&k3_clks 100 2>; 206 assigned-clock-parents = <&k3_clks 100 3>; 207 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 208 ti,timer-pwm; 209 }; 210 211 main_timer4: timer@2440000 { 212 compatible = "ti,am654-timer"; 213 reg = <0x00 0x2440000 0x00 0x400>; 214 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&k3_clks 101 2>; 216 clock-names = "fck"; 217 assigned-clocks = <&k3_clks 101 2>; 218 assigned-clock-parents = <&k3_clks 101 3>; 219 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 220 ti,timer-pwm; 221 }; 222 223 main_timer5: timer@2450000 { 224 compatible = "ti,am654-timer"; 225 reg = <0x00 0x2450000 0x00 0x400>; 226 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&k3_clks 102 2>; 228 clock-names = "fck"; 229 assigned-clocks = <&k3_clks 102 2>; 230 assigned-clock-parents = <&k3_clks 102 3>; 231 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 232 ti,timer-pwm; 233 }; 234 235 main_timer6: timer@2460000 { 236 compatible = "ti,am654-timer"; 237 reg = <0x00 0x2460000 0x00 0x400>; 238 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&k3_clks 103 2>; 240 clock-names = "fck"; 241 assigned-clocks = <&k3_clks 103 2>; 242 assigned-clock-parents = <&k3_clks 103 3>; 243 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 244 ti,timer-pwm; 245 }; 246 247 main_timer7: timer@2470000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x2470000 0x00 0x400>; 250 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 104 2>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 104 2>; 254 assigned-clock-parents = <&k3_clks 104 3>; 255 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 }; 258 259 main_timer8: timer@2480000 { 260 compatible = "ti,am654-timer"; 261 reg = <0x00 0x2480000 0x00 0x400>; 262 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&k3_clks 105 2>; 264 clock-names = "fck"; 265 assigned-clocks = <&k3_clks 105 2>; 266 assigned-clock-parents = <&k3_clks 105 3>; 267 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 268 ti,timer-pwm; 269 }; 270 271 main_timer9: timer@2490000 { 272 compatible = "ti,am654-timer"; 273 reg = <0x00 0x2490000 0x00 0x400>; 274 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 106 2>; 276 clock-names = "fck"; 277 assigned-clocks = <&k3_clks 106 2>; 278 assigned-clock-parents = <&k3_clks 106 3>; 279 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 280 ti,timer-pwm; 281 }; 282 283 main_timer10: timer@24a0000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x24a0000 0x00 0x400>; 286 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 107 2>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 107 2>; 290 assigned-clock-parents = <&k3_clks 107 3>; 291 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 }; 294 295 main_timer11: timer@24b0000 { 296 compatible = "ti,am654-timer"; 297 reg = <0x00 0x24b0000 0x00 0x400>; 298 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&k3_clks 108 2>; 300 clock-names = "fck"; 301 assigned-clocks = <&k3_clks 108 2>; 302 assigned-clock-parents = <&k3_clks 108 3>; 303 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 304 ti,timer-pwm; 305 }; 306 307 main_timer12: timer@24c0000 { 308 compatible = "ti,am654-timer"; 309 reg = <0x00 0x24c0000 0x00 0x400>; 310 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 109 2>; 312 clock-names = "fck"; 313 assigned-clocks = <&k3_clks 109 2>; 314 assigned-clock-parents = <&k3_clks 109 3>; 315 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 316 ti,timer-pwm; 317 }; 318 319 main_timer13: timer@24d0000 { 320 compatible = "ti,am654-timer"; 321 reg = <0x00 0x24d0000 0x00 0x400>; 322 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&k3_clks 110 2>; 324 clock-names = "fck"; 325 assigned-clocks = <&k3_clks 110 2>; 326 assigned-clock-parents = <&k3_clks 110 3>; 327 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 328 ti,timer-pwm; 329 }; 330 331 main_timer14: timer@24e0000 { 332 compatible = "ti,am654-timer"; 333 reg = <0x00 0x24e0000 0x00 0x400>; 334 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&k3_clks 111 2>; 336 clock-names = "fck"; 337 assigned-clocks = <&k3_clks 111 2>; 338 assigned-clock-parents = <&k3_clks 111 3>; 339 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 340 ti,timer-pwm; 341 }; 342 343 main_timer15: timer@24f0000 { 344 compatible = "ti,am654-timer"; 345 reg = <0x00 0x24f0000 0x00 0x400>; 346 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&k3_clks 112 2>; 348 clock-names = "fck"; 349 assigned-clocks = <&k3_clks 112 2>; 350 assigned-clock-parents = <&k3_clks 112 3>; 351 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 352 ti,timer-pwm; 353 }; 354 355 main_timer16: timer@2500000 { 356 compatible = "ti,am654-timer"; 357 reg = <0x00 0x2500000 0x00 0x400>; 358 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&k3_clks 113 2>; 360 clock-names = "fck"; 361 assigned-clocks = <&k3_clks 113 2>; 362 assigned-clock-parents = <&k3_clks 113 3>; 363 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 364 ti,timer-pwm; 365 }; 366 367 main_timer17: timer@2510000 { 368 compatible = "ti,am654-timer"; 369 reg = <0x00 0x2510000 0x00 0x400>; 370 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&k3_clks 114 2>; 372 clock-names = "fck"; 373 assigned-clocks = <&k3_clks 114 2>; 374 assigned-clock-parents = <&k3_clks 114 3>; 375 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 376 ti,timer-pwm; 377 }; 378 379 main_timer18: timer@2520000 { 380 compatible = "ti,am654-timer"; 381 reg = <0x00 0x2520000 0x00 0x400>; 382 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&k3_clks 115 2>; 384 clock-names = "fck"; 385 assigned-clocks = <&k3_clks 115 2>; 386 assigned-clock-parents = <&k3_clks 115 3>; 387 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 388 ti,timer-pwm; 389 }; 390 391 main_timer19: timer@2530000 { 392 compatible = "ti,am654-timer"; 393 reg = <0x00 0x2530000 0x00 0x400>; 394 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&k3_clks 116 2>; 396 clock-names = "fck"; 397 assigned-clocks = <&k3_clks 116 2>; 398 assigned-clock-parents = <&k3_clks 116 3>; 399 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 400 ti,timer-pwm; 401 }; 402 403 main_uart0: serial@2800000 { 404 compatible = "ti,j721e-uart", "ti,am654-uart"; 405 reg = <0x00 0x02800000 0x00 0x200>; 406 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 407 current-speed = <115200>; 408 clocks = <&k3_clks 146 0>; 409 clock-names = "fclk"; 410 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 411 status = "disabled"; 412 }; 413 414 main_uart1: serial@2810000 { 415 compatible = "ti,j721e-uart", "ti,am654-uart"; 416 reg = <0x00 0x02810000 0x00 0x200>; 417 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 418 current-speed = <115200>; 419 clocks = <&k3_clks 388 0>; 420 clock-names = "fclk"; 421 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 422 status = "disabled"; 423 }; 424 425 main_uart2: serial@2820000 { 426 compatible = "ti,j721e-uart", "ti,am654-uart"; 427 reg = <0x00 0x02820000 0x00 0x200>; 428 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 429 current-speed = <115200>; 430 clocks = <&k3_clks 389 0>; 431 clock-names = "fclk"; 432 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 433 status = "disabled"; 434 }; 435 436 main_uart3: serial@2830000 { 437 compatible = "ti,j721e-uart", "ti,am654-uart"; 438 reg = <0x00 0x02830000 0x00 0x200>; 439 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 440 current-speed = <115200>; 441 clocks = <&k3_clks 390 0>; 442 clock-names = "fclk"; 443 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 444 status = "disabled"; 445 }; 446 447 main_uart4: serial@2840000 { 448 compatible = "ti,j721e-uart", "ti,am654-uart"; 449 reg = <0x00 0x02840000 0x00 0x200>; 450 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 451 current-speed = <115200>; 452 clocks = <&k3_clks 391 0>; 453 clock-names = "fclk"; 454 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 455 status = "disabled"; 456 }; 457 458 main_uart5: serial@2850000 { 459 compatible = "ti,j721e-uart", "ti,am654-uart"; 460 reg = <0x00 0x02850000 0x00 0x200>; 461 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 462 current-speed = <115200>; 463 clocks = <&k3_clks 392 0>; 464 clock-names = "fclk"; 465 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 466 status = "disabled"; 467 }; 468 469 main_uart6: serial@2860000 { 470 compatible = "ti,j721e-uart", "ti,am654-uart"; 471 reg = <0x00 0x02860000 0x00 0x200>; 472 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 473 current-speed = <115200>; 474 clocks = <&k3_clks 393 0>; 475 clock-names = "fclk"; 476 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 477 status = "disabled"; 478 }; 479 480 main_uart7: serial@2870000 { 481 compatible = "ti,j721e-uart", "ti,am654-uart"; 482 reg = <0x00 0x02870000 0x00 0x200>; 483 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 484 current-speed = <115200>; 485 clocks = <&k3_clks 394 0>; 486 clock-names = "fclk"; 487 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 488 status = "disabled"; 489 }; 490 491 main_uart8: serial@2880000 { 492 compatible = "ti,j721e-uart", "ti,am654-uart"; 493 reg = <0x00 0x02880000 0x00 0x200>; 494 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 495 current-speed = <115200>; 496 clocks = <&k3_clks 395 0>; 497 clock-names = "fclk"; 498 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 499 status = "disabled"; 500 }; 501 502 main_uart9: serial@2890000 { 503 compatible = "ti,j721e-uart", "ti,am654-uart"; 504 reg = <0x00 0x02890000 0x00 0x200>; 505 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 506 current-speed = <115200>; 507 clocks = <&k3_clks 396 0>; 508 clock-names = "fclk"; 509 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 510 status = "disabled"; 511 }; 512 513 main_gpio0: gpio@600000 { 514 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 515 reg = <0x00 0x00600000 0x00 0x100>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-parent = <&main_gpio_intr>; 519 interrupts = <145>, <146>, <147>, <148>, <149>; 520 interrupt-controller; 521 #interrupt-cells = <2>; 522 ti,ngpio = <66>; 523 ti,davinci-gpio-unbanked = <0>; 524 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 525 clocks = <&k3_clks 163 0>; 526 clock-names = "gpio"; 527 status = "disabled"; 528 }; 529 530 main_gpio2: gpio@610000 { 531 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 532 reg = <0x00 0x00610000 0x00 0x100>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-parent = <&main_gpio_intr>; 536 interrupts = <154>, <155>, <156>, <157>, <158>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 ti,ngpio = <66>; 540 ti,davinci-gpio-unbanked = <0>; 541 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 542 clocks = <&k3_clks 164 0>; 543 clock-names = "gpio"; 544 status = "disabled"; 545 }; 546 547 main_gpio4: gpio@620000 { 548 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 549 reg = <0x00 0x00620000 0x00 0x100>; 550 gpio-controller; 551 #gpio-cells = <2>; 552 interrupt-parent = <&main_gpio_intr>; 553 interrupts = <163>, <164>, <165>, <166>, <167>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 ti,ngpio = <66>; 557 ti,davinci-gpio-unbanked = <0>; 558 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 559 clocks = <&k3_clks 165 0>; 560 clock-names = "gpio"; 561 status = "disabled"; 562 }; 563 564 main_gpio6: gpio@630000 { 565 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 566 reg = <0x00 0x00630000 0x00 0x100>; 567 gpio-controller; 568 #gpio-cells = <2>; 569 interrupt-parent = <&main_gpio_intr>; 570 interrupts = <172>, <173>, <174>, <175>, <176>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 ti,ngpio = <66>; 574 ti,davinci-gpio-unbanked = <0>; 575 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 576 clocks = <&k3_clks 166 0>; 577 clock-names = "gpio"; 578 status = "disabled"; 579 }; 580 581 main_i2c0: i2c@2000000 { 582 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 583 reg = <0x00 0x02000000 0x00 0x100>; 584 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 clocks = <&k3_clks 270 2>; 588 clock-names = "fck"; 589 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 590 status = "disabled"; 591 }; 592 593 main_i2c1: i2c@2010000 { 594 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 595 reg = <0x00 0x02010000 0x00 0x100>; 596 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 clocks = <&k3_clks 271 2>; 600 clock-names = "fck"; 601 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 602 status = "disabled"; 603 }; 604 605 main_i2c2: i2c@2020000 { 606 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 607 reg = <0x00 0x02020000 0x00 0x100>; 608 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 clocks = <&k3_clks 272 2>; 612 clock-names = "fck"; 613 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 614 status = "disabled"; 615 }; 616 617 main_i2c3: i2c@2030000 { 618 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 619 reg = <0x00 0x02030000 0x00 0x100>; 620 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 clocks = <&k3_clks 273 2>; 624 clock-names = "fck"; 625 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 626 status = "disabled"; 627 }; 628 629 main_i2c4: i2c@2040000 { 630 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 631 reg = <0x00 0x02040000 0x00 0x100>; 632 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 clocks = <&k3_clks 274 2>; 636 clock-names = "fck"; 637 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 638 status = "disabled"; 639 }; 640 641 main_i2c5: i2c@2050000 { 642 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 643 reg = <0x00 0x02050000 0x00 0x100>; 644 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 clocks = <&k3_clks 275 2>; 648 clock-names = "fck"; 649 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 650 status = "disabled"; 651 }; 652 653 main_i2c6: i2c@2060000 { 654 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 655 reg = <0x00 0x02060000 0x00 0x100>; 656 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&k3_clks 276 2>; 660 clock-names = "fck"; 661 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 662 status = "disabled"; 663 }; 664 665 main_sdhci0: mmc@4f80000 { 666 compatible = "ti,j721e-sdhci-8bit"; 667 reg = <0x00 0x04f80000 0x00 0x1000>, 668 <0x00 0x04f88000 0x00 0x400>; 669 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 670 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 671 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 672 clock-names = "clk_ahb", "clk_xin"; 673 assigned-clocks = <&k3_clks 140 2>; 674 assigned-clock-parents = <&k3_clks 140 3>; 675 bus-width = <8>; 676 ti,otap-del-sel-legacy = <0x0>; 677 ti,otap-del-sel-mmc-hs = <0x0>; 678 ti,otap-del-sel-ddr52 = <0x6>; 679 ti,otap-del-sel-hs200 = <0x8>; 680 ti,otap-del-sel-hs400 = <0x5>; 681 ti,itap-del-sel-legacy = <0x10>; 682 ti,itap-del-sel-mmc-hs = <0xa>; 683 ti,strobe-sel = <0x77>; 684 ti,clkbuf-sel = <0x7>; 685 ti,trm-icp = <0x8>; 686 mmc-ddr-1_8v; 687 mmc-hs200-1_8v; 688 mmc-hs400-1_8v; 689 dma-coherent; 690 status = "disabled"; 691 }; 692 693 main_sdhci1: mmc@4fb0000 { 694 compatible = "ti,j721e-sdhci-4bit"; 695 reg = <0x00 0x04fb0000 0x00 0x1000>, 696 <0x00 0x04fb8000 0x00 0x400>; 697 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 698 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 699 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 700 clock-names = "clk_ahb", "clk_xin"; 701 assigned-clocks = <&k3_clks 141 4>; 702 assigned-clock-parents = <&k3_clks 141 5>; 703 bus-width = <4>; 704 ti,otap-del-sel-legacy = <0x0>; 705 ti,otap-del-sel-sd-hs = <0x0>; 706 ti,otap-del-sel-sdr12 = <0xf>; 707 ti,otap-del-sel-sdr25 = <0xf>; 708 ti,otap-del-sel-sdr50 = <0xc>; 709 ti,otap-del-sel-sdr104 = <0x5>; 710 ti,otap-del-sel-ddr50 = <0xc>; 711 ti,itap-del-sel-legacy = <0x0>; 712 ti,itap-del-sel-sd-hs = <0x0>; 713 ti,itap-del-sel-sdr12 = <0x0>; 714 ti,itap-del-sel-sdr25 = <0x0>; 715 ti,clkbuf-sel = <0x7>; 716 ti,trm-icp = <0x8>; 717 dma-coherent; 718 sdhci-caps-mask = <0x00000003 0x00000000>; 719 no-1-8-v; 720 status = "disabled"; 721 }; 722 723 serdes_wiz0: wiz@5060000 { 724 compatible = "ti,j784s4-wiz-10g"; 725 #address-cells = <1>; 726 #size-cells = <1>; 727 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 728 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 729 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 730 assigned-clocks = <&k3_clks 404 6>; 731 assigned-clock-parents = <&k3_clks 404 10>; 732 num-lanes = <4>; 733 #reset-cells = <1>; 734 #clock-cells = <1>; 735 ranges = <0x5060000 0x00 0x5060000 0x10000>; 736 status = "disabled"; 737 738 serdes0: serdes@5060000 { 739 compatible = "ti,j721e-serdes-10g"; 740 reg = <0x05060000 0x010000>; 741 reg-names = "torrent_phy"; 742 resets = <&serdes_wiz0 0>; 743 reset-names = "torrent_reset"; 744 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 745 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 746 clock-names = "refclk", "phy_en_refclk"; 747 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 748 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 749 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 750 assigned-clock-parents = <&k3_clks 404 6>, 751 <&k3_clks 404 6>, 752 <&k3_clks 404 6>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 #clock-cells = <1>; 756 status = "disabled"; 757 }; 758 }; 759 760 serdes_wiz1: wiz@5070000 { 761 compatible = "ti,j784s4-wiz-10g"; 762 #address-cells = <1>; 763 #size-cells = <1>; 764 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 765 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 766 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 767 assigned-clocks = <&k3_clks 405 6>; 768 assigned-clock-parents = <&k3_clks 405 10>; 769 num-lanes = <4>; 770 #reset-cells = <1>; 771 #clock-cells = <1>; 772 ranges = <0x05070000 0x00 0x05070000 0x10000>; 773 status = "disabled"; 774 775 serdes1: serdes@5070000 { 776 compatible = "ti,j721e-serdes-10g"; 777 reg = <0x05070000 0x010000>; 778 reg-names = "torrent_phy"; 779 resets = <&serdes_wiz1 0>; 780 reset-names = "torrent_reset"; 781 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 782 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 783 clock-names = "refclk", "phy_en_refclk"; 784 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 785 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 786 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 787 assigned-clock-parents = <&k3_clks 405 6>, 788 <&k3_clks 405 6>, 789 <&k3_clks 405 6>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 #clock-cells = <1>; 793 status = "disabled"; 794 }; 795 }; 796 797 serdes_wiz2: wiz@5020000 { 798 compatible = "ti,j784s4-wiz-10g"; 799 #address-cells = <1>; 800 #size-cells = <1>; 801 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; 802 clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; 803 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 804 assigned-clocks = <&k3_clks 406 6>; 805 assigned-clock-parents = <&k3_clks 406 10>; 806 num-lanes = <4>; 807 #reset-cells = <1>; 808 #clock-cells = <1>; 809 ranges = <0x05020000 0x00 0x05020000 0x10000>; 810 status = "disabled"; 811 812 serdes2: serdes@5020000 { 813 compatible = "ti,j721e-serdes-10g"; 814 reg = <0x05020000 0x010000>; 815 reg-names = "torrent_phy"; 816 resets = <&serdes_wiz2 0>; 817 reset-names = "torrent_reset"; 818 clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 819 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; 820 clock-names = "refclk", "phy_en_refclk"; 821 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, 822 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, 823 <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; 824 assigned-clock-parents = <&k3_clks 406 6>, 825 <&k3_clks 406 6>, 826 <&k3_clks 406 6>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 #clock-cells = <1>; 830 status = "disabled"; 831 }; 832 }; 833 834 serdes_wiz4: wiz@5050000 { 835 compatible = "ti,j784s4-wiz-10g"; 836 #address-cells = <1>; 837 #size-cells = <1>; 838 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 839 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 840 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 841 assigned-clocks = <&k3_clks 407 6>; 842 assigned-clock-parents = <&k3_clks 407 10>; 843 num-lanes = <4>; 844 #reset-cells = <1>; 845 #clock-cells = <1>; 846 ranges = <0x05050000 0x00 0x05050000 0x10000>, 847 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 848 status = "disabled"; 849 850 serdes4: serdes@5050000 { 851 /* 852 * Note: we also map DPTX PHY registers as the Torrent 853 * needs to manage those. 854 */ 855 compatible = "ti,j721e-serdes-10g"; 856 reg = <0x05050000 0x010000>, 857 <0x0a030a00 0x40>; /* DPTX PHY */ 858 reg-names = "torrent_phy"; 859 resets = <&serdes_wiz4 0>; 860 reset-names = "torrent_reset"; 861 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 862 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 863 clock-names = "refclk", "phy_en_refclk"; 864 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 865 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 866 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 867 assigned-clock-parents = <&k3_clks 407 6>, 868 <&k3_clks 407 6>, 869 <&k3_clks 407 6>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 #clock-cells = <1>; 873 status = "disabled"; 874 }; 875 }; 876 877 main_navss: bus@30000000 { 878 bootph-all; 879 compatible = "simple-bus"; 880 #address-cells = <2>; 881 #size-cells = <2>; 882 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 883 ti,sci-dev-id = <280>; 884 dma-coherent; 885 dma-ranges; 886 887 main_navss_intr: interrupt-controller@310e0000 { 888 compatible = "ti,sci-intr"; 889 reg = <0x00 0x310e0000 0x00 0x4000>; 890 ti,intr-trigger-type = <4>; 891 interrupt-controller; 892 interrupt-parent = <&gic500>; 893 #interrupt-cells = <1>; 894 ti,sci = <&sms>; 895 ti,sci-dev-id = <283>; 896 ti,interrupt-ranges = <0 64 64>, 897 <64 448 64>, 898 <128 672 64>; 899 }; 900 901 main_udmass_inta: msi-controller@33d00000 { 902 compatible = "ti,sci-inta"; 903 reg = <0x00 0x33d00000 0x00 0x100000>; 904 interrupt-controller; 905 #interrupt-cells = <0>; 906 interrupt-parent = <&main_navss_intr>; 907 msi-controller; 908 ti,sci = <&sms>; 909 ti,sci-dev-id = <321>; 910 ti,interrupt-ranges = <0 0 256>; 911 ti,unmapped-event-sources = <&main_bcdma_csi>; 912 }; 913 914 secure_proxy_main: mailbox@32c00000 { 915 bootph-all; 916 compatible = "ti,am654-secure-proxy"; 917 #mbox-cells = <1>; 918 reg-names = "target_data", "rt", "scfg"; 919 reg = <0x00 0x32c00000 0x00 0x100000>, 920 <0x00 0x32400000 0x00 0x100000>, 921 <0x00 0x32800000 0x00 0x100000>; 922 interrupt-names = "rx_011"; 923 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 924 }; 925 926 hwspinlock: hwlock@30e00000 { 927 compatible = "ti,am654-hwspinlock"; 928 reg = <0x00 0x30e00000 0x00 0x1000>; 929 #hwlock-cells = <1>; 930 }; 931 932 mailbox0_cluster0: mailbox@31f80000 { 933 compatible = "ti,am654-mailbox"; 934 reg = <0x00 0x31f80000 0x00 0x200>; 935 #mbox-cells = <1>; 936 ti,mbox-num-users = <4>; 937 ti,mbox-num-fifos = <16>; 938 interrupt-parent = <&main_navss_intr>; 939 status = "disabled"; 940 }; 941 942 mailbox0_cluster1: mailbox@31f81000 { 943 compatible = "ti,am654-mailbox"; 944 reg = <0x00 0x31f81000 0x00 0x200>; 945 #mbox-cells = <1>; 946 ti,mbox-num-users = <4>; 947 ti,mbox-num-fifos = <16>; 948 interrupt-parent = <&main_navss_intr>; 949 status = "disabled"; 950 }; 951 952 mailbox0_cluster2: mailbox@31f82000 { 953 compatible = "ti,am654-mailbox"; 954 reg = <0x00 0x31f82000 0x00 0x200>; 955 #mbox-cells = <1>; 956 ti,mbox-num-users = <4>; 957 ti,mbox-num-fifos = <16>; 958 interrupt-parent = <&main_navss_intr>; 959 status = "disabled"; 960 }; 961 962 mailbox0_cluster3: mailbox@31f83000 { 963 compatible = "ti,am654-mailbox"; 964 reg = <0x00 0x31f83000 0x00 0x200>; 965 #mbox-cells = <1>; 966 ti,mbox-num-users = <4>; 967 ti,mbox-num-fifos = <16>; 968 interrupt-parent = <&main_navss_intr>; 969 status = "disabled"; 970 }; 971 972 mailbox0_cluster4: mailbox@31f84000 { 973 compatible = "ti,am654-mailbox"; 974 reg = <0x00 0x31f84000 0x00 0x200>; 975 #mbox-cells = <1>; 976 ti,mbox-num-users = <4>; 977 ti,mbox-num-fifos = <16>; 978 interrupt-parent = <&main_navss_intr>; 979 status = "disabled"; 980 }; 981 982 mailbox0_cluster5: mailbox@31f85000 { 983 compatible = "ti,am654-mailbox"; 984 reg = <0x00 0x31f85000 0x00 0x200>; 985 #mbox-cells = <1>; 986 ti,mbox-num-users = <4>; 987 ti,mbox-num-fifos = <16>; 988 interrupt-parent = <&main_navss_intr>; 989 status = "disabled"; 990 }; 991 992 mailbox0_cluster6: mailbox@31f86000 { 993 compatible = "ti,am654-mailbox"; 994 reg = <0x00 0x31f86000 0x00 0x200>; 995 #mbox-cells = <1>; 996 ti,mbox-num-users = <4>; 997 ti,mbox-num-fifos = <16>; 998 interrupt-parent = <&main_navss_intr>; 999 status = "disabled"; 1000 }; 1001 1002 mailbox0_cluster7: mailbox@31f87000 { 1003 compatible = "ti,am654-mailbox"; 1004 reg = <0x00 0x31f87000 0x00 0x200>; 1005 #mbox-cells = <1>; 1006 ti,mbox-num-users = <4>; 1007 ti,mbox-num-fifos = <16>; 1008 interrupt-parent = <&main_navss_intr>; 1009 status = "disabled"; 1010 }; 1011 1012 mailbox0_cluster8: mailbox@31f88000 { 1013 compatible = "ti,am654-mailbox"; 1014 reg = <0x00 0x31f88000 0x00 0x200>; 1015 #mbox-cells = <1>; 1016 ti,mbox-num-users = <4>; 1017 ti,mbox-num-fifos = <16>; 1018 interrupt-parent = <&main_navss_intr>; 1019 status = "disabled"; 1020 }; 1021 1022 mailbox0_cluster9: mailbox@31f89000 { 1023 compatible = "ti,am654-mailbox"; 1024 reg = <0x00 0x31f89000 0x00 0x200>; 1025 #mbox-cells = <1>; 1026 ti,mbox-num-users = <4>; 1027 ti,mbox-num-fifos = <16>; 1028 interrupt-parent = <&main_navss_intr>; 1029 status = "disabled"; 1030 }; 1031 1032 mailbox0_cluster10: mailbox@31f8a000 { 1033 compatible = "ti,am654-mailbox"; 1034 reg = <0x00 0x31f8a000 0x00 0x200>; 1035 #mbox-cells = <1>; 1036 ti,mbox-num-users = <4>; 1037 ti,mbox-num-fifos = <16>; 1038 interrupt-parent = <&main_navss_intr>; 1039 status = "disabled"; 1040 }; 1041 1042 mailbox0_cluster11: mailbox@31f8b000 { 1043 compatible = "ti,am654-mailbox"; 1044 reg = <0x00 0x31f8b000 0x00 0x200>; 1045 #mbox-cells = <1>; 1046 ti,mbox-num-users = <4>; 1047 ti,mbox-num-fifos = <16>; 1048 interrupt-parent = <&main_navss_intr>; 1049 status = "disabled"; 1050 }; 1051 1052 mailbox1_cluster0: mailbox@31f90000 { 1053 compatible = "ti,am654-mailbox"; 1054 reg = <0x00 0x31f90000 0x00 0x200>; 1055 #mbox-cells = <1>; 1056 ti,mbox-num-users = <4>; 1057 ti,mbox-num-fifos = <16>; 1058 interrupt-parent = <&main_navss_intr>; 1059 status = "disabled"; 1060 }; 1061 1062 mailbox1_cluster1: mailbox@31f91000 { 1063 compatible = "ti,am654-mailbox"; 1064 reg = <0x00 0x31f91000 0x00 0x200>; 1065 #mbox-cells = <1>; 1066 ti,mbox-num-users = <4>; 1067 ti,mbox-num-fifos = <16>; 1068 interrupt-parent = <&main_navss_intr>; 1069 status = "disabled"; 1070 }; 1071 1072 mailbox1_cluster2: mailbox@31f92000 { 1073 compatible = "ti,am654-mailbox"; 1074 reg = <0x00 0x31f92000 0x00 0x200>; 1075 #mbox-cells = <1>; 1076 ti,mbox-num-users = <4>; 1077 ti,mbox-num-fifos = <16>; 1078 interrupt-parent = <&main_navss_intr>; 1079 status = "disabled"; 1080 }; 1081 1082 mailbox1_cluster3: mailbox@31f93000 { 1083 compatible = "ti,am654-mailbox"; 1084 reg = <0x00 0x31f93000 0x00 0x200>; 1085 #mbox-cells = <1>; 1086 ti,mbox-num-users = <4>; 1087 ti,mbox-num-fifos = <16>; 1088 interrupt-parent = <&main_navss_intr>; 1089 status = "disabled"; 1090 }; 1091 1092 mailbox1_cluster4: mailbox@31f94000 { 1093 compatible = "ti,am654-mailbox"; 1094 reg = <0x00 0x31f94000 0x00 0x200>; 1095 #mbox-cells = <1>; 1096 ti,mbox-num-users = <4>; 1097 ti,mbox-num-fifos = <16>; 1098 interrupt-parent = <&main_navss_intr>; 1099 status = "disabled"; 1100 }; 1101 1102 mailbox1_cluster5: mailbox@31f95000 { 1103 compatible = "ti,am654-mailbox"; 1104 reg = <0x00 0x31f95000 0x00 0x200>; 1105 #mbox-cells = <1>; 1106 ti,mbox-num-users = <4>; 1107 ti,mbox-num-fifos = <16>; 1108 interrupt-parent = <&main_navss_intr>; 1109 status = "disabled"; 1110 }; 1111 1112 mailbox1_cluster6: mailbox@31f96000 { 1113 compatible = "ti,am654-mailbox"; 1114 reg = <0x00 0x31f96000 0x00 0x200>; 1115 #mbox-cells = <1>; 1116 ti,mbox-num-users = <4>; 1117 ti,mbox-num-fifos = <16>; 1118 interrupt-parent = <&main_navss_intr>; 1119 status = "disabled"; 1120 }; 1121 1122 mailbox1_cluster7: mailbox@31f97000 { 1123 compatible = "ti,am654-mailbox"; 1124 reg = <0x00 0x31f97000 0x00 0x200>; 1125 #mbox-cells = <1>; 1126 ti,mbox-num-users = <4>; 1127 ti,mbox-num-fifos = <16>; 1128 interrupt-parent = <&main_navss_intr>; 1129 status = "disabled"; 1130 }; 1131 1132 mailbox1_cluster8: mailbox@31f98000 { 1133 compatible = "ti,am654-mailbox"; 1134 reg = <0x00 0x31f98000 0x00 0x200>; 1135 #mbox-cells = <1>; 1136 ti,mbox-num-users = <4>; 1137 ti,mbox-num-fifos = <16>; 1138 interrupt-parent = <&main_navss_intr>; 1139 status = "disabled"; 1140 }; 1141 1142 mailbox1_cluster9: mailbox@31f99000 { 1143 compatible = "ti,am654-mailbox"; 1144 reg = <0x00 0x31f99000 0x00 0x200>; 1145 #mbox-cells = <1>; 1146 ti,mbox-num-users = <4>; 1147 ti,mbox-num-fifos = <16>; 1148 interrupt-parent = <&main_navss_intr>; 1149 status = "disabled"; 1150 }; 1151 1152 mailbox1_cluster10: mailbox@31f9a000 { 1153 compatible = "ti,am654-mailbox"; 1154 reg = <0x00 0x31f9a000 0x00 0x200>; 1155 #mbox-cells = <1>; 1156 ti,mbox-num-users = <4>; 1157 ti,mbox-num-fifos = <16>; 1158 interrupt-parent = <&main_navss_intr>; 1159 status = "disabled"; 1160 }; 1161 1162 mailbox1_cluster11: mailbox@31f9b000 { 1163 compatible = "ti,am654-mailbox"; 1164 reg = <0x00 0x31f9b000 0x00 0x200>; 1165 #mbox-cells = <1>; 1166 ti,mbox-num-users = <4>; 1167 ti,mbox-num-fifos = <16>; 1168 interrupt-parent = <&main_navss_intr>; 1169 status = "disabled"; 1170 }; 1171 1172 main_ringacc: ringacc@3c000000 { 1173 compatible = "ti,am654-navss-ringacc"; 1174 reg = <0x00 0x3c000000 0x00 0x400000>, 1175 <0x00 0x38000000 0x00 0x400000>, 1176 <0x00 0x31120000 0x00 0x100>, 1177 <0x00 0x33000000 0x00 0x40000>, 1178 <0x00 0x31080000 0x00 0x40000>; 1179 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1180 ti,num-rings = <1024>; 1181 ti,sci-rm-range-gp-rings = <0x1>; 1182 ti,sci = <&sms>; 1183 ti,sci-dev-id = <315>; 1184 msi-parent = <&main_udmass_inta>; 1185 }; 1186 1187 main_udmap: dma-controller@31150000 { 1188 compatible = "ti,j721e-navss-main-udmap"; 1189 reg = <0x00 0x31150000 0x00 0x100>, 1190 <0x00 0x34000000 0x00 0x80000>, 1191 <0x00 0x35000000 0x00 0x200000>; 1192 reg-names = "gcfg", "rchanrt", "tchanrt"; 1193 msi-parent = <&main_udmass_inta>; 1194 #dma-cells = <1>; 1195 1196 ti,sci = <&sms>; 1197 ti,sci-dev-id = <319>; 1198 ti,ringacc = <&main_ringacc>; 1199 1200 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1201 <0x0f>, /* TX_HCHAN */ 1202 <0x10>; /* TX_UHCHAN */ 1203 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1204 <0x0b>, /* RX_HCHAN */ 1205 <0x0c>; /* RX_UHCHAN */ 1206 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1207 }; 1208 1209 main_bcdma_csi: dma-controller@311a0000 { 1210 compatible = "ti,j721s2-dmss-bcdma-csi"; 1211 reg = <0x00 0x311a0000 0x00 0x100>, 1212 <0x00 0x35d00000 0x00 0x20000>, 1213 <0x00 0x35c00000 0x00 0x10000>, 1214 <0x00 0x35e00000 0x00 0x80000>; 1215 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1216 msi-parent = <&main_udmass_inta>; 1217 #dma-cells = <3>; 1218 ti,sci = <&sms>; 1219 ti,sci-dev-id = <281>; 1220 ti,sci-rm-range-rchan = <0x21>; 1221 ti,sci-rm-range-tchan = <0x22>; 1222 status = "disabled"; 1223 }; 1224 1225 cpts@310d0000 { 1226 compatible = "ti,j721e-cpts"; 1227 reg = <0x00 0x310d0000 0x00 0x400>; 1228 reg-names = "cpts"; 1229 clocks = <&k3_clks 282 0>; 1230 clock-names = "cpts"; 1231 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1232 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1233 interrupts-extended = <&main_navss_intr 391>; 1234 interrupt-names = "cpts"; 1235 ti,cpts-periodic-outputs = <6>; 1236 ti,cpts-ext-ts-inputs = <8>; 1237 }; 1238 }; 1239 1240 main_mcan0: can@2701000 { 1241 compatible = "bosch,m_can"; 1242 reg = <0x00 0x02701000 0x00 0x200>, 1243 <0x00 0x02708000 0x00 0x8000>; 1244 reg-names = "m_can", "message_ram"; 1245 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1246 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1247 clock-names = "hclk", "cclk"; 1248 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1250 interrupt-names = "int0", "int1"; 1251 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1252 status = "disabled"; 1253 }; 1254 1255 main_mcan1: can@2711000 { 1256 compatible = "bosch,m_can"; 1257 reg = <0x00 0x02711000 0x00 0x200>, 1258 <0x00 0x02718000 0x00 0x8000>; 1259 reg-names = "m_can", "message_ram"; 1260 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1261 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1262 clock-names = "hclk", "cclk"; 1263 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1265 interrupt-names = "int0", "int1"; 1266 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1267 status = "disabled"; 1268 }; 1269 1270 main_mcan2: can@2721000 { 1271 compatible = "bosch,m_can"; 1272 reg = <0x00 0x02721000 0x00 0x200>, 1273 <0x00 0x02728000 0x00 0x8000>; 1274 reg-names = "m_can", "message_ram"; 1275 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1276 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1277 clock-names = "hclk", "cclk"; 1278 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1280 interrupt-names = "int0", "int1"; 1281 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1282 status = "disabled"; 1283 }; 1284 1285 main_mcan3: can@2731000 { 1286 compatible = "bosch,m_can"; 1287 reg = <0x00 0x02731000 0x00 0x200>, 1288 <0x00 0x02738000 0x00 0x8000>; 1289 reg-names = "m_can", "message_ram"; 1290 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1291 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1292 clock-names = "hclk", "cclk"; 1293 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1295 interrupt-names = "int0", "int1"; 1296 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1297 status = "disabled"; 1298 }; 1299 1300 main_mcan4: can@2741000 { 1301 compatible = "bosch,m_can"; 1302 reg = <0x00 0x02741000 0x00 0x200>, 1303 <0x00 0x02748000 0x00 0x8000>; 1304 reg-names = "m_can", "message_ram"; 1305 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1306 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1307 clock-names = "hclk", "cclk"; 1308 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1310 interrupt-names = "int0", "int1"; 1311 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1312 status = "disabled"; 1313 }; 1314 1315 main_mcan5: can@2751000 { 1316 compatible = "bosch,m_can"; 1317 reg = <0x00 0x02751000 0x00 0x200>, 1318 <0x00 0x02758000 0x00 0x8000>; 1319 reg-names = "m_can", "message_ram"; 1320 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1321 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1322 clock-names = "hclk", "cclk"; 1323 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1325 interrupt-names = "int0", "int1"; 1326 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1327 status = "disabled"; 1328 }; 1329 1330 main_mcan6: can@2761000 { 1331 compatible = "bosch,m_can"; 1332 reg = <0x00 0x02761000 0x00 0x200>, 1333 <0x00 0x02768000 0x00 0x8000>; 1334 reg-names = "m_can", "message_ram"; 1335 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1336 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1337 clock-names = "hclk", "cclk"; 1338 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1340 interrupt-names = "int0", "int1"; 1341 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1342 status = "disabled"; 1343 }; 1344 1345 main_mcan7: can@2771000 { 1346 compatible = "bosch,m_can"; 1347 reg = <0x00 0x02771000 0x00 0x200>, 1348 <0x00 0x02778000 0x00 0x8000>; 1349 reg-names = "m_can", "message_ram"; 1350 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1351 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1352 clock-names = "hclk", "cclk"; 1353 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1355 interrupt-names = "int0", "int1"; 1356 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1357 status = "disabled"; 1358 }; 1359 1360 main_mcan8: can@2781000 { 1361 compatible = "bosch,m_can"; 1362 reg = <0x00 0x02781000 0x00 0x200>, 1363 <0x00 0x02788000 0x00 0x8000>; 1364 reg-names = "m_can", "message_ram"; 1365 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1366 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1367 clock-names = "hclk", "cclk"; 1368 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1370 interrupt-names = "int0", "int1"; 1371 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1372 status = "disabled"; 1373 }; 1374 1375 main_mcan9: can@2791000 { 1376 compatible = "bosch,m_can"; 1377 reg = <0x00 0x02791000 0x00 0x200>, 1378 <0x00 0x02798000 0x00 0x8000>; 1379 reg-names = "m_can", "message_ram"; 1380 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1381 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1382 clock-names = "hclk", "cclk"; 1383 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1385 interrupt-names = "int0", "int1"; 1386 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1387 status = "disabled"; 1388 }; 1389 1390 main_mcan10: can@27a1000 { 1391 compatible = "bosch,m_can"; 1392 reg = <0x00 0x027a1000 0x00 0x200>, 1393 <0x00 0x027a8000 0x00 0x8000>; 1394 reg-names = "m_can", "message_ram"; 1395 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1396 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1397 clock-names = "hclk", "cclk"; 1398 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1400 interrupt-names = "int0", "int1"; 1401 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1402 status = "disabled"; 1403 }; 1404 1405 main_mcan11: can@27b1000 { 1406 compatible = "bosch,m_can"; 1407 reg = <0x00 0x027b1000 0x00 0x200>, 1408 <0x00 0x027b8000 0x00 0x8000>; 1409 reg-names = "m_can", "message_ram"; 1410 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1411 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1412 clock-names = "hclk", "cclk"; 1413 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1415 interrupt-names = "int0", "int1"; 1416 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1417 status = "disabled"; 1418 }; 1419 1420 main_mcan12: can@27c1000 { 1421 compatible = "bosch,m_can"; 1422 reg = <0x00 0x027c1000 0x00 0x200>, 1423 <0x00 0x027c8000 0x00 0x8000>; 1424 reg-names = "m_can", "message_ram"; 1425 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1426 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1427 clock-names = "hclk", "cclk"; 1428 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1430 interrupt-names = "int0", "int1"; 1431 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1432 status = "disabled"; 1433 }; 1434 1435 main_mcan13: can@27d1000 { 1436 compatible = "bosch,m_can"; 1437 reg = <0x00 0x027d1000 0x00 0x200>, 1438 <0x00 0x027d8000 0x00 0x8000>; 1439 reg-names = "m_can", "message_ram"; 1440 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1441 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1442 clock-names = "hclk", "cclk"; 1443 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1445 interrupt-names = "int0", "int1"; 1446 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1447 status = "disabled"; 1448 }; 1449 1450 main_mcan14: can@2681000 { 1451 compatible = "bosch,m_can"; 1452 reg = <0x00 0x02681000 0x00 0x200>, 1453 <0x00 0x02688000 0x00 0x8000>; 1454 reg-names = "m_can", "message_ram"; 1455 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1456 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1457 clock-names = "hclk", "cclk"; 1458 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1460 interrupt-names = "int0", "int1"; 1461 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1462 status = "disabled"; 1463 }; 1464 1465 main_mcan15: can@2691000 { 1466 compatible = "bosch,m_can"; 1467 reg = <0x00 0x02691000 0x00 0x200>, 1468 <0x00 0x02698000 0x00 0x8000>; 1469 reg-names = "m_can", "message_ram"; 1470 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 1471 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 1472 clock-names = "hclk", "cclk"; 1473 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1475 interrupt-names = "int0", "int1"; 1476 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1477 status = "disabled"; 1478 }; 1479 1480 main_mcan16: can@26a1000 { 1481 compatible = "bosch,m_can"; 1482 reg = <0x00 0x026a1000 0x00 0x200>, 1483 <0x00 0x026a8000 0x00 0x8000>; 1484 reg-names = "m_can", "message_ram"; 1485 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 1486 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 1487 clock-names = "hclk", "cclk"; 1488 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1490 interrupt-names = "int0", "int1"; 1491 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1492 status = "disabled"; 1493 }; 1494 1495 main_mcan17: can@26b1000 { 1496 compatible = "bosch,m_can"; 1497 reg = <0x00 0x026b1000 0x00 0x200>, 1498 <0x00 0x026b8000 0x00 0x8000>; 1499 reg-names = "m_can", "message_ram"; 1500 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 1501 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 1502 clock-names = "hclk", "cclk"; 1503 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1505 interrupt-names = "int0", "int1"; 1506 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1507 status = "disabled"; 1508 }; 1509 1510 main_spi0: spi@2100000 { 1511 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1512 reg = <0x00 0x02100000 0x00 0x400>; 1513 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 1517 clocks = <&k3_clks 376 1>; 1518 status = "disabled"; 1519 }; 1520 1521 main_spi1: spi@2110000 { 1522 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1523 reg = <0x00 0x02110000 0x00 0x400>; 1524 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 1528 clocks = <&k3_clks 377 1>; 1529 status = "disabled"; 1530 }; 1531 1532 main_spi2: spi@2120000 { 1533 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1534 reg = <0x00 0x02120000 0x00 0x400>; 1535 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 1539 clocks = <&k3_clks 378 1>; 1540 status = "disabled"; 1541 }; 1542 1543 main_spi3: spi@2130000 { 1544 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1545 reg = <0x00 0x02130000 0x00 0x400>; 1546 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 1550 clocks = <&k3_clks 379 1>; 1551 status = "disabled"; 1552 }; 1553 1554 main_spi4: spi@2140000 { 1555 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1556 reg = <0x00 0x02140000 0x00 0x400>; 1557 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 1561 clocks = <&k3_clks 380 1>; 1562 status = "disabled"; 1563 }; 1564 1565 main_spi5: spi@2150000 { 1566 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1567 reg = <0x00 0x02150000 0x00 0x400>; 1568 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 1572 clocks = <&k3_clks 381 1>; 1573 status = "disabled"; 1574 }; 1575 1576 main_spi6: spi@2160000 { 1577 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1578 reg = <0x00 0x02160000 0x00 0x400>; 1579 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 1583 clocks = <&k3_clks 382 1>; 1584 status = "disabled"; 1585 }; 1586 1587 main_spi7: spi@2170000 { 1588 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1589 reg = <0x00 0x02170000 0x00 0x400>; 1590 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 1594 clocks = <&k3_clks 383 1>; 1595 status = "disabled"; 1596 }; 1597 1598 ufs_wrapper: ufs-wrapper@4e80000 { 1599 compatible = "ti,j721e-ufs"; 1600 reg = <0x00 0x4e80000 0x00 0x100>; 1601 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 1602 clocks = <&k3_clks 387 3>; 1603 assigned-clocks = <&k3_clks 387 3>; 1604 assigned-clock-parents = <&k3_clks 387 6>; 1605 ranges; 1606 #address-cells = <2>; 1607 #size-cells = <2>; 1608 status = "disabled"; 1609 1610 ufs@4e84000 { 1611 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1612 reg = <0x00 0x4e84000 0x00 0x10000>; 1613 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1614 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 1615 <19200000 19200000>; 1616 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 1617 clock-names = "core_clk", "phy_clk", "ref_clk"; 1618 dma-coherent; 1619 }; 1620 }; 1621 1622 main_r5fss0: r5fss@5c00000 { 1623 compatible = "ti,j721s2-r5fss"; 1624 ti,cluster-mode = <1>; 1625 #address-cells = <1>; 1626 #size-cells = <1>; 1627 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1628 <0x5d00000 0x00 0x5d00000 0x20000>; 1629 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 1630 1631 main_r5fss0_core0: r5f@5c00000 { 1632 compatible = "ti,j721s2-r5f"; 1633 reg = <0x5c00000 0x00010000>, 1634 <0x5c10000 0x00010000>; 1635 reg-names = "atcm", "btcm"; 1636 ti,sci = <&sms>; 1637 ti,sci-dev-id = <339>; 1638 ti,sci-proc-ids = <0x06 0xff>; 1639 resets = <&k3_reset 339 1>; 1640 firmware-name = "j784s4-main-r5f0_0-fw"; 1641 ti,atcm-enable = <1>; 1642 ti,btcm-enable = <1>; 1643 ti,loczrama = <1>; 1644 }; 1645 1646 main_r5fss0_core1: r5f@5d00000 { 1647 compatible = "ti,j721s2-r5f"; 1648 reg = <0x5d00000 0x00010000>, 1649 <0x5d10000 0x00010000>; 1650 reg-names = "atcm", "btcm"; 1651 ti,sci = <&sms>; 1652 ti,sci-dev-id = <340>; 1653 ti,sci-proc-ids = <0x07 0xff>; 1654 resets = <&k3_reset 340 1>; 1655 firmware-name = "j784s4-main-r5f0_1-fw"; 1656 ti,atcm-enable = <1>; 1657 ti,btcm-enable = <1>; 1658 ti,loczrama = <1>; 1659 }; 1660 }; 1661 1662 main_r5fss1: r5fss@5e00000 { 1663 compatible = "ti,j721s2-r5fss"; 1664 ti,cluster-mode = <1>; 1665 #address-cells = <1>; 1666 #size-cells = <1>; 1667 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1668 <0x5f00000 0x00 0x5f00000 0x20000>; 1669 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 1670 1671 main_r5fss1_core0: r5f@5e00000 { 1672 compatible = "ti,j721s2-r5f"; 1673 reg = <0x5e00000 0x00010000>, 1674 <0x5e10000 0x00010000>; 1675 reg-names = "atcm", "btcm"; 1676 ti,sci = <&sms>; 1677 ti,sci-dev-id = <341>; 1678 ti,sci-proc-ids = <0x08 0xff>; 1679 resets = <&k3_reset 341 1>; 1680 firmware-name = "j784s4-main-r5f1_0-fw"; 1681 ti,atcm-enable = <1>; 1682 ti,btcm-enable = <1>; 1683 ti,loczrama = <1>; 1684 }; 1685 1686 main_r5fss1_core1: r5f@5f00000 { 1687 compatible = "ti,j721s2-r5f"; 1688 reg = <0x5f00000 0x00010000>, 1689 <0x5f10000 0x00010000>; 1690 reg-names = "atcm", "btcm"; 1691 ti,sci = <&sms>; 1692 ti,sci-dev-id = <342>; 1693 ti,sci-proc-ids = <0x09 0xff>; 1694 resets = <&k3_reset 342 1>; 1695 firmware-name = "j784s4-main-r5f1_1-fw"; 1696 ti,atcm-enable = <1>; 1697 ti,btcm-enable = <1>; 1698 ti,loczrama = <1>; 1699 }; 1700 }; 1701 1702 main_r5fss2: r5fss@5900000 { 1703 compatible = "ti,j721s2-r5fss"; 1704 ti,cluster-mode = <1>; 1705 #address-cells = <1>; 1706 #size-cells = <1>; 1707 ranges = <0x5900000 0x00 0x5900000 0x20000>, 1708 <0x5a00000 0x00 0x5a00000 0x20000>; 1709 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 1710 1711 main_r5fss2_core0: r5f@5900000 { 1712 compatible = "ti,j721s2-r5f"; 1713 reg = <0x5900000 0x00010000>, 1714 <0x5910000 0x00010000>; 1715 reg-names = "atcm", "btcm"; 1716 ti,sci = <&sms>; 1717 ti,sci-dev-id = <343>; 1718 ti,sci-proc-ids = <0x0a 0xff>; 1719 resets = <&k3_reset 343 1>; 1720 firmware-name = "j784s4-main-r5f2_0-fw"; 1721 ti,atcm-enable = <1>; 1722 ti,btcm-enable = <1>; 1723 ti,loczrama = <1>; 1724 }; 1725 1726 main_r5fss2_core1: r5f@5a00000 { 1727 compatible = "ti,j721s2-r5f"; 1728 reg = <0x5a00000 0x00010000>, 1729 <0x5a10000 0x00010000>; 1730 reg-names = "atcm", "btcm"; 1731 ti,sci = <&sms>; 1732 ti,sci-dev-id = <344>; 1733 ti,sci-proc-ids = <0x0b 0xff>; 1734 resets = <&k3_reset 344 1>; 1735 firmware-name = "j784s4-main-r5f2_1-fw"; 1736 ti,atcm-enable = <1>; 1737 ti,btcm-enable = <1>; 1738 ti,loczrama = <1>; 1739 }; 1740 }; 1741 1742 c71_0: dsp@64800000 { 1743 compatible = "ti,j721s2-c71-dsp"; 1744 reg = <0x00 0x64800000 0x00 0x00080000>, 1745 <0x00 0x64e00000 0x00 0x0000c000>; 1746 reg-names = "l2sram", "l1dram"; 1747 ti,sci = <&sms>; 1748 ti,sci-dev-id = <30>; 1749 ti,sci-proc-ids = <0x30 0xff>; 1750 resets = <&k3_reset 30 1>; 1751 firmware-name = "j784s4-c71_0-fw"; 1752 status = "disabled"; 1753 }; 1754 1755 c71_1: dsp@65800000 { 1756 compatible = "ti,j721s2-c71-dsp"; 1757 reg = <0x00 0x65800000 0x00 0x00080000>, 1758 <0x00 0x65e00000 0x00 0x0000c000>; 1759 reg-names = "l2sram", "l1dram"; 1760 ti,sci = <&sms>; 1761 ti,sci-dev-id = <33>; 1762 ti,sci-proc-ids = <0x31 0xff>; 1763 resets = <&k3_reset 33 1>; 1764 firmware-name = "j784s4-c71_1-fw"; 1765 status = "disabled"; 1766 }; 1767 1768 c71_2: dsp@66800000 { 1769 compatible = "ti,j721s2-c71-dsp"; 1770 reg = <0x00 0x66800000 0x00 0x00080000>, 1771 <0x00 0x66e00000 0x00 0x0000c000>; 1772 reg-names = "l2sram", "l1dram"; 1773 ti,sci = <&sms>; 1774 ti,sci-dev-id = <37>; 1775 ti,sci-proc-ids = <0x32 0xff>; 1776 resets = <&k3_reset 37 1>; 1777 firmware-name = "j784s4-c71_2-fw"; 1778 status = "disabled"; 1779 }; 1780 1781 c71_3: dsp@67800000 { 1782 compatible = "ti,j721s2-c71-dsp"; 1783 reg = <0x00 0x67800000 0x00 0x00080000>, 1784 <0x00 0x67e00000 0x00 0x0000c000>; 1785 reg-names = "l2sram", "l1dram"; 1786 ti,sci = <&sms>; 1787 ti,sci-dev-id = <40>; 1788 ti,sci-proc-ids = <0x33 0xff>; 1789 resets = <&k3_reset 40 1>; 1790 firmware-name = "j784s4-c71_3-fw"; 1791 status = "disabled"; 1792 }; 1793 1794 main_esm: esm@700000 { 1795 compatible = "ti,j721e-esm"; 1796 reg = <0x00 0x700000 0x00 0x1000>; 1797 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 1798 <695>; 1799 bootph-pre-ram; 1800 }; 1801 1802 watchdog0: watchdog@2200000 { 1803 compatible = "ti,j7-rti-wdt"; 1804 reg = <0x00 0x2200000 0x00 0x100>; 1805 clocks = <&k3_clks 348 1>; 1806 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 1807 assigned-clocks = <&k3_clks 348 0>; 1808 assigned-clock-parents = <&k3_clks 348 4>; 1809 }; 1810 1811 watchdog1: watchdog@2210000 { 1812 compatible = "ti,j7-rti-wdt"; 1813 reg = <0x00 0x2210000 0x00 0x100>; 1814 clocks = <&k3_clks 349 1>; 1815 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 1816 assigned-clocks = <&k3_clks 349 0>; 1817 assigned-clock-parents = <&k3_clks 349 4>; 1818 }; 1819 1820 watchdog2: watchdog@2220000 { 1821 compatible = "ti,j7-rti-wdt"; 1822 reg = <0x00 0x2220000 0x00 0x100>; 1823 clocks = <&k3_clks 350 1>; 1824 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 1825 assigned-clocks = <&k3_clks 350 0>; 1826 assigned-clock-parents = <&k3_clks 350 4>; 1827 }; 1828 1829 watchdog3: watchdog@2230000 { 1830 compatible = "ti,j7-rti-wdt"; 1831 reg = <0x00 0x2230000 0x00 0x100>; 1832 clocks = <&k3_clks 351 1>; 1833 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 1834 assigned-clocks = <&k3_clks 351 0>; 1835 assigned-clock-parents = <&k3_clks 351 4>; 1836 }; 1837 1838 watchdog4: watchdog@2240000 { 1839 compatible = "ti,j7-rti-wdt"; 1840 reg = <0x00 0x2240000 0x00 0x100>; 1841 clocks = <&k3_clks 352 1>; 1842 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 1843 assigned-clocks = <&k3_clks 352 0>; 1844 assigned-clock-parents = <&k3_clks 352 4>; 1845 }; 1846 1847 watchdog5: watchdog@2250000 { 1848 compatible = "ti,j7-rti-wdt"; 1849 reg = <0x00 0x2250000 0x00 0x100>; 1850 clocks = <&k3_clks 353 1>; 1851 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 1852 assigned-clocks = <&k3_clks 353 0>; 1853 assigned-clock-parents = <&k3_clks 353 4>; 1854 }; 1855 1856 watchdog6: watchdog@2260000 { 1857 compatible = "ti,j7-rti-wdt"; 1858 reg = <0x00 0x2260000 0x00 0x100>; 1859 clocks = <&k3_clks 354 1>; 1860 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 1861 assigned-clocks = <&k3_clks 354 0>; 1862 assigned-clock-parents = <&k3_clks 354 4>; 1863 }; 1864 1865 watchdog7: watchdog@2270000 { 1866 compatible = "ti,j7-rti-wdt"; 1867 reg = <0x00 0x2270000 0x00 0x100>; 1868 clocks = <&k3_clks 355 1>; 1869 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 1870 assigned-clocks = <&k3_clks 355 0>; 1871 assigned-clock-parents = <&k3_clks 355 4>; 1872 }; 1873 1874 /* 1875 * The following RTI instances are coupled with MCU R5Fs, c7x and 1876 * GPU so keeping them reserved as these will be used by their 1877 * respective firmware 1878 */ 1879 watchdog8: watchdog@22f0000 { 1880 compatible = "ti,j7-rti-wdt"; 1881 reg = <0x00 0x22f0000 0x00 0x100>; 1882 clocks = <&k3_clks 360 1>; 1883 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 1884 assigned-clocks = <&k3_clks 360 0>; 1885 assigned-clock-parents = <&k3_clks 360 4>; 1886 /* reserved for GPU */ 1887 status = "reserved"; 1888 }; 1889 1890 watchdog9: watchdog@2300000 { 1891 compatible = "ti,j7-rti-wdt"; 1892 reg = <0x00 0x2300000 0x00 0x100>; 1893 clocks = <&k3_clks 356 1>; 1894 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 1895 assigned-clocks = <&k3_clks 356 0>; 1896 assigned-clock-parents = <&k3_clks 356 4>; 1897 /* reserved for C7X_0 DSP */ 1898 status = "reserved"; 1899 }; 1900 1901 watchdog10: watchdog@2310000 { 1902 compatible = "ti,j7-rti-wdt"; 1903 reg = <0x00 0x2310000 0x00 0x100>; 1904 clocks = <&k3_clks 357 1>; 1905 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 1906 assigned-clocks = <&k3_clks 357 0>; 1907 assigned-clock-parents = <&k3_clks 357 4>; 1908 /* reserved for C7X_1 DSP */ 1909 status = "reserved"; 1910 }; 1911 1912 watchdog11: watchdog@2320000 { 1913 compatible = "ti,j7-rti-wdt"; 1914 reg = <0x00 0x2320000 0x00 0x100>; 1915 clocks = <&k3_clks 358 1>; 1916 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 1917 assigned-clocks = <&k3_clks 358 0>; 1918 assigned-clock-parents = <&k3_clks 358 4>; 1919 /* reserved for C7X_2 DSP */ 1920 status = "reserved"; 1921 }; 1922 1923 watchdog12: watchdog@2330000 { 1924 compatible = "ti,j7-rti-wdt"; 1925 reg = <0x00 0x2330000 0x00 0x100>; 1926 clocks = <&k3_clks 359 1>; 1927 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 1928 assigned-clocks = <&k3_clks 359 0>; 1929 assigned-clock-parents = <&k3_clks 359 4>; 1930 /* reserved for C7X_3 DSP */ 1931 status = "reserved"; 1932 }; 1933 1934 watchdog13: watchdog@23c0000 { 1935 compatible = "ti,j7-rti-wdt"; 1936 reg = <0x00 0x23c0000 0x00 0x100>; 1937 clocks = <&k3_clks 361 1>; 1938 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 1939 assigned-clocks = <&k3_clks 361 0>; 1940 assigned-clock-parents = <&k3_clks 361 4>; 1941 /* reserved for MAIN_R5F0_0 */ 1942 status = "reserved"; 1943 }; 1944 1945 watchdog14: watchdog@23d0000 { 1946 compatible = "ti,j7-rti-wdt"; 1947 reg = <0x00 0x23d0000 0x00 0x100>; 1948 clocks = <&k3_clks 362 1>; 1949 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 1950 assigned-clocks = <&k3_clks 362 0>; 1951 assigned-clock-parents = <&k3_clks 362 4>; 1952 /* reserved for MAIN_R5F0_1 */ 1953 status = "reserved"; 1954 }; 1955 1956 watchdog15: watchdog@23e0000 { 1957 compatible = "ti,j7-rti-wdt"; 1958 reg = <0x00 0x23e0000 0x00 0x100>; 1959 clocks = <&k3_clks 363 1>; 1960 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 1961 assigned-clocks = <&k3_clks 363 0>; 1962 assigned-clock-parents = <&k3_clks 363 4>; 1963 /* reserved for MAIN_R5F1_0 */ 1964 status = "reserved"; 1965 }; 1966 1967 watchdog16: watchdog@23f0000 { 1968 compatible = "ti,j7-rti-wdt"; 1969 reg = <0x00 0x23f0000 0x00 0x100>; 1970 clocks = <&k3_clks 364 1>; 1971 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 1972 assigned-clocks = <&k3_clks 364 0>; 1973 assigned-clock-parents = <&k3_clks 364 4>; 1974 /* reserved for MAIN_R5F1_1 */ 1975 status = "reserved"; 1976 }; 1977 1978 watchdog17: watchdog@2540000 { 1979 compatible = "ti,j7-rti-wdt"; 1980 reg = <0x00 0x2540000 0x00 0x100>; 1981 clocks = <&k3_clks 365 1>; 1982 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1983 assigned-clocks = <&k3_clks 365 0>; 1984 assigned-clock-parents = <&k3_clks 366 4>; 1985 /* reserved for MAIN_R5F2_0 */ 1986 status = "reserved"; 1987 }; 1988 1989 watchdog18: watchdog@2550000 { 1990 compatible = "ti,j7-rti-wdt"; 1991 reg = <0x00 0x2550000 0x00 0x100>; 1992 clocks = <&k3_clks 366 1>; 1993 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 1994 assigned-clocks = <&k3_clks 366 0>; 1995 assigned-clock-parents = <&k3_clks 366 4>; 1996 /* reserved for MAIN_R5F2_1 */ 1997 status = "reserved"; 1998 }; 1999 2000 mhdp: bridge@a000000 { 2001 compatible = "ti,j721e-mhdp8546"; 2002 reg = <0x0 0xa000000 0x0 0x30a00>, 2003 <0x0 0x4f40000 0x0 0x20>; 2004 reg-names = "mhdptx", "j721e-intg"; 2005 clocks = <&k3_clks 217 11>; 2006 interrupt-parent = <&gic500>; 2007 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2008 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2009 status = "disabled"; 2010 2011 dp0_ports: ports { 2012 #address-cells = <1>; 2013 #size-cells = <0>; 2014 /* Remote-endpoints are on the boards so 2015 * ports are defined in the platform dt file. 2016 */ 2017 }; 2018 }; 2019 2020 dss: dss@4a00000 { 2021 compatible = "ti,j721e-dss"; 2022 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2023 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2024 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2025 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2026 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2027 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2028 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2029 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2030 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2031 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2032 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2033 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2034 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2035 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2036 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2037 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2038 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2039 reg-names = "common_m", "common_s0", 2040 "common_s1", "common_s2", 2041 "vidl1", "vidl2","vid1","vid2", 2042 "ovr1", "ovr2", "ovr3", "ovr4", 2043 "vp1", "vp2", "vp3", "vp4", 2044 "wb"; 2045 clocks = <&k3_clks 218 0>, 2046 <&k3_clks 218 2>, 2047 <&k3_clks 218 5>, 2048 <&k3_clks 218 14>, 2049 <&k3_clks 218 18>; 2050 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2051 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2052 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2056 interrupt-names = "common_m", 2057 "common_s0", 2058 "common_s1", 2059 "common_s2"; 2060 status = "disabled"; 2061 2062 dss_ports: ports { 2063 /* Ports that DSS drives are platform specific 2064 * so they are defined in platform dt file. 2065 */ 2066 }; 2067 }; 2068}; 2069