1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU102 RevA
4 *
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/input/input.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18#include <dt-bindings/phy/phy.h>
19
20/ {
21	model = "ZynqMP ZCU102 RevA";
22	compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
23
24	aliases {
25		ethernet0 = &gem3;
26		i2c0 = &i2c0;
27		i2c1 = &i2c1;
28		mmc0 = &sdhci1;
29		nvmem0 = &eeprom;
30		rtc0 = &rtc;
31		serial0 = &uart0;
32		serial1 = &uart1;
33		serial2 = &dcc;
34		spi0 = &qspi;
35		usb0 = &usb0;
36	};
37
38	chosen {
39		bootargs = "earlycon";
40		stdout-path = "serial0:115200n8";
41	};
42
43	memory@0 {
44		device_type = "memory";
45		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46	};
47
48	gpio-keys {
49		compatible = "gpio-keys";
50		autorepeat;
51		switch-19 {
52			label = "sw19";
53			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54			linux,code = <KEY_DOWN>;
55			wakeup-source;
56			autorepeat;
57		};
58	};
59
60	leds {
61		compatible = "gpio-leds";
62		heartbeat-led {
63			label = "heartbeat";
64			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65			linux,default-trigger = "heartbeat";
66		};
67	};
68
69	ina226-u76 {
70		compatible = "iio-hwmon";
71		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
72	};
73	ina226-u77 {
74		compatible = "iio-hwmon";
75		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
76	};
77	ina226-u78 {
78		compatible = "iio-hwmon";
79		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
80	};
81	ina226-u87 {
82		compatible = "iio-hwmon";
83		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
84	};
85	ina226-u85 {
86		compatible = "iio-hwmon";
87		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
88	};
89	ina226-u86 {
90		compatible = "iio-hwmon";
91		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
92	};
93	ina226-u93 {
94		compatible = "iio-hwmon";
95		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
96	};
97	ina226-u88 {
98		compatible = "iio-hwmon";
99		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
100	};
101	ina226-u15 {
102		compatible = "iio-hwmon";
103		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
104	};
105	ina226-u92 {
106		compatible = "iio-hwmon";
107		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
108	};
109	ina226-u79 {
110		compatible = "iio-hwmon";
111		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
112	};
113	ina226-u81 {
114		compatible = "iio-hwmon";
115		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
116	};
117	ina226-u80 {
118		compatible = "iio-hwmon";
119		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
120	};
121	ina226-u84 {
122		compatible = "iio-hwmon";
123		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
124	};
125	ina226-u16 {
126		compatible = "iio-hwmon";
127		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
128	};
129	ina226-u65 {
130		compatible = "iio-hwmon";
131		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
132	};
133	ina226-u74 {
134		compatible = "iio-hwmon";
135		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
136	};
137	ina226-u75 {
138		compatible = "iio-hwmon";
139		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
140	};
141
142	/* 48MHz reference crystal */
143	ref48: ref48M {
144		compatible = "fixed-clock";
145		#clock-cells = <0>;
146		clock-frequency = <48000000>;
147	};
148
149	refhdmi: refhdmi {
150		compatible = "fixed-clock";
151		#clock-cells = <0>;
152		clock-frequency = <114285000>;
153	};
154};
155
156&can1 {
157	status = "okay";
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_can1_default>;
160};
161
162&dcc {
163	status = "okay";
164};
165
166&fpd_dma_chan1 {
167	status = "okay";
168};
169
170&fpd_dma_chan2 {
171	status = "okay";
172};
173
174&fpd_dma_chan3 {
175	status = "okay";
176};
177
178&fpd_dma_chan4 {
179	status = "okay";
180};
181
182&fpd_dma_chan5 {
183	status = "okay";
184};
185
186&fpd_dma_chan6 {
187	status = "okay";
188};
189
190&fpd_dma_chan7 {
191	status = "okay";
192};
193
194&fpd_dma_chan8 {
195	status = "okay";
196};
197
198&gem3 {
199	status = "okay";
200	phy-handle = <&phy0>;
201	phy-mode = "rgmii-id";
202	pinctrl-names = "default";
203	pinctrl-0 = <&pinctrl_gem3_default>;
204	mdio: mdio {
205		#address-cells = <1>;
206		#size-cells = <0>;
207		phy0: ethernet-phy@21 {
208			#phy-cells = <1>;
209			compatible = "ethernet-phy-id2000.a231";
210			reg = <21>;
211			ti,rx-internal-delay = <0x8>;
212			ti,tx-internal-delay = <0xa>;
213			ti,fifo-depth = <0x1>;
214			ti,dp83867-rxctrl-strap-quirk;
215			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
216		};
217	};
218};
219
220&gpio {
221	status = "okay";
222	pinctrl-names = "default";
223	pinctrl-0 = <&pinctrl_gpio_default>;
224};
225
226&gpu {
227	status = "okay";
228};
229
230&i2c0 {
231	status = "okay";
232	clock-frequency = <400000>;
233	pinctrl-names = "default", "gpio";
234	pinctrl-0 = <&pinctrl_i2c0_default>;
235	pinctrl-1 = <&pinctrl_i2c0_gpio>;
236	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
237	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
238
239	tca6416_u97: gpio@20 {
240		compatible = "ti,tca6416";
241		reg = <0x20>;
242		gpio-controller; /* IRQ not connected */
243		#gpio-cells = <2>;
244		gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
245				"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
246				"", "", "", "", "", "", "", "", "";
247		gtr-sel0-hog {
248			gpio-hog;
249			gpios = <0 0>;
250			output-low; /* PCIE = 0, DP = 1 */
251			line-name = "sel0";
252		};
253		gtr-sel1-hog {
254			gpio-hog;
255			gpios = <1 0>;
256			output-high; /* PCIE = 0, DP = 1 */
257			line-name = "sel1";
258		};
259		gtr-sel2-hog {
260			gpio-hog;
261			gpios = <2 0>;
262			output-high; /* PCIE = 0, USB0 = 1 */
263			line-name = "sel2";
264		};
265		gtr-sel3-hog {
266			gpio-hog;
267			gpios = <3 0>;
268			output-high; /* PCIE = 0, SATA = 1 */
269			line-name = "sel3";
270		};
271	};
272
273	tca6416_u61: gpio@21 {
274		compatible = "ti,tca6416";
275		reg = <0x21>;
276		gpio-controller; /* IRQ not connected */
277		#gpio-cells = <2>;
278		gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
279				"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
280				"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
281				"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
282	};
283
284	i2c-mux@75 { /* u60 */
285		compatible = "nxp,pca9544";
286		#address-cells = <1>;
287		#size-cells = <0>;
288		reg = <0x75>;
289		i2c@0 {
290			#address-cells = <1>;
291			#size-cells = <0>;
292			reg = <0>;
293			/* PS_PMBUS */
294			u76: ina226@40 { /* u76 */
295				compatible = "ti,ina226";
296				#io-channel-cells = <1>;
297				label = "ina226-u76";
298				reg = <0x40>;
299				shunt-resistor = <5000>;
300			};
301			u77: ina226@41 { /* u77 */
302				compatible = "ti,ina226";
303				#io-channel-cells = <1>;
304				label = "ina226-u77";
305				reg = <0x41>;
306				shunt-resistor = <5000>;
307			};
308			u78: ina226@42 { /* u78 */
309				compatible = "ti,ina226";
310				#io-channel-cells = <1>;
311				label = "ina226-u78";
312				reg = <0x42>;
313				shunt-resistor = <5000>;
314			};
315			u87: ina226@43 { /* u87 */
316				compatible = "ti,ina226";
317				#io-channel-cells = <1>;
318				label = "ina226-u87";
319				reg = <0x43>;
320				shunt-resistor = <5000>;
321			};
322			u85: ina226@44 { /* u85 */
323				compatible = "ti,ina226";
324				#io-channel-cells = <1>;
325				label = "ina226-u85";
326				reg = <0x44>;
327				shunt-resistor = <5000>;
328			};
329			u86: ina226@45 { /* u86 */
330				compatible = "ti,ina226";
331				#io-channel-cells = <1>;
332				label = "ina226-u86";
333				reg = <0x45>;
334				shunt-resistor = <5000>;
335			};
336			u93: ina226@46 { /* u93 */
337				compatible = "ti,ina226";
338				#io-channel-cells = <1>;
339				label = "ina226-u93";
340				reg = <0x46>;
341				shunt-resistor = <5000>;
342			};
343			u88: ina226@47 { /* u88 */
344				compatible = "ti,ina226";
345				#io-channel-cells = <1>;
346				label = "ina226-u88";
347				reg = <0x47>;
348				shunt-resistor = <5000>;
349			};
350			u15: ina226@4a { /* u15 */
351				compatible = "ti,ina226";
352				#io-channel-cells = <1>;
353				label = "ina226-u15";
354				reg = <0x4a>;
355				shunt-resistor = <5000>;
356			};
357			u92: ina226@4b { /* u92 */
358				compatible = "ti,ina226";
359				#io-channel-cells = <1>;
360				label = "ina226-u92";
361				reg = <0x4b>;
362				shunt-resistor = <5000>;
363			};
364		};
365		i2c@1 {
366			#address-cells = <1>;
367			#size-cells = <0>;
368			reg = <1>;
369			/* PL_PMBUS */
370			u79: ina226@40 { /* u79 */
371				compatible = "ti,ina226";
372				#io-channel-cells = <1>;
373				label = "ina226-u79";
374				reg = <0x40>;
375				shunt-resistor = <2000>;
376			};
377			u81: ina226@41 { /* u81 */
378				compatible = "ti,ina226";
379				#io-channel-cells = <1>;
380				label = "ina226-u81";
381				reg = <0x41>;
382				shunt-resistor = <5000>;
383			};
384			u80: ina226@42 { /* u80 */
385				compatible = "ti,ina226";
386				#io-channel-cells = <1>;
387				label = "ina226-u80";
388				reg = <0x42>;
389				shunt-resistor = <5000>;
390			};
391			u84: ina226@43 { /* u84 */
392				compatible = "ti,ina226";
393				#io-channel-cells = <1>;
394				label = "ina226-u84";
395				reg = <0x43>;
396				shunt-resistor = <5000>;
397			};
398			u16: ina226@44 { /* u16 */
399				compatible = "ti,ina226";
400				#io-channel-cells = <1>;
401				label = "ina226-u16";
402				reg = <0x44>;
403				shunt-resistor = <5000>;
404			};
405			u65: ina226@45 { /* u65 */
406				compatible = "ti,ina226";
407				#io-channel-cells = <1>;
408				label = "ina226-u65";
409				reg = <0x45>;
410				shunt-resistor = <5000>;
411			};
412			u74: ina226@46 { /* u74 */
413				compatible = "ti,ina226";
414				#io-channel-cells = <1>;
415				label = "ina226-u74";
416				reg = <0x46>;
417				shunt-resistor = <5000>;
418			};
419			u75: ina226@47 { /* u75 */
420				compatible = "ti,ina226";
421				#io-channel-cells = <1>;
422				label = "ina226-u75";
423				reg = <0x47>;
424				shunt-resistor = <5000>;
425			};
426		};
427		i2c@2 {
428			#address-cells = <1>;
429			#size-cells = <0>;
430			reg = <2>;
431			/* MAXIM_PMBUS - 00 */
432			max15301@a { /* u46 */
433				compatible = "maxim,max15301";
434				reg = <0xa>;
435			};
436			max15303@b { /* u4 */
437				compatible = "maxim,max15303";
438				reg = <0xb>;
439			};
440			max15303@10 { /* u13 */
441				compatible = "maxim,max15303";
442				reg = <0x10>;
443			};
444			max15301@13 { /* u47 */
445				compatible = "maxim,max15301";
446				reg = <0x13>;
447			};
448			max15303@14 { /* u7 */
449				compatible = "maxim,max15303";
450				reg = <0x14>;
451			};
452			max15303@15 { /* u6 */
453				compatible = "maxim,max15303";
454				reg = <0x15>;
455			};
456			max15303@16 { /* u10 */
457				compatible = "maxim,max15303";
458				reg = <0x16>;
459			};
460			max15303@17 { /* u9 */
461				compatible = "maxim,max15303";
462				reg = <0x17>;
463			};
464			max15301@18 { /* u63 */
465				compatible = "maxim,max15301";
466				reg = <0x18>;
467			};
468			max15303@1a { /* u49 */
469				compatible = "maxim,max15303";
470				reg = <0x1a>;
471			};
472			max15303@1d { /* u18 */
473				compatible = "maxim,max15303";
474				reg = <0x1d>;
475			};
476			max15303@20 { /* u8 */
477				compatible = "maxim,max15303";
478				status = "disabled"; /* unreachable */
479				reg = <0x20>;
480			};
481			max20751@72 { /* u95 */
482				compatible = "maxim,max20751";
483				reg = <0x72>;
484			};
485			max20751@73 { /* u96 */
486				compatible = "maxim,max20751";
487				reg = <0x73>;
488			};
489		};
490		/* Bus 3 is not connected */
491	};
492};
493
494&i2c1 {
495	status = "okay";
496	clock-frequency = <400000>;
497	pinctrl-names = "default", "gpio";
498	pinctrl-0 = <&pinctrl_i2c1_default>;
499	pinctrl-1 = <&pinctrl_i2c1_gpio>;
500	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
501	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
502
503	/* PL i2c via PCA9306 - u45 */
504	i2c-mux@74 { /* u34 */
505		compatible = "nxp,pca9548";
506		#address-cells = <1>;
507		#size-cells = <0>;
508		reg = <0x74>;
509		i2c@0 {
510			#address-cells = <1>;
511			#size-cells = <0>;
512			reg = <0>;
513			/*
514			 * IIC_EEPROM 1kB memory which uses 256B blocks
515			 * where every block has different address.
516			 *    0 - 256B address 0x54
517			 * 256B - 512B address 0x55
518			 * 512B - 768B address 0x56
519			 * 768B - 1024B address 0x57
520			 */
521			eeprom: eeprom@54 { /* u23 */
522				compatible = "atmel,24c08";
523				reg = <0x54>;
524			};
525		};
526		i2c@1 {
527			#address-cells = <1>;
528			#size-cells = <0>;
529			reg = <1>;
530			si5341: clock-generator@36 { /* SI5341 - u69 */
531				compatible = "silabs,si5341";
532				reg = <0x36>;
533				#clock-cells = <2>;
534				#address-cells = <1>;
535				#size-cells = <0>;
536				clocks = <&ref48>;
537				clock-names = "xtal";
538				clock-output-names = "si5341";
539
540				si5341_0: out@0 {
541					/* refclk0 for PS-GT, used for DP */
542					reg = <0>;
543					always-on;
544				};
545				si5341_2: out@2 {
546					/* refclk2 for PS-GT, used for USB3 */
547					reg = <2>;
548					always-on;
549				};
550				si5341_3: out@3 {
551					/* refclk3 for PS-GT, used for SATA */
552					reg = <3>;
553					always-on;
554				};
555				si5341_4: out@4 {
556					/* refclk4 for PS-GT, used for PCIE slot */
557					reg = <4>;
558					always-on;
559				};
560				si5341_5: out@5 {
561					/* refclk5 for PS-GT, used for PCIE */
562					reg = <5>;
563					always-on;
564				};
565				si5341_6: out@6 {
566					/* refclk6 PL CLK125 */
567					reg = <6>;
568					always-on;
569				};
570				si5341_7: out@7 {
571					/* refclk7 PL CLK74 */
572					reg = <7>;
573					always-on;
574				};
575				si5341_9: out@9 {
576					/* refclk9 used for PS_REF_CLK 33.3 MHz */
577					reg = <9>;
578					always-on;
579				};
580			};
581		};
582		i2c@2 {
583			#address-cells = <1>;
584			#size-cells = <0>;
585			reg = <2>;
586			si570_1: clock-generator@5d { /* USER SI570 - u42 */
587				#clock-cells = <0>;
588				compatible = "silabs,si570";
589				reg = <0x5d>;
590				temperature-stability = <50>;
591				factory-fout = <300000000>;
592				clock-frequency = <300000000>;
593				clock-output-names = "si570_user";
594			};
595		};
596		i2c@3 {
597			#address-cells = <1>;
598			#size-cells = <0>;
599			reg = <3>;
600			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
601				#clock-cells = <0>;
602				compatible = "silabs,si570";
603				reg = <0x5d>;
604				temperature-stability = <50>; /* copy from zc702 */
605				factory-fout = <156250000>;
606				clock-frequency = <148500000>;
607				clock-output-names = "si570_mgt";
608			};
609		};
610		i2c@4 {
611			#address-cells = <1>;
612			#size-cells = <0>;
613			reg = <4>;
614			/* SI5328 - u20 */
615		};
616		/* 5 - 7 unconnected */
617	};
618
619	i2c-mux@75 {
620		compatible = "nxp,pca9548"; /* u135 */
621		#address-cells = <1>;
622		#size-cells = <0>;
623		reg = <0x75>;
624
625		i2c@0 {
626			#address-cells = <1>;
627			#size-cells = <0>;
628			reg = <0>;
629			/* HPC0_IIC */
630		};
631		i2c@1 {
632			#address-cells = <1>;
633			#size-cells = <0>;
634			reg = <1>;
635			/* HPC1_IIC */
636		};
637		i2c@2 {
638			#address-cells = <1>;
639			#size-cells = <0>;
640			reg = <2>;
641			/* SYSMON */
642		};
643		i2c@3 {
644			#address-cells = <1>;
645			#size-cells = <0>;
646			reg = <3>;
647			/* DDR4 SODIMM */
648		};
649		i2c@4 {
650			#address-cells = <1>;
651			#size-cells = <0>;
652			reg = <4>;
653			/* SEP 3 */
654		};
655		i2c@5 {
656			#address-cells = <1>;
657			#size-cells = <0>;
658			reg = <5>;
659			/* SEP 2 */
660		};
661		i2c@6 {
662			#address-cells = <1>;
663			#size-cells = <0>;
664			reg = <6>;
665			/* SEP 1 */
666		};
667		i2c@7 {
668			#address-cells = <1>;
669			#size-cells = <0>;
670			reg = <7>;
671			/* SEP 0 */
672		};
673	};
674};
675
676&pinctrl0 {
677	status = "okay";
678	pinctrl_i2c0_default: i2c0-default {
679		mux {
680			groups = "i2c0_3_grp";
681			function = "i2c0";
682		};
683
684		conf {
685			groups = "i2c0_3_grp";
686			bias-pull-up;
687			slew-rate = <SLEW_RATE_SLOW>;
688			power-source = <IO_STANDARD_LVCMOS18>;
689		};
690	};
691
692	pinctrl_i2c0_gpio: i2c0-gpio {
693		mux {
694			groups = "gpio0_14_grp", "gpio0_15_grp";
695			function = "gpio0";
696		};
697
698		conf {
699			groups = "gpio0_14_grp", "gpio0_15_grp";
700			slew-rate = <SLEW_RATE_SLOW>;
701			power-source = <IO_STANDARD_LVCMOS18>;
702		};
703	};
704
705	pinctrl_i2c1_default: i2c1-default {
706		mux {
707			groups = "i2c1_4_grp";
708			function = "i2c1";
709		};
710
711		conf {
712			groups = "i2c1_4_grp";
713			bias-pull-up;
714			slew-rate = <SLEW_RATE_SLOW>;
715			power-source = <IO_STANDARD_LVCMOS18>;
716		};
717	};
718
719	pinctrl_i2c1_gpio: i2c1-gpio {
720		mux {
721			groups = "gpio0_16_grp", "gpio0_17_grp";
722			function = "gpio0";
723		};
724
725		conf {
726			groups = "gpio0_16_grp", "gpio0_17_grp";
727			slew-rate = <SLEW_RATE_SLOW>;
728			power-source = <IO_STANDARD_LVCMOS18>;
729		};
730	};
731
732	pinctrl_uart0_default: uart0-default {
733		mux {
734			groups = "uart0_4_grp";
735			function = "uart0";
736		};
737
738		conf {
739			groups = "uart0_4_grp";
740			slew-rate = <SLEW_RATE_SLOW>;
741			power-source = <IO_STANDARD_LVCMOS18>;
742		};
743
744		conf-rx {
745			pins = "MIO18";
746			bias-high-impedance;
747		};
748
749		conf-tx {
750			pins = "MIO19";
751			bias-disable;
752		};
753	};
754
755	pinctrl_uart1_default: uart1-default {
756		mux {
757			groups = "uart1_5_grp";
758			function = "uart1";
759		};
760
761		conf {
762			groups = "uart1_5_grp";
763			slew-rate = <SLEW_RATE_SLOW>;
764			power-source = <IO_STANDARD_LVCMOS18>;
765		};
766
767		conf-rx {
768			pins = "MIO21";
769			bias-high-impedance;
770		};
771
772		conf-tx {
773			pins = "MIO20";
774			bias-disable;
775		};
776	};
777
778	pinctrl_usb0_default: usb0-default {
779		mux {
780			groups = "usb0_0_grp";
781			function = "usb0";
782		};
783
784		conf {
785			groups = "usb0_0_grp";
786			power-source = <IO_STANDARD_LVCMOS18>;
787		};
788
789		conf-rx {
790			pins = "MIO52", "MIO53", "MIO55";
791			bias-high-impedance;
792			drive-strength = <12>;
793			slew-rate = <SLEW_RATE_FAST>;
794		};
795
796		conf-tx {
797			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
798			       "MIO60", "MIO61", "MIO62", "MIO63";
799			bias-disable;
800			drive-strength = <4>;
801			slew-rate = <SLEW_RATE_SLOW>;
802		};
803	};
804
805	pinctrl_gem3_default: gem3-default {
806		mux {
807			function = "ethernet3";
808			groups = "ethernet3_0_grp";
809		};
810
811		conf {
812			groups = "ethernet3_0_grp";
813			slew-rate = <SLEW_RATE_SLOW>;
814			power-source = <IO_STANDARD_LVCMOS18>;
815		};
816
817		conf-rx {
818			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
819									"MIO75";
820			bias-high-impedance;
821			low-power-disable;
822		};
823
824		conf-tx {
825			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
826									"MIO69";
827			bias-disable;
828			low-power-enable;
829		};
830
831		mux-mdio {
832			function = "mdio3";
833			groups = "mdio3_0_grp";
834		};
835
836		conf-mdio {
837			groups = "mdio3_0_grp";
838			slew-rate = <SLEW_RATE_SLOW>;
839			power-source = <IO_STANDARD_LVCMOS18>;
840			bias-disable;
841		};
842	};
843
844	pinctrl_can1_default: can1-default {
845		mux {
846			function = "can1";
847			groups = "can1_6_grp";
848		};
849
850		conf {
851			groups = "can1_6_grp";
852			slew-rate = <SLEW_RATE_SLOW>;
853			power-source = <IO_STANDARD_LVCMOS18>;
854		};
855
856		conf-rx {
857			pins = "MIO25";
858			bias-high-impedance;
859		};
860
861		conf-tx {
862			pins = "MIO24";
863			bias-disable;
864		};
865	};
866
867	pinctrl_sdhci1_default: sdhci1-default {
868		mux {
869			groups = "sdio1_0_grp";
870			function = "sdio1";
871		};
872
873		conf {
874			groups = "sdio1_0_grp";
875			slew-rate = <SLEW_RATE_SLOW>;
876			power-source = <IO_STANDARD_LVCMOS18>;
877			bias-disable;
878		};
879
880		mux-cd {
881			groups = "sdio1_cd_0_grp";
882			function = "sdio1_cd";
883		};
884
885		conf-cd {
886			groups = "sdio1_cd_0_grp";
887			bias-high-impedance;
888			bias-pull-up;
889			slew-rate = <SLEW_RATE_SLOW>;
890			power-source = <IO_STANDARD_LVCMOS18>;
891		};
892
893		mux-wp {
894			groups = "sdio1_wp_0_grp";
895			function = "sdio1_wp";
896		};
897
898		conf-wp {
899			groups = "sdio1_wp_0_grp";
900			bias-high-impedance;
901			bias-pull-up;
902			slew-rate = <SLEW_RATE_SLOW>;
903			power-source = <IO_STANDARD_LVCMOS18>;
904		};
905	};
906
907	pinctrl_gpio_default: gpio-default {
908		mux-sw {
909			function = "gpio0";
910			groups = "gpio0_22_grp", "gpio0_23_grp";
911		};
912
913		conf-sw {
914			groups = "gpio0_22_grp", "gpio0_23_grp";
915			slew-rate = <SLEW_RATE_SLOW>;
916			power-source = <IO_STANDARD_LVCMOS18>;
917		};
918
919		mux-msp {
920			function = "gpio0";
921			groups = "gpio0_13_grp", "gpio0_38_grp";
922		};
923
924		conf-msp {
925			groups = "gpio0_13_grp", "gpio0_38_grp";
926			slew-rate = <SLEW_RATE_SLOW>;
927			power-source = <IO_STANDARD_LVCMOS18>;
928		};
929
930		conf-pull-up {
931			pins = "MIO22", "MIO23";
932			bias-pull-up;
933		};
934
935		conf-pull-none {
936			pins = "MIO13", "MIO38";
937			bias-disable;
938		};
939	};
940};
941
942&pcie {
943	status = "okay";
944};
945
946&psgtr {
947	status = "okay";
948	/* pcie, sata, usb3, dp */
949	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
950	clock-names = "ref0", "ref1", "ref2", "ref3";
951};
952
953&qspi {
954	status = "okay";
955	flash@0 {
956		compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
957		#address-cells = <1>;
958		#size-cells = <1>;
959		reg = <0x0>;
960		spi-tx-bus-width = <4>;
961		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
962		spi-max-frequency = <108000000>; /* Based on DC1 spec */
963	};
964};
965
966&rtc {
967	status = "okay";
968};
969
970&sata {
971	status = "okay";
972	/* SATA OOB timing settings */
973	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
974	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
975	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
976	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
977	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
978	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
979	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
980	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
981	phy-names = "sata-phy";
982	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
983};
984
985/* SD1 with level shifter */
986&sdhci1 {
987	status = "okay";
988	/*
989	 * 1.0 revision has level shifter and this property should be
990	 * removed for supporting UHS mode
991	 */
992	no-1-8-v;
993	pinctrl-names = "default";
994	pinctrl-0 = <&pinctrl_sdhci1_default>;
995	xlnx,mio-bank = <1>;
996};
997
998&uart0 {
999	status = "okay";
1000	pinctrl-names = "default";
1001	pinctrl-0 = <&pinctrl_uart0_default>;
1002};
1003
1004&uart1 {
1005	status = "okay";
1006	pinctrl-names = "default";
1007	pinctrl-0 = <&pinctrl_uart1_default>;
1008};
1009
1010/* ULPI SMSC USB3320 */
1011&usb0 {
1012	status = "okay";
1013	pinctrl-names = "default";
1014	pinctrl-0 = <&pinctrl_usb0_default>;
1015	phy-names = "usb3-phy";
1016	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1017};
1018
1019&dwc3_0 {
1020	status = "okay";
1021	dr_mode = "host";
1022	snps,usb3_lpm_capable;
1023	maximum-speed = "super-speed";
1024};
1025
1026&watchdog0 {
1027	status = "okay";
1028};
1029
1030&xilinx_ams {
1031	status = "okay";
1032};
1033
1034&ams_ps {
1035	status = "okay";
1036};
1037
1038&ams_pl {
1039	status = "okay";
1040};
1041
1042&zynqmp_dpdma {
1043	status = "okay";
1044};
1045
1046&zynqmp_dpsub {
1047	status = "okay";
1048	phy-names = "dp-phy0";
1049	phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
1050};
1051