1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU106 4 * 5 * (C) Copyright 2016 - 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/phy/phy.h> 17 18/ { 19 model = "ZynqMP ZCU106 RevA"; 20 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; 21 22 aliases { 23 ethernet0 = &gem3; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 mmc0 = &sdhci1; 27 rtc0 = &rtc; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &dcc; 31 }; 32 33 chosen { 34 bootargs = "earlycon"; 35 stdout-path = "serial0:115200n8"; 36 }; 37 38 memory@0 { 39 device_type = "memory"; 40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 41 }; 42 43 gpio-keys { 44 compatible = "gpio-keys"; 45 autorepeat; 46 sw19 { 47 label = "sw19"; 48 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 49 linux,code = <KEY_DOWN>; 50 wakeup-source; 51 autorepeat; 52 }; 53 }; 54 55 leds { 56 compatible = "gpio-leds"; 57 heartbeat-led { 58 label = "heartbeat"; 59 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 60 linux,default-trigger = "heartbeat"; 61 }; 62 }; 63 64 ina226-u76 { 65 compatible = "iio-hwmon"; 66 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 67 }; 68 ina226-u77 { 69 compatible = "iio-hwmon"; 70 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 71 }; 72 ina226-u78 { 73 compatible = "iio-hwmon"; 74 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 75 }; 76 ina226-u87 { 77 compatible = "iio-hwmon"; 78 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 79 }; 80 ina226-u85 { 81 compatible = "iio-hwmon"; 82 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 83 }; 84 ina226-u86 { 85 compatible = "iio-hwmon"; 86 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 87 }; 88 ina226-u93 { 89 compatible = "iio-hwmon"; 90 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 91 }; 92 ina226-u88 { 93 compatible = "iio-hwmon"; 94 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 95 }; 96 ina226-u15 { 97 compatible = "iio-hwmon"; 98 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 99 }; 100 ina226-u92 { 101 compatible = "iio-hwmon"; 102 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 103 }; 104 ina226-u79 { 105 compatible = "iio-hwmon"; 106 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 107 }; 108 ina226-u81 { 109 compatible = "iio-hwmon"; 110 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 111 }; 112 ina226-u80 { 113 compatible = "iio-hwmon"; 114 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 115 }; 116 ina226-u84 { 117 compatible = "iio-hwmon"; 118 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 119 }; 120 ina226-u16 { 121 compatible = "iio-hwmon"; 122 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 123 }; 124 ina226-u65 { 125 compatible = "iio-hwmon"; 126 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 127 }; 128 ina226-u74 { 129 compatible = "iio-hwmon"; 130 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 131 }; 132 ina226-u75 { 133 compatible = "iio-hwmon"; 134 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 135 }; 136 137 /* 48MHz reference crystal */ 138 ref48: ref48M { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <48000000>; 142 }; 143 144 refhdmi: refhdmi { 145 compatible = "fixed-clock"; 146 #clock-cells = <0>; 147 clock-frequency = <114285000>; 148 }; 149}; 150 151&can1 { 152 status = "okay"; 153}; 154 155&dcc { 156 status = "okay"; 157}; 158 159&zynqmp_dpdma { 160 status = "okay"; 161}; 162 163&zynqmp_dpsub { 164 status = "okay"; 165 phy-names = "dp-phy0", "dp-phy1"; 166 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 167 <&psgtr 0 PHY_TYPE_DP 1 3>; 168}; 169 170/* fpd_dma clk 667MHz, lpd_dma 500MHz */ 171&fpd_dma_chan1 { 172 status = "okay"; 173}; 174 175&fpd_dma_chan2 { 176 status = "okay"; 177}; 178 179&fpd_dma_chan3 { 180 status = "okay"; 181}; 182 183&fpd_dma_chan4 { 184 status = "okay"; 185}; 186 187&fpd_dma_chan5 { 188 status = "okay"; 189}; 190 191&fpd_dma_chan6 { 192 status = "okay"; 193}; 194 195&fpd_dma_chan7 { 196 status = "okay"; 197}; 198 199&fpd_dma_chan8 { 200 status = "okay"; 201}; 202 203&gem3 { 204 status = "okay"; 205 phy-handle = <&phy0>; 206 phy-mode = "rgmii-id"; 207 phy0: ethernet-phy@c { 208 reg = <0xc>; 209 ti,rx-internal-delay = <0x8>; 210 ti,tx-internal-delay = <0xa>; 211 ti,fifo-depth = <0x1>; 212 ti,dp83867-rxctrl-strap-quirk; 213 }; 214}; 215 216&gpio { 217 status = "okay"; 218}; 219 220&i2c0 { 221 status = "okay"; 222 clock-frequency = <400000>; 223 224 tca6416_u97: gpio@20 { 225 compatible = "ti,tca6416"; 226 reg = <0x20>; 227 gpio-controller; /* interrupt not connected */ 228 #gpio-cells = <2>; 229 /* 230 * IRQ not connected 231 * Lines: 232 * 0 - SFP_SI5328_INT_ALM 233 * 1 - HDMI_SI5328_INT_ALM 234 * 5 - IIC_MUX_RESET_B 235 * 6 - GEM3_EXP_RESET_B 236 * 10 - FMC_HPC0_PRSNT_M2C_B 237 * 11 - FMC_HPC1_PRSNT_M2C_B 238 * 2-4, 7, 12-17 - not connected 239 */ 240 }; 241 242 tca6416_u61: gpio@21 { 243 compatible = "ti,tca6416"; 244 reg = <0x21>; 245 gpio-controller; 246 #gpio-cells = <2>; 247 /* 248 * IRQ not connected 249 * Lines: 250 * 0 - VCCPSPLL_EN 251 * 1 - MGTRAVCC_EN 252 * 2 - MGTRAVTT_EN 253 * 3 - VCCPSDDRPLL_EN 254 * 4 - MIO26_PMU_INPUT_LS 255 * 5 - PL_PMBUS_ALERT 256 * 6 - PS_PMBUS_ALERT 257 * 7 - MAXIM_PMBUS_ALERT 258 * 10 - PL_DDR4_VTERM_EN 259 * 11 - PL_DDR4_VPP_2V5_EN 260 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON 261 * 13 - PS_DIMM_SUSPEND_EN 262 * 14 - PS_DDR4_VTERM_EN 263 * 15 - PS_DDR4_VPP_2V5_EN 264 * 16 - 17 - not connected 265 */ 266 }; 267 268 i2c-mux@75 { /* u60 */ 269 compatible = "nxp,pca9544"; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 reg = <0x75>; 273 i2c@0 { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 reg = <0>; 277 /* PS_PMBUS */ 278 u76: ina226@40 { /* u76 */ 279 compatible = "ti,ina226"; 280 #io-channel-cells = <1>; 281 label = "ina226-u76"; 282 reg = <0x40>; 283 shunt-resistor = <5000>; 284 }; 285 u77: ina226@41 { /* u77 */ 286 compatible = "ti,ina226"; 287 #io-channel-cells = <1>; 288 label = "ina226-u77"; 289 reg = <0x41>; 290 shunt-resistor = <5000>; 291 }; 292 u78: ina226@42 { /* u78 */ 293 compatible = "ti,ina226"; 294 #io-channel-cells = <1>; 295 label = "ina226-u78"; 296 reg = <0x42>; 297 shunt-resistor = <5000>; 298 }; 299 u87: ina226@43 { /* u87 */ 300 compatible = "ti,ina226"; 301 #io-channel-cells = <1>; 302 label = "ina226-u87"; 303 reg = <0x43>; 304 shunt-resistor = <5000>; 305 }; 306 u85: ina226@44 { /* u85 */ 307 compatible = "ti,ina226"; 308 #io-channel-cells = <1>; 309 label = "ina226-u85"; 310 reg = <0x44>; 311 shunt-resistor = <5000>; 312 }; 313 u86: ina226@45 { /* u86 */ 314 compatible = "ti,ina226"; 315 #io-channel-cells = <1>; 316 label = "ina226-u86"; 317 reg = <0x45>; 318 shunt-resistor = <5000>; 319 }; 320 u93: ina226@46 { /* u93 */ 321 compatible = "ti,ina226"; 322 #io-channel-cells = <1>; 323 label = "ina226-u93"; 324 reg = <0x46>; 325 shunt-resistor = <5000>; 326 }; 327 u88: ina226@47 { /* u88 */ 328 compatible = "ti,ina226"; 329 #io-channel-cells = <1>; 330 label = "ina226-u88"; 331 reg = <0x47>; 332 shunt-resistor = <5000>; 333 }; 334 u15: ina226@4a { /* u15 */ 335 compatible = "ti,ina226"; 336 #io-channel-cells = <1>; 337 label = "ina226-u15"; 338 reg = <0x4a>; 339 shunt-resistor = <5000>; 340 }; 341 u92: ina226@4b { /* u92 */ 342 compatible = "ti,ina226"; 343 #io-channel-cells = <1>; 344 label = "ina226-u92"; 345 reg = <0x4b>; 346 shunt-resistor = <5000>; 347 }; 348 }; 349 i2c@1 { 350 #address-cells = <1>; 351 #size-cells = <0>; 352 reg = <1>; 353 /* PL_PMBUS */ 354 u79: ina226@40 { /* u79 */ 355 compatible = "ti,ina226"; 356 #io-channel-cells = <1>; 357 label = "ina226-u79"; 358 reg = <0x40>; 359 shunt-resistor = <2000>; 360 }; 361 u81: ina226@41 { /* u81 */ 362 compatible = "ti,ina226"; 363 #io-channel-cells = <1>; 364 label = "ina226-u81"; 365 reg = <0x41>; 366 shunt-resistor = <5000>; 367 }; 368 u80: ina226@42 { /* u80 */ 369 compatible = "ti,ina226"; 370 #io-channel-cells = <1>; 371 label = "ina226-u80"; 372 reg = <0x42>; 373 shunt-resistor = <5000>; 374 }; 375 u84: ina226@43 { /* u84 */ 376 compatible = "ti,ina226"; 377 #io-channel-cells = <1>; 378 label = "ina226-u84"; 379 reg = <0x43>; 380 shunt-resistor = <5000>; 381 }; 382 u16: ina226@44 { /* u16 */ 383 compatible = "ti,ina226"; 384 #io-channel-cells = <1>; 385 label = "ina226-u16"; 386 reg = <0x44>; 387 shunt-resistor = <5000>; 388 }; 389 u65: ina226@45 { /* u65 */ 390 compatible = "ti,ina226"; 391 #io-channel-cells = <1>; 392 label = "ina226-u65"; 393 reg = <0x45>; 394 shunt-resistor = <5000>; 395 }; 396 u74: ina226@46 { /* u74 */ 397 compatible = "ti,ina226"; 398 #io-channel-cells = <1>; 399 label = "ina226-u74"; 400 reg = <0x46>; 401 shunt-resistor = <5000>; 402 }; 403 u75: ina226@47 { /* u75 */ 404 compatible = "ti,ina226"; 405 #io-channel-cells = <1>; 406 label = "ina226-u75"; 407 reg = <0x47>; 408 shunt-resistor = <5000>; 409 }; 410 }; 411 i2c@2 { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <2>; 415 /* MAXIM_PMBUS - 00 */ 416 max15301@a { /* u46 */ 417 compatible = "maxim,max15301"; 418 reg = <0xa>; 419 }; 420 max15303@b { /* u4 */ 421 compatible = "maxim,max15303"; 422 reg = <0xb>; 423 }; 424 max15303@10 { /* u13 */ 425 compatible = "maxim,max15303"; 426 reg = <0x10>; 427 }; 428 max15301@13 { /* u47 */ 429 compatible = "maxim,max15301"; 430 reg = <0x13>; 431 }; 432 max15303@14 { /* u7 */ 433 compatible = "maxim,max15303"; 434 reg = <0x14>; 435 }; 436 max15303@15 { /* u6 */ 437 compatible = "maxim,max15303"; 438 reg = <0x15>; 439 }; 440 max15303@16 { /* u10 */ 441 compatible = "maxim,max15303"; 442 reg = <0x16>; 443 }; 444 max15303@17 { /* u9 */ 445 compatible = "maxim,max15303"; 446 reg = <0x17>; 447 }; 448 max15301@18 { /* u63 */ 449 compatible = "maxim,max15301"; 450 reg = <0x18>; 451 }; 452 max15303@1a { /* u49 */ 453 compatible = "maxim,max15303"; 454 reg = <0x1a>; 455 }; 456 max15303@1b { /* u8 */ 457 compatible = "maxim,max15303"; 458 reg = <0x1b>; 459 }; 460 max15303@1d { /* u18 */ 461 compatible = "maxim,max15303"; 462 reg = <0x1d>; 463 }; 464 465 max20751@72 { /* u95 */ 466 compatible = "maxim,max20751"; 467 reg = <0x72>; 468 }; 469 max20751@73 { /* u96 */ 470 compatible = "maxim,max20751"; 471 reg = <0x73>; 472 }; 473 }; 474 /* Bus 3 is not connected */ 475 }; 476}; 477 478&i2c1 { 479 status = "okay"; 480 clock-frequency = <400000>; 481 482 /* PL i2c via PCA9306 - u45 */ 483 i2c-mux@74 { /* u34 */ 484 compatible = "nxp,pca9548"; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <0x74>; 488 i2c@0 { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 reg = <0>; 492 /* 493 * IIC_EEPROM 1kB memory which uses 256B blocks 494 * where every block has different address. 495 * 0 - 256B address 0x54 496 * 256B - 512B address 0x55 497 * 512B - 768B address 0x56 498 * 768B - 1024B address 0x57 499 */ 500 eeprom: eeprom@54 { /* u23 */ 501 compatible = "atmel,24c08"; 502 reg = <0x54>; 503 }; 504 }; 505 i2c@1 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <1>; 509 si5341: clock-generator@36 { /* SI5341 - u69 */ 510 compatible = "silabs,si5341"; 511 reg = <0x36>; 512 #clock-cells = <2>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&ref48>; 516 clock-names = "xtal"; 517 clock-output-names = "si5341"; 518 519 si5341_0: out@0 { 520 /* refclk0 for PS-GT, used for DP */ 521 reg = <0>; 522 always-on; 523 }; 524 si5341_2: out@2 { 525 /* refclk2 for PS-GT, used for USB3 */ 526 reg = <2>; 527 always-on; 528 }; 529 si5341_3: out@3 { 530 /* refclk3 for PS-GT, used for SATA */ 531 reg = <3>; 532 always-on; 533 }; 534 si5341_6: out@6 { 535 /* refclk6 PL CLK125 */ 536 reg = <6>; 537 always-on; 538 }; 539 si5341_7: out@7 { 540 /* refclk7 PL CLK74 */ 541 reg = <7>; 542 always-on; 543 }; 544 si5341_9: out@9 { 545 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 546 reg = <9>; 547 always-on; 548 }; 549 }; 550 551 }; 552 i2c@2 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <2>; 556 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 557 #clock-cells = <0>; 558 compatible = "silabs,si570"; 559 reg = <0x5d>; 560 temperature-stability = <50>; 561 factory-fout = <300000000>; 562 clock-frequency = <300000000>; 563 clock-output-names = "si570_user"; 564 }; 565 }; 566 i2c@3 { 567 #address-cells = <1>; 568 #size-cells = <0>; 569 reg = <3>; 570 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 571 #clock-cells = <0>; 572 compatible = "silabs,si570"; 573 reg = <0x5d>; 574 temperature-stability = <50>; /* copy from zc702 */ 575 factory-fout = <156250000>; 576 clock-frequency = <148500000>; 577 clock-output-names = "si570_mgt"; 578 }; 579 }; 580 i2c@4 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 reg = <4>; 584 /* SI5328 - u20 */ 585 }; 586 i2c@5 { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 reg = <5>; /* FAN controller */ 590 temp@4c {/* lm96163 - u128 */ 591 compatible = "national,lm96163"; 592 reg = <0x4c>; 593 }; 594 }; 595 /* 6 - 7 unconnected */ 596 }; 597 598 i2c-mux@75 { 599 compatible = "nxp,pca9548"; /* u135 */ 600 #address-cells = <1>; 601 #size-cells = <0>; 602 reg = <0x75>; 603 604 i2c@0 { 605 #address-cells = <1>; 606 #size-cells = <0>; 607 reg = <0>; 608 /* HPC0_IIC */ 609 }; 610 i2c@1 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 reg = <1>; 614 /* HPC1_IIC */ 615 }; 616 i2c@2 { 617 #address-cells = <1>; 618 #size-cells = <0>; 619 reg = <2>; 620 /* SYSMON */ 621 }; 622 i2c@3 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 reg = <3>; 626 /* DDR4 SODIMM */ 627 }; 628 i2c@4 { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 reg = <4>; 632 /* SEP 3 */ 633 }; 634 i2c@5 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 reg = <5>; 638 /* SEP 2 */ 639 }; 640 i2c@6 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 reg = <6>; 644 /* SEP 1 */ 645 }; 646 i2c@7 { 647 #address-cells = <1>; 648 #size-cells = <0>; 649 reg = <7>; 650 /* SEP 0 */ 651 }; 652 }; 653}; 654 655&psgtr { 656 status = "okay"; 657 /* nc, sata, usb3, dp */ 658 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 659 clock-names = "ref1", "ref2", "ref3"; 660}; 661 662&rtc { 663 status = "okay"; 664}; 665 666&sata { 667 status = "okay"; 668 /* SATA OOB timing settings */ 669 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 670 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 671 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 672 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 673 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 674 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 675 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 676 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 677 phy-names = "sata-phy"; 678 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 679}; 680 681/* SD1 with level shifter */ 682&sdhci1 { 683 status = "okay"; 684 no-1-8-v; 685 xlnx,mio-bank = <1>; 686}; 687 688&uart0 { 689 status = "okay"; 690}; 691 692&uart1 { 693 status = "okay"; 694}; 695 696/* ULPI SMSC USB3320 */ 697&usb0 { 698 status = "okay"; 699 dr_mode = "host"; 700}; 701 702&watchdog0 { 703 status = "okay"; 704}; 705