1// SPDX-License-Identifier: GPL-2.0
2
3#include "dt-bindings/clock/bcm63268-clock.h"
4#include "dt-bindings/reset/bcm63268-reset.h"
5#include "dt-bindings/soc/bcm63268-pm.h"
6
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10	compatible = "brcm,bcm63268";
11
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		mips-hpt-frequency = <200000000>;
17
18		cpu@0 {
19			compatible = "brcm,bmips4350";
20			device_type = "cpu";
21			reg = <0>;
22		};
23
24		cpu@1 {
25			compatible = "brcm,bmips4350";
26			device_type = "cpu";
27			reg = <1>;
28		};
29	};
30
31	clocks {
32		periph_osc: periph-osc {
33			compatible = "fixed-clock";
34			#clock-cells = <0>;
35			clock-frequency = <50000000>;
36			clock-output-names = "periph";
37		};
38
39		hsspi_osc: hsspi-osc {
40			compatible = "fixed-clock";
41
42			#clock-cells = <0>;
43
44			clock-frequency = <400000000>;
45			clock-output-names = "hsspi_osc";
46		};
47	};
48
49	aliases {
50		nflash = &nflash;
51		serial0 = &uart0;
52		serial1 = &uart1;
53		spi0 = &lsspi;
54		spi1 = &hsspi;
55	};
56
57	cpu_intc: interrupt-controller {
58		#address-cells = <0>;
59		compatible = "mti,cpu-interrupt-controller";
60
61		interrupt-controller;
62		#interrupt-cells = <1>;
63	};
64
65	ubus {
66		#address-cells = <1>;
67		#size-cells = <1>;
68
69		compatible = "simple-bus";
70		ranges;
71
72		periph_clk: clock-controller@10000004 {
73			compatible = "brcm,bcm63268-clocks";
74			reg = <0x10000004 0x4>;
75			#clock-cells = <1>;
76		};
77
78		pll_cntl: syscon@10000008 {
79			compatible = "syscon";
80			reg = <0x10000008 0x4>;
81			native-endian;
82
83			reboot {
84				compatible = "syscon-reboot";
85				offset = <0x0>;
86				mask = <0x1>;
87			};
88		};
89
90		periph_rst: reset-controller@10000010 {
91			compatible = "brcm,bcm6345-reset";
92			reg = <0x10000010 0x4>;
93			#reset-cells = <1>;
94		};
95
96		periph_intc: interrupt-controller@10000020 {
97			compatible = "brcm,bcm6345-l1-intc";
98			reg = <0x10000020 0x20>,
99			      <0x10000040 0x20>;
100
101			interrupt-controller;
102			#interrupt-cells = <1>;
103
104			interrupt-parent = <&cpu_intc>;
105			interrupts = <2>, <3>;
106		};
107
108		wdt: watchdog@1000009c {
109			compatible = "brcm,bcm7038-wdt";
110			reg = <0x1000009c 0xc>;
111
112			clocks = <&periph_osc>;
113			clock-names = "refclk";
114
115			timeout-sec = <30>;
116		};
117
118		uart0: serial@10000180 {
119			compatible = "brcm,bcm6345-uart";
120			reg = <0x10000180 0x18>;
121
122			interrupt-parent = <&periph_intc>;
123			interrupts = <5>;
124
125			clocks = <&periph_osc>;
126			clock-names = "refclk";
127
128			status = "disabled";
129		};
130
131		nflash: nand@10000200 {
132			#address-cells = <1>;
133			#size-cells = <0>;
134			compatible = "brcm,nand-bcm6368",
135				     "brcm,brcmnand-v4.0",
136				     "brcm,brcmnand";
137			reg = <0x10000200 0x180>,
138			      <0x10000600 0x200>,
139			      <0x100000b0 0x10>;
140			reg-names = "nand",
141				    "nand-cache",
142				    "nand-int-base";
143
144			interrupt-parent = <&periph_intc>;
145			interrupts = <50>;
146
147			clocks = <&periph_clk BCM63268_CLK_NAND>;
148			clock-names = "nand";
149
150			status = "disabled";
151		};
152
153		uart1: serial@100001a0 {
154			compatible = "brcm,bcm6345-uart";
155			reg = <0x100001a0 0x18>;
156
157			interrupt-parent = <&periph_intc>;
158			interrupts = <34>;
159
160			clocks = <&periph_osc>;
161			clock-names = "refclk";
162
163			status = "disabled";
164		};
165
166		lsspi: spi@10000800 {
167			#address-cells = <1>;
168			#size-cells = <0>;
169			compatible = "brcm,bcm6358-spi";
170			reg = <0x10000800 0x70c>;
171
172			interrupt-parent = <&periph_intc>;
173			interrupts = <80>;
174
175			clocks = <&periph_clk BCM63268_CLK_SPI>;
176			clock-names = "spi";
177
178			resets = <&periph_rst BCM63268_RST_SPI>;
179
180			status = "disabled";
181		};
182
183		hsspi: spi@10001000 {
184			#address-cells = <1>;
185			#size-cells = <0>;
186			compatible = "brcm,bcm6328-hsspi";
187			reg = <0x10001000 0x600>;
188
189			interrupt-parent = <&periph_intc>;
190			interrupts = <6>;
191
192			clocks = <&periph_clk BCM63268_CLK_HSSPI>,
193				 <&hsspi_osc>;
194			clock-names = "hsspi",
195				      "pll";
196
197			resets = <&periph_rst BCM63268_RST_SPI>;
198
199			status = "disabled";
200		};
201
202		periph_pwr: power-controller@1000184c {
203			compatible = "brcm,bcm6328-power-controller";
204			reg = <0x1000184c 0x4>;
205			#power-domain-cells = <1>;
206		};
207
208		leds0: led-controller@10001900 {
209			#address-cells = <1>;
210			#size-cells = <0>;
211			compatible = "brcm,bcm6328-leds";
212			reg = <0x10001900 0x24>;
213
214			status = "disabled";
215		};
216
217		ehci: usb@10002500 {
218			compatible = "brcm,bcm63268-ehci", "generic-ehci";
219			reg = <0x10002500 0x100>;
220			big-endian;
221
222			interrupt-parent = <&periph_intc>;
223			interrupts = <10>;
224
225			phys = <&usbh 0>;
226			phy-names = "usb";
227
228			status = "disabled";
229		};
230
231		ohci: usb@10002600 {
232			compatible = "brcm,bcm63268-ohci", "generic-ohci";
233			reg = <0x10002600 0x100>;
234			big-endian;
235			no-big-frame-no;
236
237			interrupt-parent = <&periph_intc>;
238			interrupts = <9>;
239
240			phys = <&usbh 0>;
241			phy-names = "usb";
242
243			status = "disabled";
244		};
245
246		usbh: usb-phy@10002700 {
247			compatible = "brcm,bcm63268-usbh-phy";
248			reg = <0x10002700 0x38>;
249			#phy-cells = <1>;
250
251			clocks = <&periph_clk BCM63268_CLK_USBH>;
252			clock-names = "usbh";
253
254			power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
255
256			resets = <&periph_rst BCM63268_RST_USBH>;
257			reset-names = "usbh";
258
259			status = "disabled";
260		};
261	};
262};
263