1// SPDX-License-Identifier: GPL-2.0
2
3/dts-v1/;
4
5#include <dt-bindings/interrupt-controller/irq.h>
6
7/ {
8	compatible = "loongson,loongson2k1000";
9
10	#address-cells = <2>;
11	#size-cells = <2>;
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu0: cpu@0 {
18			device_type = "cpu";
19			compatible = "loongson,gs264";
20			reg = <0x0>;
21			#clock-cells = <1>;
22			clocks = <&cpu_clk>;
23		};
24	};
25
26	memory {
27		compatible = "memory";
28		device_type = "memory";
29		reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
30			<0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */
31			<0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */
32	};
33
34	cpu_clk: cpu_clk {
35		#clock-cells = <0>;
36		compatible = "fixed-clock";
37		clock-frequency = <800000000>;
38	};
39
40	cpuintc: interrupt-controller {
41		#address-cells = <0>;
42		#interrupt-cells = <1>;
43		interrupt-controller;
44		compatible = "mti,cpu-interrupt-controller";
45	};
46
47	package0: bus@10000000 {
48		compatible = "simple-bus";
49		#address-cells = <2>;
50		#size-cells = <2>;
51		ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
52			0 0x40000000 0 0x40000000 0 0x40000000
53			0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
54
55		liointc0: interrupt-controller@1fe11400 {
56			compatible = "loongson,liointc-2.0";
57			reg = <0 0x1fe11400 0 0x40>,
58				<0 0x1fe11040 0 0x8>,
59				<0 0x1fe11140 0 0x8>;
60			reg-names = "main", "isr0", "isr1";
61
62			interrupt-controller;
63			#interrupt-cells = <2>;
64
65			interrupt-parent = <&cpuintc>;
66			interrupts = <2>;
67			interrupt-names = "int0";
68
69			loongson,parent_int_map = <0xffffffff>, /* int0 */
70						<0x00000000>, /* int1 */
71						<0x00000000>, /* int2 */
72						<0x00000000>; /* int3 */
73		};
74
75		liointc1: interrupt-controller@1fe11440 {
76			compatible = "loongson,liointc-2.0";
77			reg = <0 0x1fe11440 0 0x40>,
78				<0 0x1fe11048 0 0x8>,
79				<0 0x1fe11148 0 0x8>;
80			reg-names = "main", "isr0", "isr1";
81
82			interrupt-controller;
83			#interrupt-cells = <2>;
84
85			interrupt-parent = <&cpuintc>;
86			interrupts = <3>;
87			interrupt-names = "int1";
88
89			loongson,parent_int_map = <0x00000000>, /* int0 */
90						<0xffffffff>, /* int1 */
91						<0x00000000>, /* int2 */
92						<0x00000000>; /* int3 */
93		};
94
95		uart0: serial@1fe00000 {
96			compatible = "ns16550a";
97			reg = <0 0x1fe00000 0 0x8>;
98			clock-frequency = <125000000>;
99			interrupt-parent = <&liointc0>;
100			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
101			no-loopback-test;
102		};
103
104		pci@1a000000 {
105			compatible = "loongson,ls2k-pci";
106			device_type = "pci";
107			#address-cells = <3>;
108			#size-cells = <2>;
109			#interrupt-cells = <2>;
110
111			reg = <0 0x1a000000 0 0x02000000>,
112				<0xfe 0x00000000 0 0x20000000>;
113
114			ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000  0x0 0x00010000>,
115				 <0x02000000 0x0 0x40000000 0x0 0x40000000  0x0 0x40000000>;
116
117			ehci@4,1 {
118				compatible = "pci0014,7a14.0",
119						   "pci0014,7a14",
120						   "pciclass0c0320",
121						   "pciclass0c03";
122
123				reg = <0x2100 0x0 0x0 0x0 0x0>;
124				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
125				interrupt-parent = <&liointc1>;
126			};
127
128			ohci@4,2 {
129				compatible = "pci0014,7a24.0",
130						   "pci0014,7a24",
131						   "pciclass0c0310",
132						   "pciclass0c03";
133
134				reg = <0x2200 0x0 0x0 0x0 0x0>;
135				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
136				interrupt-parent = <&liointc1>;
137			};
138
139			sata@8,0 {
140				compatible = "pci0014,7a08.0",
141						   "pci0014,7a08",
142						   "pciclass010601",
143						   "pciclass0106";
144
145				reg = <0x4000 0x0 0x0 0x0 0x0>;
146				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
147				interrupt-parent = <&liointc0>;
148			};
149
150			pci_bridge@9,0 {
151				compatible = "pci0014,7a19.0",
152						   "pci0014,7a19",
153						   "pciclass060400",
154						   "pciclass0604";
155
156				reg = <0x4800 0x0 0x0 0x0 0x0>;
157				#interrupt-cells = <1>;
158				interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
159				interrupt-parent = <&liointc1>;
160				interrupt-map-mask = <0 0 0 0>;
161				interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
162				external-facing;
163			};
164
165			pci_bridge@a,0 {
166				compatible = "pci0014,7a19.0",
167						   "pci0014,7a19",
168						   "pciclass060400",
169						   "pciclass0604";
170
171				reg = <0x5000 0x0 0x0 0x0 0x0>;
172				#interrupt-cells = <1>;
173				interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
174				interrupt-parent = <&liointc1>;
175				interrupt-map-mask = <0 0 0 0>;
176				interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
177				external-facing;
178			};
179
180			pci_bridge@b,0 {
181				compatible = "pci0014,7a19.0",
182						   "pci0014,7a19",
183						   "pciclass060400",
184						   "pciclass0604";
185
186				reg = <0x5800 0x0 0x0 0x0 0x0>;
187				#interrupt-cells = <1>;
188				interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
189				interrupt-parent = <&liointc1>;
190				interrupt-map-mask = <0 0 0 0>;
191				interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
192				external-facing;
193			};
194
195			pci_bridge@c,0 {
196				compatible = "pci0014,7a19.0",
197						   "pci0014,7a19",
198						   "pciclass060400",
199						   "pciclass0604";
200
201				reg = <0x6000 0x0 0x0 0x0 0x0>;
202				#interrupt-cells = <1>;
203				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
204				interrupt-parent = <&liointc1>;
205				interrupt-map-mask = <0 0 0 0>;
206				interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
207				external-facing;
208			};
209
210			pci_bridge@d,0 {
211				compatible = "pci0014,7a19.0",
212						   "pci0014,7a19",
213						   "pciclass060400",
214						   "pciclass0604";
215
216				reg = <0x6800 0x0 0x0 0x0 0x0>;
217				#interrupt-cells = <1>;
218				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
219				interrupt-parent = <&liointc1>;
220				interrupt-map-mask = <0 0 0 0>;
221				interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
222				external-facing;
223			};
224
225			pci_bridge@e,0 {
226				compatible = "pci0014,7a19.0",
227						   "pci0014,7a19",
228						   "pciclass060400",
229						   "pciclass0604";
230
231				reg = <0x7000 0x0 0x0 0x0 0x0>;
232				#interrupt-cells = <1>;
233				interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
234				interrupt-parent = <&liointc1>;
235				interrupt-map-mask = <0 0 0 0>;
236				interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
237				external-facing;
238			};
239
240		};
241	};
242};
243
244