1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2#include <dt-bindings/interrupt-controller/mips-gic.h>
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/clock/mt7621-clk.h>
5#include <dt-bindings/reset/mt7621-reset.h>
6
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10	compatible = "mediatek,mt7621-soc";
11
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu@0 {
17			device_type = "cpu";
18			compatible = "mips,mips1004Kc";
19			reg = <0>;
20		};
21
22		cpu@1 {
23			device_type = "cpu";
24			compatible = "mips,mips1004Kc";
25			reg = <1>;
26		};
27	};
28
29	cpuintc: cpuintc {
30		#address-cells = <0>;
31		#interrupt-cells = <1>;
32		interrupt-controller;
33		compatible = "mti,cpu-interrupt-controller";
34	};
35
36	aliases {
37		serial0 = &uartlite;
38	};
39
40
41	mmc_fixed_3v3: regulator-3v3 {
42		compatible = "regulator-fixed";
43		regulator-name = "mmc_power";
44		regulator-min-microvolt = <3300000>;
45		regulator-max-microvolt = <3300000>;
46		enable-active-high;
47		regulator-always-on;
48	};
49
50	mmc_fixed_1v8_io: regulator-1v8 {
51		compatible = "regulator-fixed";
52		regulator-name = "mmc_io";
53		regulator-min-microvolt = <1800000>;
54		regulator-max-microvolt = <1800000>;
55		enable-active-high;
56		regulator-always-on;
57	};
58
59	palmbus: palmbus@1e000000 {
60		compatible = "palmbus";
61		reg = <0x1e000000 0x100000>;
62		ranges = <0x0 0x1e000000 0x0fffff>;
63
64		#address-cells = <1>;
65		#size-cells = <1>;
66
67		sysc: syscon@0 {
68			compatible = "mediatek,mt7621-sysc", "syscon";
69			reg = <0x0 0x100>;
70			#clock-cells = <1>;
71			#reset-cells = <1>;
72			ralink,memctl = <&memc>;
73			clock-output-names = "xtal", "cpu", "bus",
74					     "50m", "125m", "150m",
75					     "250m", "270m";
76		};
77
78		wdt: wdt@100 {
79			compatible = "mediatek,mt7621-wdt";
80			reg = <0x100 0x100>;
81		};
82
83		gpio: gpio@600 {
84			#gpio-cells = <2>;
85			#interrupt-cells = <2>;
86			compatible = "mediatek,mt7621-gpio";
87			gpio-controller;
88			gpio-ranges = <&pinctrl 0 0 95>;
89			interrupt-controller;
90			reg = <0x600 0x100>;
91			interrupt-parent = <&gic>;
92			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
93		};
94
95		i2c: i2c@900 {
96			compatible = "mediatek,mt7621-i2c";
97			reg = <0x900 0x100>;
98
99			clocks = <&sysc MT7621_CLK_I2C>;
100			clock-names = "i2c";
101			resets = <&sysc MT7621_RST_I2C>;
102			reset-names = "i2c";
103
104			#address-cells = <1>;
105			#size-cells = <0>;
106
107			status = "disabled";
108
109			pinctrl-names = "default";
110			pinctrl-0 = <&i2c_pins>;
111		};
112
113		memc: syscon@5000 {
114			compatible = "mediatek,mt7621-memc", "syscon";
115			reg = <0x5000 0x1000>;
116		};
117
118		uartlite: uartlite@c00 {
119			compatible = "ns16550a";
120			reg = <0xc00 0x100>;
121
122			clocks = <&sysc MT7621_CLK_UART1>;
123			clock-names = "uart1";
124
125			interrupt-parent = <&gic>;
126			interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
127
128			reg-shift = <2>;
129			reg-io-width = <4>;
130			no-loopback-test;
131		};
132
133		spi0: spi@b00 {
134			status = "disabled";
135
136			compatible = "ralink,mt7621-spi";
137			reg = <0xb00 0x100>;
138
139			clocks = <&sysc MT7621_CLK_SPI>;
140			clock-names = "spi";
141
142			resets = <&sysc MT7621_RST_SPI>;
143			reset-names = "spi";
144
145			#address-cells = <1>;
146			#size-cells = <0>;
147
148			pinctrl-names = "default";
149			pinctrl-0 = <&spi_pins>;
150		};
151	};
152
153	pinctrl: pinctrl {
154		compatible = "ralink,mt7621-pinctrl";
155
156		i2c_pins: i2c0-pins {
157			pinmux {
158				groups = "i2c";
159				function = "i2c";
160			};
161		};
162
163		spi_pins: spi0-pins {
164			pinmux {
165				groups = "spi";
166				function = "spi";
167			};
168		};
169
170		uart1_pins: uart1-pins {
171			pinmux {
172				groups = "uart1";
173				function = "uart1";
174			};
175		};
176
177		uart2_pins: uart2-pins {
178			pinmux {
179				groups = "uart2";
180				function = "uart2";
181			};
182		};
183
184		uart3_pins: uart3-pins {
185			pinmux {
186				groups = "uart3";
187				function = "uart3";
188			};
189		};
190
191		rgmii1_pins: rgmii1-pins {
192			pinmux {
193				groups = "rgmii1";
194				function = "rgmii1";
195			};
196		};
197
198		rgmii2_pins: rgmii2-pins {
199			pinmux {
200				groups = "rgmii2";
201				function = "rgmii2";
202			};
203		};
204
205		mdio_pins: mdio0-pins {
206			pinmux {
207				groups = "mdio";
208				function = "mdio";
209			};
210		};
211
212		pcie_pins: pcie0-pins {
213			pinmux {
214				groups = "pcie";
215				function = "gpio";
216			};
217		};
218
219		nand_pins: nand0-pins {
220			spi-pinmux {
221				groups = "spi";
222				function = "nand1";
223			};
224
225			sdhci-pinmux {
226				groups = "sdhci";
227				function = "nand2";
228			};
229		};
230
231		sdhci_pins: sdhci0-pins {
232			pinmux {
233				groups = "sdhci";
234				function = "sdhci";
235			};
236		};
237	};
238
239	sdhci: sdhci@1e130000 {
240		status = "disabled";
241
242		compatible = "mediatek,mt7620-mmc";
243		reg = <0x1e130000 0x4000>;
244
245		bus-width = <4>;
246		max-frequency = <48000000>;
247		cap-sd-highspeed;
248		cap-mmc-highspeed;
249		vmmc-supply = <&mmc_fixed_3v3>;
250		vqmmc-supply = <&mmc_fixed_1v8_io>;
251		disable-wp;
252
253		pinctrl-names = "default", "state_uhs";
254		pinctrl-0 = <&sdhci_pins>;
255		pinctrl-1 = <&sdhci_pins>;
256
257		clocks = <&sysc MT7621_CLK_SHXC>,
258			 <&sysc MT7621_CLK_50M>;
259		clock-names = "source", "hclk";
260
261		interrupt-parent = <&gic>;
262		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
263	};
264
265	xhci: xhci@1e1c0000 {
266		compatible = "mediatek,mt8173-xhci";
267		reg = <0x1e1c0000 0x1000
268		       0x1e1d0700 0x0100>;
269		reg-names = "mac", "ippc";
270
271		clocks = <&sysc MT7621_CLK_XTAL>;
272		clock-names = "sys_ck";
273
274		interrupt-parent = <&gic>;
275		interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
276	};
277
278	gic: interrupt-controller@1fbc0000 {
279		compatible = "mti,gic";
280		reg = <0x1fbc0000 0x2000>;
281
282		interrupt-controller;
283		#interrupt-cells = <3>;
284
285		mti,reserved-cpu-vectors = <7>;
286
287		timer {
288			compatible = "mti,gic-timer";
289			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
290			clocks = <&sysc MT7621_CLK_CPU>;
291		};
292	};
293
294	cpc: cpc@1fbf0000 {
295		compatible = "mti,mips-cpc";
296		reg = <0x1fbf0000 0x8000>;
297	};
298
299	cdmm: cdmm@1fbf8000 {
300		compatible = "mti,mips-cdmm";
301		reg = <0x1fbf8000 0x8000>;
302	};
303
304	ethernet: ethernet@1e100000 {
305		compatible = "mediatek,mt7621-eth";
306		reg = <0x1e100000 0x10000>;
307
308		clocks = <&sysc MT7621_CLK_FE>,
309			 <&sysc MT7621_CLK_ETH>;
310		clock-names = "fe", "ethif";
311
312		#address-cells = <1>;
313		#size-cells = <0>;
314
315		resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
316		reset-names = "fe", "eth";
317
318		interrupt-parent = <&gic>;
319		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
320
321		mediatek,ethsys = <&sysc>;
322
323		pinctrl-names = "default";
324		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
325
326		gmac0: mac@0 {
327			compatible = "mediatek,eth-mac";
328			reg = <0>;
329			phy-mode = "trgmii";
330
331			fixed-link {
332				speed = <1000>;
333				full-duplex;
334				pause;
335			};
336		};
337
338		gmac1: mac@1 {
339			compatible = "mediatek,eth-mac";
340			reg = <1>;
341			status = "off";
342			phy-mode = "rgmii-rxid";
343		};
344
345		mdio: mdio-bus {
346			#address-cells = <1>;
347			#size-cells = <0>;
348
349			switch0: switch0@0 {
350				compatible = "mediatek,mt7621";
351				reg = <0>;
352				mediatek,mcm;
353				resets = <&sysc MT7621_RST_MCM>;
354				reset-names = "mcm";
355				interrupt-controller;
356				#interrupt-cells = <1>;
357				interrupt-parent = <&gic>;
358				interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
359
360				ports {
361					#address-cells = <1>;
362					#size-cells = <0>;
363
364					port@0 {
365						status = "off";
366						reg = <0>;
367						label = "lan0";
368					};
369
370					port@1 {
371						status = "off";
372						reg = <1>;
373						label = "lan1";
374					};
375
376					port@2 {
377						status = "off";
378						reg = <2>;
379						label = "lan2";
380					};
381
382					port@3 {
383						status = "off";
384						reg = <3>;
385						label = "lan3";
386					};
387
388					port@4 {
389						status = "off";
390						reg = <4>;
391						label = "lan4";
392					};
393
394					port@6 {
395						reg = <6>;
396						label = "cpu";
397						ethernet = <&gmac0>;
398						phy-mode = "trgmii";
399
400						fixed-link {
401							speed = <1000>;
402							full-duplex;
403							pause;
404						};
405					};
406				};
407			};
408		};
409	};
410
411	pcie: pcie@1e140000 {
412		compatible = "mediatek,mt7621-pci";
413		reg = <0x1e140000 0x100>, /* host-pci bridge registers */
414		      <0x1e142000 0x100>, /* pcie port 0 RC control registers */
415		      <0x1e143000 0x100>, /* pcie port 1 RC control registers */
416		      <0x1e144000 0x100>; /* pcie port 2 RC control registers */
417		#address-cells = <3>;
418		#size-cells = <2>;
419
420		pinctrl-names = "default";
421		pinctrl-0 = <&pcie_pins>;
422
423		device_type = "pci";
424
425		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
426			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
427
428		#interrupt-cells = <1>;
429		interrupt-map-mask = <0xF800 0 0 0>;
430		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
431				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
432				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
433
434		status = "disabled";
435
436		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
437
438		pcie@0,0 {
439			reg = <0x0000 0 0 0 0>;
440			#address-cells = <3>;
441			#size-cells = <2>;
442			device_type = "pci";
443			#interrupt-cells = <1>;
444			interrupt-map-mask = <0 0 0 0>;
445			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
446			resets = <&sysc MT7621_RST_PCIE0>;
447			clocks = <&sysc MT7621_CLK_PCIE0>;
448			phys = <&pcie0_phy 1>;
449			phy-names = "pcie-phy0";
450			ranges;
451		};
452
453		pcie@1,0 {
454			reg = <0x0800 0 0 0 0>;
455			#address-cells = <3>;
456			#size-cells = <2>;
457			device_type = "pci";
458			#interrupt-cells = <1>;
459			interrupt-map-mask = <0 0 0 0>;
460			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
461			resets = <&sysc MT7621_RST_PCIE1>;
462			clocks = <&sysc MT7621_CLK_PCIE1>;
463			phys = <&pcie0_phy 1>;
464			phy-names = "pcie-phy1";
465			ranges;
466		};
467
468		pcie@2,0 {
469			reg = <0x1000 0 0 0 0>;
470			#address-cells = <3>;
471			#size-cells = <2>;
472			device_type = "pci";
473			#interrupt-cells = <1>;
474			interrupt-map-mask = <0 0 0 0>;
475			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
476			resets = <&sysc MT7621_RST_PCIE2>;
477			clocks = <&sysc MT7621_CLK_PCIE2>;
478			phys = <&pcie2_phy 0>;
479			phy-names = "pcie-phy2";
480			ranges;
481		};
482	};
483
484	pcie0_phy: pcie-phy@1e149000 {
485		compatible = "mediatek,mt7621-pci-phy";
486		reg = <0x1e149000 0x0700>;
487		clocks = <&sysc MT7621_CLK_XTAL>;
488		#phy-cells = <1>;
489	};
490
491	pcie2_phy: pcie-phy@1e14a000 {
492		compatible = "mediatek,mt7621-pci-phy";
493		reg = <0x1e14a000 0x0700>;
494		clocks = <&sysc MT7621_CLK_XTAL>;
495		#phy-cells = <1>;
496	};
497};
498