1/dts-v1/;
2/ {
3	compatible = "andestech,ae3xx";
4	#address-cells = <1>;
5	#size-cells = <1>;
6	interrupt-parent = <&intc>;
7
8	chosen {
9		stdout-path = &serial0;
10	};
11
12	memory@0 {
13		device_type = "memory";
14		reg = <0x00000000 0x40000000>;
15	};
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20		cpu@0 {
21			device_type = "cpu";
22			compatible = "andestech,n13", "andestech,nds32v3";
23			reg = <0>;
24			clock-frequency = <60000000>;
25			next-level-cache = <&L2>;
26		};
27	};
28
29	intc: interrupt-controller {
30		compatible = "andestech,ativic32";
31		#interrupt-cells = <1>;
32		interrupt-controller;
33	};
34
35	clock: clk {
36		#clock-cells = <0>;
37		compatible = "fixed-clock";
38		clock-frequency = <30000000>;
39	};
40
41	apb {
42		compatible = "simple-bus";
43		#address-cells = <1>;
44		#size-cells = <1>;
45		ranges;
46
47		serial0: serial@f0300000 {
48			compatible = "andestech,uart16550", "ns16550a";
49			reg = <0xf0300000 0x1000>;
50			interrupts = <8>;
51			clock-frequency = <14745600>;
52			reg-shift = <2>;
53			reg-offset = <32>;
54			no-loopback-test = <1>;
55		};
56
57		timer0: timer@f0400000 {
58			compatible = "andestech,atcpit100";
59			reg = <0xf0400000 0x1000>;
60			interrupts = <2>;
61			clocks = <&clock>;
62			clock-names = "PCLK";
63		};
64	};
65
66	ahb {
67		compatible = "simple-bus";
68		#address-cells = <1>;
69		#size-cells = <1>;
70		ranges;
71
72		L2: cache-controller@e0500000 {
73			compatible = "andestech,atl2c";
74			reg = <0xe0500000 0x1000>;
75			cache-unified;
76			cache-level = <2>;
77		};
78
79		mac0: ethernet@e0100000 {
80			compatible = "andestech,atmac100";
81			reg = <0xe0100000 0x1000>;
82			interrupts = <18>;
83		};
84	};
85
86	pmu {
87		compatible = "andestech,nds32v3-pmu";
88		interrupts= <13>;
89	};
90};
91