1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8541 CDS Device Tree Source
4 *
5 * Copyright 2006, 2008 Freescale Semiconductor Inc.
6 */
7
8/dts-v1/;
9
10/include/ "e500v1_power_isa.dtsi"
11
12/ {
13	model = "MPC8541CDS";
14	compatible = "MPC8541CDS", "MPC85xxCDS";
15	#address-cells = <1>;
16	#size-cells = <1>;
17
18	aliases {
19		ethernet0 = &enet0;
20		ethernet1 = &enet1;
21		serial0 = &serial0;
22		serial1 = &serial1;
23		pci0 = &pci0;
24		pci1 = &pci1;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		PowerPC,8541@0 {
32			device_type = "cpu";
33			reg = <0x0>;
34			d-cache-line-size = <32>;	// 32 bytes
35			i-cache-line-size = <32>;	// 32 bytes
36			d-cache-size = <0x8000>;		// L1, 32K
37			i-cache-size = <0x8000>;		// L1, 32K
38			timebase-frequency = <0>;	//  33 MHz, from uboot
39			bus-frequency = <0>;	// 166 MHz
40			clock-frequency = <0>;	// 825 MHz, from uboot
41			next-level-cache = <&L2>;
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x0 0x8000000>;	// 128M at 0x0
48	};
49
50	soc8541@e0000000 {
51		#address-cells = <1>;
52		#size-cells = <1>;
53		device_type = "soc";
54		compatible = "simple-bus";
55		ranges = <0x0 0xe0000000 0x100000>;
56		bus-frequency = <0>;
57
58		ecm-law@0 {
59			compatible = "fsl,ecm-law";
60			reg = <0x0 0x1000>;
61			fsl,num-laws = <8>;
62		};
63
64		ecm@1000 {
65			compatible = "fsl,mpc8541-ecm", "fsl,ecm";
66			reg = <0x1000 0x1000>;
67			interrupts = <17 2>;
68			interrupt-parent = <&mpic>;
69		};
70
71		memory-controller@2000 {
72			compatible = "fsl,mpc8541-memory-controller";
73			reg = <0x2000 0x1000>;
74			interrupt-parent = <&mpic>;
75			interrupts = <18 2>;
76		};
77
78		L2: l2-cache-controller@20000 {
79			compatible = "fsl,mpc8541-l2-cache-controller";
80			reg = <0x20000 0x1000>;
81			cache-line-size = <32>;	// 32 bytes
82			cache-size = <0x40000>;	// L2, 256K
83			interrupt-parent = <&mpic>;
84			interrupts = <16 2>;
85		};
86
87		i2c@3000 {
88			#address-cells = <1>;
89			#size-cells = <0>;
90			cell-index = <0>;
91			compatible = "fsl-i2c";
92			reg = <0x3000 0x100>;
93			interrupts = <43 2>;
94			interrupt-parent = <&mpic>;
95			dfsrr;
96		};
97
98		dma@21300 {
99			#address-cells = <1>;
100			#size-cells = <1>;
101			compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
102			reg = <0x21300 0x4>;
103			ranges = <0x0 0x21100 0x200>;
104			cell-index = <0>;
105			dma-channel@0 {
106				compatible = "fsl,mpc8541-dma-channel",
107						"fsl,eloplus-dma-channel";
108				reg = <0x0 0x80>;
109				cell-index = <0>;
110				interrupt-parent = <&mpic>;
111				interrupts = <20 2>;
112			};
113			dma-channel@80 {
114				compatible = "fsl,mpc8541-dma-channel",
115						"fsl,eloplus-dma-channel";
116				reg = <0x80 0x80>;
117				cell-index = <1>;
118				interrupt-parent = <&mpic>;
119				interrupts = <21 2>;
120			};
121			dma-channel@100 {
122				compatible = "fsl,mpc8541-dma-channel",
123						"fsl,eloplus-dma-channel";
124				reg = <0x100 0x80>;
125				cell-index = <2>;
126				interrupt-parent = <&mpic>;
127				interrupts = <22 2>;
128			};
129			dma-channel@180 {
130				compatible = "fsl,mpc8541-dma-channel",
131						"fsl,eloplus-dma-channel";
132				reg = <0x180 0x80>;
133				cell-index = <3>;
134				interrupt-parent = <&mpic>;
135				interrupts = <23 2>;
136			};
137		};
138
139		enet0: ethernet@24000 {
140			#address-cells = <1>;
141			#size-cells = <1>;
142			cell-index = <0>;
143			device_type = "network";
144			model = "TSEC";
145			compatible = "gianfar";
146			reg = <0x24000 0x1000>;
147			ranges = <0x0 0x24000 0x1000>;
148			local-mac-address = [ 00 00 00 00 00 00 ];
149			interrupts = <29 2 30 2 34 2>;
150			interrupt-parent = <&mpic>;
151			tbi-handle = <&tbi0>;
152			phy-handle = <&phy0>;
153
154			mdio@520 {
155				#address-cells = <1>;
156				#size-cells = <0>;
157				compatible = "fsl,gianfar-mdio";
158				reg = <0x520 0x20>;
159
160				phy0: ethernet-phy@0 {
161					interrupt-parent = <&mpic>;
162					interrupts = <5 1>;
163					reg = <0x0>;
164				};
165				phy1: ethernet-phy@1 {
166					interrupt-parent = <&mpic>;
167					interrupts = <5 1>;
168					reg = <0x1>;
169				};
170				tbi0: tbi-phy@11 {
171					reg = <0x11>;
172					device_type = "tbi-phy";
173				};
174			};
175		};
176
177		enet1: ethernet@25000 {
178			#address-cells = <1>;
179			#size-cells = <1>;
180			cell-index = <1>;
181			device_type = "network";
182			model = "TSEC";
183			compatible = "gianfar";
184			reg = <0x25000 0x1000>;
185			ranges = <0x0 0x25000 0x1000>;
186			local-mac-address = [ 00 00 00 00 00 00 ];
187			interrupts = <35 2 36 2 40 2>;
188			interrupt-parent = <&mpic>;
189			tbi-handle = <&tbi1>;
190			phy-handle = <&phy1>;
191
192			mdio@520 {
193				#address-cells = <1>;
194				#size-cells = <0>;
195				compatible = "fsl,gianfar-tbi";
196				reg = <0x520 0x20>;
197
198				tbi1: tbi-phy@11 {
199					reg = <0x11>;
200					device_type = "tbi-phy";
201				};
202			};
203		};
204
205		serial0: serial@4500 {
206			cell-index = <0>;
207			device_type = "serial";
208			compatible = "fsl,ns16550", "ns16550";
209			reg = <0x4500 0x100>; 	// reg base, size
210			clock-frequency = <0>; 	// should we fill in in uboot?
211			interrupts = <42 2>;
212			interrupt-parent = <&mpic>;
213		};
214
215		serial1: serial@4600 {
216			cell-index = <1>;
217			device_type = "serial";
218			compatible = "fsl,ns16550", "ns16550";
219			reg = <0x4600 0x100>;	// reg base, size
220			clock-frequency = <0>; 	// should we fill in in uboot?
221			interrupts = <42 2>;
222			interrupt-parent = <&mpic>;
223		};
224
225		crypto@30000 {
226			compatible = "fsl,sec2.0";
227			reg = <0x30000 0x10000>;
228			interrupts = <45 2>;
229			interrupt-parent = <&mpic>;
230			fsl,num-channels = <4>;
231			fsl,channel-fifo-len = <24>;
232			fsl,exec-units-mask = <0x7e>;
233			fsl,descriptor-types-mask = <0x01010ebf>;
234		};
235
236		mpic: pic@40000 {
237			interrupt-controller;
238			#address-cells = <0>;
239			#interrupt-cells = <2>;
240			reg = <0x40000 0x40000>;
241			compatible = "chrp,open-pic";
242			device_type = "open-pic";
243		};
244
245		cpm@919c0 {
246			#address-cells = <1>;
247			#size-cells = <1>;
248			compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
249			reg = <0x919c0 0x30>;
250			ranges;
251
252			muram@80000 {
253				#address-cells = <1>;
254				#size-cells = <1>;
255				ranges = <0x0 0x80000 0x10000>;
256
257				data@0 {
258					compatible = "fsl,cpm-muram-data";
259					reg = <0x0 0x2000 0x9000 0x1000>;
260				};
261			};
262
263			brg@919f0 {
264				compatible = "fsl,mpc8541-brg",
265				             "fsl,cpm2-brg",
266				             "fsl,cpm-brg";
267				reg = <0x919f0 0x10 0x915f0 0x10>;
268			};
269
270			cpmpic: pic@90c00 {
271				interrupt-controller;
272				#address-cells = <0>;
273				#interrupt-cells = <2>;
274				interrupts = <46 2>;
275				interrupt-parent = <&mpic>;
276				reg = <0x90c00 0x80>;
277				compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
278			};
279		};
280	};
281
282	pci0: pci@e0008000 {
283		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
284		interrupt-map = <
285
286			/* IDSEL 0x10 */
287			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
288			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
289			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
290			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
291
292			/* IDSEL 0x11 */
293			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
294			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
295			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
296			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
297
298			/* IDSEL 0x12 (Slot 1) */
299			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
300			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
301			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
302			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
303
304			/* IDSEL 0x13 (Slot 2) */
305			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
306			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
307			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
308			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
309
310			/* IDSEL 0x14 (Slot 3) */
311			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
312			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
313			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
314			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
315
316			/* IDSEL 0x15 (Slot 4) */
317			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
318			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
319			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
320			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
321
322			/* Bus 1 (Tundra Bridge) */
323			/* IDSEL 0x12 (ISA bridge) */
324			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
325			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
326			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
327			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
328		interrupt-parent = <&mpic>;
329		interrupts = <24 2>;
330		bus-range = <0 0>;
331		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
332			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
333		clock-frequency = <66666666>;
334		#interrupt-cells = <1>;
335		#size-cells = <2>;
336		#address-cells = <3>;
337		reg = <0xe0008000 0x1000>;
338		compatible = "fsl,mpc8540-pci";
339		device_type = "pci";
340
341		i8259@19000 {
342			interrupt-controller;
343			device_type = "interrupt-controller";
344			reg = <0x19000 0x0 0x0 0x0 0x1>;
345			#address-cells = <0>;
346			#interrupt-cells = <2>;
347			compatible = "chrp,iic";
348			interrupts = <1>;
349			interrupt-parent = <&pci0>;
350		};
351	};
352
353	pci1: pci@e0009000 {
354		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
355		interrupt-map = <
356
357			/* IDSEL 0x15 */
358			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
359			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
360			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
361			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
362		interrupt-parent = <&mpic>;
363		interrupts = <25 2>;
364		bus-range = <0 0>;
365		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
366			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
367		clock-frequency = <66666666>;
368		#interrupt-cells = <1>;
369		#size-cells = <2>;
370		#address-cells = <3>;
371		reg = <0xe0009000 0x1000>;
372		compatible = "fsl,mpc8540-pci";
373		device_type = "pci";
374	};
375};
376