1/*
2 * T2080PCIe-RDB Board Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *	 notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *	 notice, this list of conditions and the following disclaimer in the
12 *	 documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *	 names of its contributors may be used to endorse or promote products
15 *	 derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36	model = "fsl,T2080RDB";
37	compatible = "fsl,T2080RDB";
38	#address-cells = <2>;
39	#size-cells = <2>;
40	interrupt-parent = <&mpic>;
41
42	reserved-memory {
43		#address-cells = <2>;
44		#size-cells = <2>;
45		ranges;
46
47		bman_fbpr: bman-fbpr {
48			size = <0 0x1000000>;
49			alignment = <0 0x1000000>;
50		};
51		qman_fqd: qman-fqd {
52			size = <0 0x400000>;
53			alignment = <0 0x400000>;
54		};
55		qman_pfdr: qman-pfdr {
56			size = <0 0x2000000>;
57			alignment = <0 0x2000000>;
58		};
59	};
60
61	ifc: localbus@ffe124000 {
62		reg = <0xf 0xfe124000 0 0x2000>;
63		ranges = <0 0 0xf 0xe8000000 0x08000000
64			  2 0 0xf 0xff800000 0x00010000
65			  3 0 0xf 0xffdf0000 0x00008000>;
66
67		nor@0,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70			compatible = "cfi-flash";
71			reg = <0x0 0x0 0x8000000>;
72
73			bank-width = <2>;
74			device-width = <1>;
75		};
76
77		nand@1,0 {
78			#address-cells = <1>;
79			#size-cells = <1>;
80			compatible = "fsl,ifc-nand";
81			reg = <0x2 0x0 0x10000>;
82		};
83
84		boardctrl: board-control@2,0 {
85			#address-cells = <1>;
86			#size-cells = <1>;
87			compatible = "fsl,t2080-cpld";
88			reg = <3 0 0x300>;
89			ranges = <0 3 0 0x300>;
90		};
91	};
92
93	memory {
94		device_type = "memory";
95	};
96
97	dcsr: dcsr@f00000000 {
98		ranges = <0x00000000 0xf 0x00000000 0x01072000>;
99	};
100
101	bportals: bman-portals@ff4000000 {
102		ranges = <0x0 0xf 0xf4000000 0x2000000>;
103	};
104
105	qportals: qman-portals@ff6000000 {
106		ranges = <0x0 0xf 0xf6000000 0x2000000>;
107	};
108
109	soc: soc@ffe000000 {
110		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
111		reg = <0xf 0xfe000000 0 0x00001000>;
112		spi@110000 {
113			flash@0 {
114				#address-cells = <1>;
115				#size-cells = <1>;
116				compatible = "micron,n25q512ax3", "jedec,spi-nor";
117				reg = <0>;
118				spi-max-frequency = <10000000>; /* input clock */
119			};
120		};
121
122		i2c@118000 {
123			adt7481@4c {
124				compatible = "adi,adt7481";
125				reg = <0x4c>;
126			};
127
128			rtc@68 {
129				compatible = "dallas,ds1339";
130				reg = <0x68>;
131				interrupts = <0x1 0x1 0 0>;
132			};
133
134			eeprom@50 {
135				compatible = "atmel,24c256";
136				reg = <0x50>;
137			};
138		};
139
140		i2c@118100 {
141			pca9546@77 {
142				compatible = "nxp,pca9546";
143				reg = <0x77>;
144			};
145		};
146
147		sdhc@114000 {
148			voltage-ranges = <1800 1800 3300 3300>;
149		};
150	};
151
152	pci0: pcie@ffe240000 {
153		reg = <0xf 0xfe240000 0 0x10000>;
154		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
155			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
156		pcie@0 {
157			ranges = <0x02000000 0 0xe0000000
158				  0x02000000 0 0xe0000000
159				  0 0x20000000
160
161				  0x01000000 0 0x00000000
162				  0x01000000 0 0x00000000
163				  0 0x00010000>;
164		};
165	};
166
167	pci1: pcie@ffe250000 {
168		reg = <0xf 0xfe250000 0 0x10000>;
169		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000
170			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
171		pcie@0 {
172			ranges = <0x02000000 0 0xe0000000
173				  0x02000000 0 0xe0000000
174				  0 0x20000000
175
176				  0x01000000 0 0x00000000
177				  0x01000000 0 0x00000000
178				  0 0x00010000>;
179		};
180	};
181
182	pci2: pcie@ffe260000 {
183		reg = <0xf 0xfe260000 0 0x1000>;
184		ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
185			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
186		pcie@0 {
187			ranges = <0x02000000 0 0xe0000000
188				  0x02000000 0 0xe0000000
189				  0 0x20000000
190
191				  0x01000000 0 0x00000000
192				  0x01000000 0 0x00000000
193				  0 0x00010000>;
194		};
195	};
196
197	pci3: pcie@ffe270000 {
198		reg = <0xf 0xfe270000 0 0x10000>;
199		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000
200			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
201		pcie@0 {
202			ranges = <0x02000000 0 0xe0000000
203				  0x02000000 0 0xe0000000
204				  0 0x20000000
205
206				  0x01000000 0 0x00000000
207				  0x01000000 0 0x00000000
208				  0 0x00010000>;
209		};
210	};
211};
212