1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8360E EMDS Device Tree Source
4 *
5 * Copyright 2006 Freescale Semiconductor Inc.
6 */
7
8
9/*
10/memreserve/	00000000 1000000;
11*/
12
13/dts-v1/;
14
15/ {
16	model = "MPC8360MDS";
17	compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	aliases {
22		ethernet0 = &enet0;
23		ethernet1 = &enet1;
24		serial0 = &serial0;
25		serial1 = &serial1;
26		pci0 = &pci0;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		PowerPC,8360@0 {
34			device_type = "cpu";
35			reg = <0x0>;
36			d-cache-line-size = <32>;	// 32 bytes
37			i-cache-line-size = <32>;	// 32 bytes
38			d-cache-size = <32768>;		// L1, 32K
39			i-cache-size = <32768>;		// L1, 32K
40			timebase-frequency = <66000000>;
41			bus-frequency = <264000000>;
42			clock-frequency = <528000000>;
43		};
44	};
45
46	memory {
47		device_type = "memory";
48		reg = <0x00000000 0x10000000>;
49	};
50
51	localbus@e0005000 {
52		#address-cells = <2>;
53		#size-cells = <1>;
54		compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
55			     "simple-bus";
56		reg = <0xe0005000 0xd8>;
57		ranges = <0 0 0xfe000000 0x02000000
58		          1 0 0xf8000000 0x00008000>;
59
60		flash@0,0 {
61			compatible = "cfi-flash";
62			reg = <0 0 0x2000000>;
63			bank-width = <2>;
64			device-width = <1>;
65		};
66
67		bcsr@1,0 {
68			#address-cells = <1>;
69			#size-cells = <1>;
70 			compatible = "fsl,mpc8360mds-bcsr";
71			reg = <1 0 0x8000>;
72			ranges = <0 1 0 0x8000>;
73
74			bcsr13: gpio-controller@d {
75				#gpio-cells = <2>;
76				compatible = "fsl,mpc8360mds-bcsr-gpio";
77				reg = <0xd 1>;
78				gpio-controller;
79			};
80		};
81	};
82
83	soc8360@e0000000 {
84		#address-cells = <1>;
85		#size-cells = <1>;
86		device_type = "soc";
87		compatible = "simple-bus";
88		ranges = <0x0 0xe0000000 0x00100000>;
89		reg = <0xe0000000 0x00000200>;
90		bus-frequency = <264000000>;
91
92		wdt@200 {
93			device_type = "watchdog";
94			compatible = "mpc83xx_wdt";
95			reg = <0x200 0x100>;
96		};
97
98		pmc: power@b00 {
99			compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
100			reg = <0xb00 0x100 0xa00 0x100>;
101			interrupts = <80 0x8>;
102			interrupt-parent = <&ipic>;
103		};
104
105		i2c@3000 {
106			#address-cells = <1>;
107			#size-cells = <0>;
108			cell-index = <0>;
109			compatible = "fsl-i2c";
110			reg = <0x3000 0x100>;
111			interrupts = <14 0x8>;
112			interrupt-parent = <&ipic>;
113			dfsrr;
114
115			rtc@68 {
116				compatible = "dallas,ds1374";
117				reg = <0x68>;
118			};
119		};
120
121		i2c@3100 {
122			#address-cells = <1>;
123			#size-cells = <0>;
124			cell-index = <1>;
125			compatible = "fsl-i2c";
126			reg = <0x3100 0x100>;
127			interrupts = <15 0x8>;
128			interrupt-parent = <&ipic>;
129			dfsrr;
130		};
131
132		serial0: serial@4500 {
133			cell-index = <0>;
134			device_type = "serial";
135			compatible = "fsl,ns16550", "ns16550";
136			reg = <0x4500 0x100>;
137			clock-frequency = <264000000>;
138			interrupts = <9 0x8>;
139			interrupt-parent = <&ipic>;
140		};
141
142		serial1: serial@4600 {
143			cell-index = <1>;
144			device_type = "serial";
145			compatible = "fsl,ns16550", "ns16550";
146			reg = <0x4600 0x100>;
147			clock-frequency = <264000000>;
148			interrupts = <10 0x8>;
149			interrupt-parent = <&ipic>;
150		};
151
152		dma@82a8 {
153			#address-cells = <1>;
154			#size-cells = <1>;
155			compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
156			reg = <0x82a8 4>;
157			ranges = <0 0x8100 0x1a8>;
158			interrupt-parent = <&ipic>;
159			interrupts = <71 8>;
160			cell-index = <0>;
161			dma-channel@0 {
162				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
163				reg = <0 0x80>;
164				cell-index = <0>;
165				interrupt-parent = <&ipic>;
166				interrupts = <71 8>;
167			};
168			dma-channel@80 {
169				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
170				reg = <0x80 0x80>;
171				cell-index = <1>;
172				interrupt-parent = <&ipic>;
173				interrupts = <71 8>;
174			};
175			dma-channel@100 {
176				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
177				reg = <0x100 0x80>;
178				cell-index = <2>;
179				interrupt-parent = <&ipic>;
180				interrupts = <71 8>;
181			};
182			dma-channel@180 {
183				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
184				reg = <0x180 0x28>;
185				cell-index = <3>;
186				interrupt-parent = <&ipic>;
187				interrupts = <71 8>;
188			};
189		};
190
191		crypto@30000 {
192			compatible = "fsl,sec2.0";
193			reg = <0x30000 0x10000>;
194			interrupts = <11 0x8>;
195			interrupt-parent = <&ipic>;
196			fsl,num-channels = <4>;
197			fsl,channel-fifo-len = <24>;
198			fsl,exec-units-mask = <0x7e>;
199			fsl,descriptor-types-mask = <0x01010ebf>;
200			sleep = <&pmc 0x03000000>;
201		};
202
203		ipic: pic@700 {
204			interrupt-controller;
205			#address-cells = <0>;
206			#interrupt-cells = <2>;
207			reg = <0x700 0x100>;
208			device_type = "ipic";
209		};
210
211		par_io@1400 {
212			#address-cells = <1>;
213			#size-cells = <1>;
214			reg = <0x1400 0x100>;
215			ranges = <0 0x1400 0x100>;
216			device_type = "par_io";
217			num-ports = <7>;
218
219			qe_pio_b: gpio-controller@18 {
220				#gpio-cells = <2>;
221				compatible = "fsl,mpc8360-qe-pario-bank",
222					     "fsl,mpc8323-qe-pario-bank";
223				reg = <0x18 0x18>;
224				gpio-controller;
225			};
226
227			pio1: ucc_pin@1 {
228				pio-map = <
229			/* port  pin  dir  open_drain  assignment  has_irq */
230					0  3  1  0  1  0 	/* TxD0 */
231					0  4  1  0  1  0 	/* TxD1 */
232					0  5  1  0  1  0 	/* TxD2 */
233					0  6  1  0  1  0 	/* TxD3 */
234					1  6  1  0  3  0 	/* TxD4 */
235					1  7  1  0  1  0 	/* TxD5 */
236					1  9  1  0  2  0 	/* TxD6 */
237					1  10 1  0  2  0 	/* TxD7 */
238					0  9  2  0  1  0 	/* RxD0 */
239					0  10 2  0  1  0 	/* RxD1 */
240					0  11 2  0  1  0 	/* RxD2 */
241					0  12 2  0  1  0 	/* RxD3 */
242					0  13 2  0  1  0 	/* RxD4 */
243					1  1  2  0  2  0 	/* RxD5 */
244					1  0  2  0  2  0 	/* RxD6 */
245					1  4  2  0  2  0 	/* RxD7 */
246					0  7  1  0  1  0 	/* TX_EN */
247					0  8  1  0  1  0 	/* TX_ER */
248					0  15 2  0  1  0 	/* RX_DV */
249					0  16 2  0  1  0 	/* RX_ER */
250					0  0  2  0  1  0 	/* RX_CLK */
251					2  9  1  0  3  0 	/* GTX_CLK - CLK10 */
252					2  8  2  0  1  0>;	/* GTX125 - CLK9 */
253			};
254			pio2: ucc_pin@2 {
255				pio-map = <
256			/* port  pin  dir  open_drain  assignment  has_irq */
257					0  17 1  0  1  0   /* TxD0 */
258					0  18 1  0  1  0   /* TxD1 */
259					0  19 1  0  1  0   /* TxD2 */
260					0  20 1  0  1  0   /* TxD3 */
261					1  2  1  0  1  0   /* TxD4 */
262					1  3  1  0  2  0   /* TxD5 */
263					1  5  1  0  3  0   /* TxD6 */
264					1  8  1  0  3  0   /* TxD7 */
265					0  23 2  0  1  0   /* RxD0 */
266					0  24 2  0  1  0   /* RxD1 */
267					0  25 2  0  1  0   /* RxD2 */
268					0  26 2  0  1  0   /* RxD3 */
269					0  27 2  0  1  0   /* RxD4 */
270					1  12 2  0  2  0   /* RxD5 */
271					1  13 2  0  3  0   /* RxD6 */
272					1  11 2  0  2  0   /* RxD7 */
273					0  21 1  0  1  0   /* TX_EN */
274					0  22 1  0  1  0   /* TX_ER */
275					0  29 2  0  1  0   /* RX_DV */
276					0  30 2  0  1  0   /* RX_ER */
277					0  31 2  0  1  0   /* RX_CLK */
278					2  2  1  0  2  0   /* GTX_CLK - CLK10 */
279					2  3  2  0  1  0   /* GTX125 - CLK4 */
280					0  1  3  0  2  0   /* MDIO */
281					0  2  1  0  1  0>; /* MDC */
282			};
283
284		};
285	};
286
287	qe@e0100000 {
288		#address-cells = <1>;
289		#size-cells = <1>;
290		device_type = "qe";
291		compatible = "fsl,qe";
292		ranges = <0x0 0xe0100000 0x00100000>;
293		reg = <0xe0100000 0x480>;
294		brg-frequency = <0>;
295		bus-frequency = <396000000>;
296		fsl,qe-num-riscs = <2>;
297		fsl,qe-num-snums = <28>;
298
299		muram@10000 {
300 			#address-cells = <1>;
301 			#size-cells = <1>;
302			compatible = "fsl,qe-muram", "fsl,cpm-muram";
303			ranges = <0x0 0x00010000 0x0000c000>;
304
305			data-only@0 {
306				compatible = "fsl,qe-muram-data",
307					     "fsl,cpm-muram-data";
308				reg = <0x0 0xc000>;
309			};
310		};
311
312		timer@440 {
313			compatible = "fsl,mpc8360-qe-gtm",
314				     "fsl,qe-gtm", "fsl,gtm";
315			reg = <0x440 0x40>;
316			clock-frequency = <132000000>;
317			interrupts = <12 13 14 15>;
318			interrupt-parent = <&qeic>;
319		};
320
321		spi@4c0 {
322			cell-index = <0>;
323			compatible = "fsl,spi";
324			reg = <0x4c0 0x40>;
325			interrupts = <2>;
326			interrupt-parent = <&qeic>;
327			mode = "cpu";
328		};
329
330		spi@500 {
331			cell-index = <1>;
332			compatible = "fsl,spi";
333			reg = <0x500 0x40>;
334			interrupts = <1>;
335			interrupt-parent = <&qeic>;
336			mode = "cpu";
337		};
338
339		usb@6c0 {
340			compatible = "fsl,mpc8360-qe-usb",
341				     "fsl,mpc8323-qe-usb";
342			reg = <0x6c0 0x40 0x8b00 0x100>;
343			interrupts = <11>;
344			interrupt-parent = <&qeic>;
345			fsl,fullspeed-clock = "clk21";
346			fsl,lowspeed-clock = "brg9";
347			gpios = <&qe_pio_b  2 0   /* USBOE */
348				 &qe_pio_b  3 0   /* USBTP */
349				 &qe_pio_b  8 0   /* USBTN */
350				 &qe_pio_b  9 0   /* USBRP */
351				 &qe_pio_b 11 0   /* USBRN */
352				 &bcsr13    5 0   /* SPEED */
353				 &bcsr13    4 1>; /* POWER */
354		};
355
356		enet0: ucc@2000 {
357			device_type = "network";
358			compatible = "ucc_geth";
359			cell-index = <1>;
360			reg = <0x2000 0x200>;
361			interrupts = <32>;
362			interrupt-parent = <&qeic>;
363			local-mac-address = [ 00 00 00 00 00 00 ];
364			rx-clock-name = "none";
365			tx-clock-name = "clk9";
366			phy-handle = <&phy0>;
367			phy-connection-type = "rgmii-id";
368			pio-handle = <&pio1>;
369		};
370
371		enet1: ucc@3000 {
372			device_type = "network";
373			compatible = "ucc_geth";
374			cell-index = <2>;
375			reg = <0x3000 0x200>;
376			interrupts = <33>;
377			interrupt-parent = <&qeic>;
378			local-mac-address = [ 00 00 00 00 00 00 ];
379			rx-clock-name = "none";
380			tx-clock-name = "clk4";
381			phy-handle = <&phy1>;
382			phy-connection-type = "rgmii-id";
383			pio-handle = <&pio2>;
384		};
385
386		mdio@2120 {
387			#address-cells = <1>;
388			#size-cells = <0>;
389			reg = <0x2120 0x18>;
390			compatible = "fsl,ucc-mdio";
391
392			phy0: ethernet-phy@0 {
393				interrupt-parent = <&ipic>;
394				interrupts = <17 0x8>;
395				reg = <0x0>;
396			};
397			phy1: ethernet-phy@1 {
398				interrupt-parent = <&ipic>;
399				interrupts = <18 0x8>;
400				reg = <0x1>;
401			};
402			tbi-phy@2 {
403				device_type = "tbi-phy";
404				reg = <0x2>;
405			};
406		};
407
408		qeic: interrupt-controller@80 {
409			interrupt-controller;
410			compatible = "fsl,qe-ic";
411			#address-cells = <0>;
412			#interrupt-cells = <1>;
413			reg = <0x80 0x80>;
414			big-endian;
415			interrupts = <32 0x8 33 0x8>; // high:32 low:33
416			interrupt-parent = <&ipic>;
417		};
418	};
419
420	pci0: pci@e0008500 {
421		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
422		interrupt-map = <
423
424				/* IDSEL 0x11 AD17 */
425				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
426				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
427				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
428				 0x8800 0x0 0x0 0x4 &ipic 23 0x8
429
430				/* IDSEL 0x12 AD18 */
431				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
432				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
433				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
434				 0x9000 0x0 0x0 0x4 &ipic 21 0x8
435
436				/* IDSEL 0x13 AD19 */
437				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
438				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
439				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
440				 0x9800 0x0 0x0 0x4 &ipic 22 0x8
441
442				/* IDSEL 0x15 AD21*/
443				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
444				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
445				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
446				 0xa800 0x0 0x0 0x4 &ipic 23 0x8
447
448				/* IDSEL 0x16 AD22*/
449				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
450				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
451				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
452				 0xb000 0x0 0x0 0x4 &ipic 22 0x8
453
454				/* IDSEL 0x17 AD23*/
455				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
456				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
457				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
458				 0xb800 0x0 0x0 0x4 &ipic 21 0x8
459
460				/* IDSEL 0x18 AD24*/
461				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
462				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
463				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
464				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
465		interrupt-parent = <&ipic>;
466		interrupts = <66 0x8>;
467		bus-range = <0 0>;
468		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
469			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
470			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
471		clock-frequency = <66666666>;
472		#interrupt-cells = <1>;
473		#size-cells = <2>;
474		#address-cells = <3>;
475		reg = <0xe0008500 0x100		/* internal registers */
476		       0xe0008300 0x8>;		/* config space access registers */
477		compatible = "fsl,mpc8349-pci";
478		device_type = "pci";
479		sleep = <&pmc 0x00010000>;
480	};
481};
482