1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
4 *
5 * Copyright (C) 2006-2009 Pengutronix
6 * Sascha Hauer, Juergen Beisert, Wolfram Sang <kernel@pengutronix.de>
7 */
8
9/include/ "mpc5200b.dtsi"
10
11&gpt0 { fsl,has-wdt; };
12&gpt2 { gpio-controller; };
13&gpt3 { gpio-controller; };
14&gpt4 { gpio-controller; };
15&gpt5 { gpio-controller; };
16&gpt6 { gpio-controller; };
17&gpt7 { gpio-controller; };
18
19/ {
20	model = "phytec,pcm032";
21	compatible = "phytec,pcm032";
22
23	memory@0 {
24		reg = <0x00000000 0x08000000>;	// 128MB
25	};
26
27	soc5200@f0000000 {
28		psc@2000 {	/* PSC1 is ac97 */
29			compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
30			cell-index = <0>;
31		};
32
33		/* PSC2 port is used by CAN1/2 */
34		psc@2200 {
35			status = "disabled";
36		};
37
38		psc@2400 { /* PSC3 in UART mode */
39			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
40		};
41
42		/* PSC4 is ??? */
43		psc@2600 {
44			status = "disabled";
45		};
46
47		/* PSC5 is ??? */
48		psc@2800 {
49			status = "disabled";
50		};
51
52		psc@2c00 { /* PSC6 in UART mode */
53			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54		};
55
56		ethernet@3000 {
57			phy-handle = <&phy0>;
58		};
59
60		mdio@3000 {
61			phy0: ethernet-phy@0 {
62				reg = <0>;
63			};
64		};
65
66		i2c@3d40 {
67			rtc@51 {
68				compatible = "nxp,pcf8563";
69				reg = <0x51>;
70			};
71			eeprom@52 {
72				compatible = "catalyst,24c32", "atmel,24c32";
73				reg = <0x52>;
74				pagesize = <32>;
75			};
76		};
77	};
78
79	pci@f0000d00 {
80		interrupt-map-mask = <0xf800 0 0 7>;
81		interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82				 0xc000 0 0 2 &mpc5200_pic 1 1 3
83				 0xc000 0 0 3 &mpc5200_pic 1 2 3
84				 0xc000 0 0 4 &mpc5200_pic 1 3 3
85
86				 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
87				 0xc800 0 0 2 &mpc5200_pic 1 2 3
88				 0xc800 0 0 3 &mpc5200_pic 1 3 3
89				 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
90		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>,
91			 <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>,
92			 <0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
93	};
94
95	localbus {
96		ranges = <0 0 0xfe000000 0x02000000
97			  1 0 0xfc000000 0x02000000
98			  2 0 0xfbe00000 0x00200000
99			  3 0 0xf9e00000 0x02000000
100			  4 0 0xf7e00000 0x02000000
101			  5 0 0xe6000000 0x02000000
102			  6 0 0xe8000000 0x02000000
103			  7 0 0xea000000 0x02000000>;
104
105		flash@0,0 {
106			compatible = "cfi-flash";
107			reg = <0 0 0x02000000>;
108			bank-width = <4>;
109			#size-cells = <1>;
110			#address-cells = <1>;
111
112			partition@0 {
113				label = "ubootl";
114				reg = <0x00000000 0x00040000>;
115			};
116			partition@40000 {
117				label = "kernel";
118				reg = <0x00040000 0x001c0000>;
119			};
120			partition@200000 {
121				label = "jffs2";
122				reg = <0x00200000 0x01d00000>;
123			};
124			partition@1f00000 {
125				label = "uboot";
126				reg = <0x01f00000 0x00040000>;
127			};
128			partition@1f40000 {
129				label = "env";
130				reg = <0x01f40000 0x00040000>;
131			};
132			partition@1f80000 {
133				label = "oftree";
134				reg = <0x01f80000 0x00040000>;
135			};
136			partition@1fc0000 {
137				label = "space";
138				reg = <0x01fc0000 0x00040000>;
139			};
140		};
141
142		sram@2,0 {
143			compatible = "mtd-ram";
144			reg = <2 0 0x00200000>;
145			bank-width = <2>;
146		};
147
148		/*
149		 * example snippets for FPGA
150		 *
151		 * fpga@3,0 {
152		 *	 compatible = "fpga_driver";
153		 *	 reg = <3 0 0x02000000>;
154		 *	 bank-width = <4>;
155		 * };
156		 *
157		 * fpga@4,0 {
158		 *	 compatible = "fpga_driver";
159		 *	 reg = <4 0 0x02000000>;
160		 *	 bank-width = <4>;
161		 * };
162		 */
163
164		/*
165		 * example snippets for free chipselects
166		 *
167		 * device@5,0 {
168		 *	 compatible = "custom_driver";
169		 *	 reg = <5 0 0x02000000>;
170		 * };
171		 *
172		 * device@6,0 {
173		 *	 compatible = "custom_driver";
174		 *	 reg = <6 0 0x02000000>;
175		 * };
176		 *
177		 * device@7,0 {
178		 *	 compatible = "custom_driver";
179		 *	 reg = <7 0 0x02000000>;
180		 * };
181		 */
182	};
183};
184