1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
4 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
5 */
6#include <dt-bindings/clock/k210-clk.h>
7#include <dt-bindings/pinctrl/k210-fpioa.h>
8#include <dt-bindings/reset/k210-rst.h>
9
10/ {
11	/*
12	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13	 * wide, and the upper half of all addresses is ignored.
14	 */
15	#address-cells = <1>;
16	#size-cells = <1>;
17	compatible = "canaan,kendryte-k210";
18
19	aliases {
20		serial0 = &uarths0;
21		serial1 = &uart1;
22		serial2 = &uart2;
23		serial3 = &uart3;
24	};
25
26	/*
27	 * The K210 has an sv39 MMU following the privileged specification v1.9.
28	 * Since this is a non-ratified draft specification, the kernel does not
29	 * support it and the K210 support enabled only for the !MMU case.
30	 * Be consistent with this by setting the CPUs MMU type to "none".
31	 */
32	cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35		timebase-frequency = <7800000>;
36		cpu0: cpu@0 {
37			device_type = "cpu";
38			compatible = "canaan,k210", "riscv";
39			reg = <0>;
40			riscv,isa = "rv64imafdc";
41			mmu-type = "riscv,none";
42			i-cache-block-size = <64>;
43			i-cache-size = <0x8000>;
44			d-cache-block-size = <64>;
45			d-cache-size = <0x8000>;
46			cpu0_intc: interrupt-controller {
47				#interrupt-cells = <1>;
48				interrupt-controller;
49				compatible = "riscv,cpu-intc";
50			};
51		};
52		cpu1: cpu@1 {
53			device_type = "cpu";
54			compatible = "canaan,k210", "riscv";
55			reg = <1>;
56			riscv,isa = "rv64imafdc";
57			mmu-type = "riscv,none";
58			i-cache-block-size = <64>;
59			i-cache-size = <0x8000>;
60			d-cache-block-size = <64>;
61			d-cache-size = <0x8000>;
62			cpu1_intc: interrupt-controller {
63				#interrupt-cells = <1>;
64				interrupt-controller;
65				compatible = "riscv,cpu-intc";
66			};
67		};
68
69		cpu-map {
70			cluster0 {
71				core0 {
72					cpu = <&cpu0>;
73				};
74
75				core1 {
76					cpu = <&cpu1>;
77				};
78			};
79		};
80	};
81
82	sram: memory@80000000 {
83		device_type = "memory";
84		reg = <0x80000000 0x400000>, /* sram0 4 MiB */
85		      <0x80400000 0x200000>, /* sram1 2 MiB */
86		      <0x80600000 0x200000>; /* aisram 2 MiB */
87	};
88
89	sram_controller: memory-controller {
90		compatible = "canaan,k210-sram";
91		clocks = <&sysclk K210_CLK_SRAM0>,
92			 <&sysclk K210_CLK_SRAM1>,
93			 <&sysclk K210_CLK_AI>;
94		clock-names = "sram0", "sram1", "aisram";
95	};
96
97	clocks {
98		in0: oscillator {
99			compatible = "fixed-clock";
100			#clock-cells = <0>;
101			clock-frequency = <26000000>;
102		};
103	};
104
105	soc {
106		#address-cells = <1>;
107		#size-cells = <1>;
108		compatible = "simple-bus";
109		ranges;
110		interrupt-parent = <&plic0>;
111
112		rom0: nvmem@1000 {
113			reg = <0x1000 0x1000>;
114			read-only;
115		};
116
117		clint0: timer@2000000 {
118			compatible = "canaan,k210-clint", "sifive,clint0";
119			reg = <0x2000000 0xC000>;
120			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
121					      <&cpu1_intc 3>, <&cpu1_intc 7>;
122		};
123
124		plic0: interrupt-controller@c000000 {
125			#interrupt-cells = <1>;
126			#address-cells = <0>;
127			compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
128			reg = <0xC000000 0x4000000>;
129			interrupt-controller;
130			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
131					      <&cpu1_intc 11>, <&cpu1_intc 9>;
132			riscv,ndev = <65>;
133		};
134
135		uarths0: serial@38000000 {
136			compatible = "canaan,k210-uarths", "sifive,uart0";
137			reg = <0x38000000 0x1000>;
138			interrupts = <33>;
139			clocks = <&sysclk K210_CLK_CPU>;
140		};
141
142		gpio0: gpio-controller@38001000 {
143			#interrupt-cells = <2>;
144			#gpio-cells = <2>;
145			compatible = "canaan,k210-gpiohs", "sifive,gpio0";
146			reg = <0x38001000 0x1000>;
147			interrupt-controller;
148			interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
149				     <41>, <42>, <43>, <44>, <45>, <46>, <47>,
150				     <48>, <49>, <50>, <51>, <52>, <53>, <54>,
151				     <55>, <56>, <57>, <58>, <59>, <60>, <61>,
152				     <62>, <63>, <64>, <65>;
153			gpio-controller;
154			ngpios = <32>;
155		};
156
157		dmac0: dma-controller@50000000 {
158			compatible = "snps,axi-dma-1.01a";
159			reg = <0x50000000 0x1000>;
160			interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
161			#dma-cells = <1>;
162			clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
163			clock-names = "core-clk", "cfgr-clk";
164			resets = <&sysrst K210_RST_DMA>;
165			dma-channels = <6>;
166			snps,dma-masters = <2>;
167			snps,priority = <0 1 2 3 4 5>;
168			snps,data-width = <5>;
169			snps,block-size = <0x200000 0x200000 0x200000
170					   0x200000 0x200000 0x200000>;
171			snps,axi-max-burst-len = <256>;
172		};
173
174		apb0: bus@50200000 {
175			#address-cells = <1>;
176			#size-cells = <1>;
177			compatible = "simple-pm-bus";
178			ranges = <0x50200000 0x50200000 0x200000>;
179			clocks = <&sysclk K210_CLK_APB0>;
180
181			gpio1: gpio@50200000 {
182				#address-cells = <1>;
183				#size-cells = <0>;
184				compatible = "snps,dw-apb-gpio";
185				reg = <0x50200000 0x80>;
186				clocks = <&sysclk K210_CLK_APB0>,
187					 <&sysclk K210_CLK_GPIO>;
188				clock-names = "bus", "db";
189				resets = <&sysrst K210_RST_GPIO>;
190
191				gpio1_0: gpio-port@0 {
192					#gpio-cells = <2>;
193					#interrupt-cells = <2>;
194					compatible = "snps,dw-apb-gpio-port";
195					reg = <0>;
196					interrupt-controller;
197					interrupts = <23>;
198					gpio-controller;
199					ngpios = <8>;
200				};
201			};
202
203			uart1: serial@50210000 {
204				compatible = "snps,dw-apb-uart";
205				reg = <0x50210000 0x100>;
206				interrupts = <11>;
207				clocks = <&sysclk K210_CLK_UART1>,
208					 <&sysclk K210_CLK_APB0>;
209				clock-names = "baudclk", "apb_pclk";
210				resets = <&sysrst K210_RST_UART1>;
211				reg-io-width = <4>;
212				reg-shift = <2>;
213				dcd-override;
214				dsr-override;
215				cts-override;
216				ri-override;
217			};
218
219			uart2: serial@50220000 {
220				compatible = "snps,dw-apb-uart";
221				reg = <0x50220000 0x100>;
222				interrupts = <12>;
223				clocks = <&sysclk K210_CLK_UART2>,
224					 <&sysclk K210_CLK_APB0>;
225				clock-names = "baudclk", "apb_pclk";
226				resets = <&sysrst K210_RST_UART2>;
227				reg-io-width = <4>;
228				reg-shift = <2>;
229				dcd-override;
230				dsr-override;
231				cts-override;
232				ri-override;
233			};
234
235			uart3: serial@50230000 {
236				compatible = "snps,dw-apb-uart";
237				reg = <0x50230000 0x100>;
238				interrupts = <13>;
239				clocks = <&sysclk K210_CLK_UART3>,
240					 <&sysclk K210_CLK_APB0>;
241				clock-names = "baudclk", "apb_pclk";
242				resets = <&sysrst K210_RST_UART3>;
243				reg-io-width = <4>;
244				reg-shift = <2>;
245				dcd-override;
246				dsr-override;
247				cts-override;
248				ri-override;
249			};
250
251			spi2: spi@50240000 {
252				compatible = "canaan,k210-spi";
253				spi-slave;
254				reg = <0x50240000 0x100>;
255				#address-cells = <0>;
256				#size-cells = <0>;
257				interrupts = <3>;
258				clocks = <&sysclk K210_CLK_SPI2>,
259					 <&sysclk K210_CLK_APB0>;
260				clock-names = "ssi_clk", "pclk";
261				resets = <&sysrst K210_RST_SPI2>;
262			};
263
264			i2s0: i2s@50250000 {
265				compatible = "canaan,k210-i2s", "snps,designware-i2s";
266				reg = <0x50250000 0x200>;
267				interrupts = <5>;
268				clocks = <&sysclk K210_CLK_I2S0>;
269				clock-names = "i2sclk";
270				resets = <&sysrst K210_RST_I2S0>;
271			};
272
273			i2s1: i2s@50260000 {
274				compatible = "canaan,k210-i2s", "snps,designware-i2s";
275				reg = <0x50260000 0x200>;
276				interrupts = <6>;
277				clocks = <&sysclk K210_CLK_I2S1>;
278				clock-names = "i2sclk";
279				resets = <&sysrst K210_RST_I2S1>;
280			};
281
282			i2s2: i2s@50270000 {
283				compatible = "canaan,k210-i2s", "snps,designware-i2s";
284				reg = <0x50270000 0x200>;
285				interrupts = <7>;
286				clocks = <&sysclk K210_CLK_I2S2>;
287				clock-names = "i2sclk";
288				resets = <&sysrst K210_RST_I2S2>;
289			};
290
291			i2c0: i2c@50280000 {
292				compatible = "snps,designware-i2c";
293				reg = <0x50280000 0x100>;
294				interrupts = <8>;
295				clocks = <&sysclk K210_CLK_I2C0>,
296					 <&sysclk K210_CLK_APB0>;
297				clock-names = "ref", "pclk";
298				resets = <&sysrst K210_RST_I2C0>;
299			};
300
301			i2c1: i2c@50290000 {
302				compatible = "snps,designware-i2c";
303				reg = <0x50290000 0x100>;
304				interrupts = <9>;
305				clocks = <&sysclk K210_CLK_I2C1>,
306					 <&sysclk K210_CLK_APB0>;
307				clock-names = "ref", "pclk";
308				resets = <&sysrst K210_RST_I2C1>;
309			};
310
311			i2c2: i2c@502a0000 {
312				compatible = "snps,designware-i2c";
313				reg = <0x502A0000 0x100>;
314				interrupts = <10>;
315				clocks = <&sysclk K210_CLK_I2C2>,
316					 <&sysclk K210_CLK_APB0>;
317				clock-names = "ref", "pclk";
318				resets = <&sysrst K210_RST_I2C2>;
319			};
320
321			fpioa: pinmux@502b0000 {
322				compatible = "canaan,k210-fpioa";
323				reg = <0x502B0000 0x100>;
324				clocks = <&sysclk K210_CLK_FPIOA>,
325					 <&sysclk K210_CLK_APB0>;
326				clock-names = "ref", "pclk";
327				resets = <&sysrst K210_RST_FPIOA>;
328				canaan,k210-sysctl-power = <&sysctl 108>;
329			};
330
331			timer0: timer@502d0000 {
332				compatible = "snps,dw-apb-timer";
333				reg = <0x502D0000 0x14>;
334				interrupts = <14>;
335				clocks = <&sysclk K210_CLK_TIMER0>,
336					 <&sysclk K210_CLK_APB0>;
337				clock-names = "timer", "pclk";
338				resets = <&sysrst K210_RST_TIMER0>;
339			};
340
341			timer1: timer@502d0014 {
342				compatible = "snps,dw-apb-timer";
343				reg = <0x502D0014 0x14>;
344				interrupts = <15>;
345				clocks = <&sysclk K210_CLK_TIMER0>,
346					 <&sysclk K210_CLK_APB0>;
347				clock-names = "timer", "pclk";
348				resets = <&sysrst K210_RST_TIMER0>;
349			};
350
351			timer2: timer@502e0000 {
352				compatible = "snps,dw-apb-timer";
353				reg = <0x502E0000 0x14>;
354				interrupts = <16>;
355				clocks = <&sysclk K210_CLK_TIMER1>,
356					 <&sysclk K210_CLK_APB0>;
357				clock-names = "timer", "pclk";
358				resets = <&sysrst K210_RST_TIMER1>;
359			};
360
361			timer3: timer@502e0014 {
362				compatible = "snps,dw-apb-timer";
363				reg = <0x502E0014 0x114>;
364				interrupts = <17>;
365				clocks = <&sysclk K210_CLK_TIMER1>,
366					 <&sysclk K210_CLK_APB0>;
367				clock-names = "timer", "pclk";
368				resets = <&sysrst K210_RST_TIMER1>;
369			};
370
371			timer4: timer@502f0000 {
372				compatible = "snps,dw-apb-timer";
373				reg = <0x502F0000 0x14>;
374				interrupts = <18>;
375				clocks = <&sysclk K210_CLK_TIMER2>,
376					 <&sysclk K210_CLK_APB0>;
377				clock-names = "timer", "pclk";
378				resets = <&sysrst K210_RST_TIMER2>;
379			};
380
381			timer5: timer@502f0014 {
382				compatible = "snps,dw-apb-timer";
383				reg = <0x502F0014 0x14>;
384				interrupts = <19>;
385				clocks = <&sysclk K210_CLK_TIMER2>,
386					 <&sysclk K210_CLK_APB0>;
387				clock-names = "timer", "pclk";
388				resets = <&sysrst K210_RST_TIMER2>;
389			};
390		};
391
392		apb1: bus@50400000 {
393			#address-cells = <1>;
394			#size-cells = <1>;
395			compatible = "simple-pm-bus";
396			ranges = <0x50400000 0x50400000 0x40100>;
397			clocks = <&sysclk K210_CLK_APB1>;
398
399			wdt0: watchdog@50400000 {
400				compatible = "snps,dw-wdt";
401				reg = <0x50400000 0x100>;
402				interrupts = <21>;
403				clocks = <&sysclk K210_CLK_WDT0>,
404					 <&sysclk K210_CLK_APB1>;
405				clock-names = "tclk", "pclk";
406				resets = <&sysrst K210_RST_WDT0>;
407			};
408
409			wdt1: watchdog@50410000 {
410				compatible = "snps,dw-wdt";
411				reg = <0x50410000 0x100>;
412				interrupts = <22>;
413				clocks = <&sysclk K210_CLK_WDT1>,
414					 <&sysclk K210_CLK_APB1>;
415				clock-names = "tclk", "pclk";
416				resets = <&sysrst K210_RST_WDT1>;
417			};
418
419			sysctl: syscon@50440000 {
420				compatible = "canaan,k210-sysctl",
421					     "syscon", "simple-mfd";
422				reg = <0x50440000 0x100>;
423				clocks = <&sysclk K210_CLK_APB1>;
424				clock-names = "pclk";
425
426				sysclk: clock-controller {
427					#clock-cells = <1>;
428					compatible = "canaan,k210-clk";
429					clocks = <&in0>;
430				};
431
432				sysrst: reset-controller {
433					compatible = "canaan,k210-rst";
434					#reset-cells = <1>;
435				};
436
437				reboot: syscon-reboot {
438					compatible = "syscon-reboot";
439					regmap = <&sysctl>;
440					offset = <48>;
441					mask = <1>;
442					value = <1>;
443				};
444			};
445		};
446
447		apb2: bus@52000000 {
448			#address-cells = <1>;
449			#size-cells = <1>;
450			compatible = "simple-pm-bus";
451			ranges = <0x52000000 0x52000000 0x2000200>;
452			clocks = <&sysclk K210_CLK_APB2>;
453
454			spi0: spi@52000000 {
455				#address-cells = <1>;
456				#size-cells = <0>;
457				compatible = "canaan,k210-spi";
458				reg = <0x52000000 0x100>;
459				interrupts = <1>;
460				clocks = <&sysclk K210_CLK_SPI0>,
461					 <&sysclk K210_CLK_APB2>;
462				clock-names = "ssi_clk", "pclk";
463				resets = <&sysrst K210_RST_SPI0>;
464				reset-names = "spi";
465				num-cs = <4>;
466				reg-io-width = <4>;
467			};
468
469			spi1: spi@53000000 {
470				#address-cells = <1>;
471				#size-cells = <0>;
472				compatible = "canaan,k210-spi";
473				reg = <0x53000000 0x100>;
474				interrupts = <2>;
475				clocks = <&sysclk K210_CLK_SPI1>,
476					 <&sysclk K210_CLK_APB2>;
477				clock-names = "ssi_clk", "pclk";
478				resets = <&sysrst K210_RST_SPI1>;
479				reset-names = "spi";
480				num-cs = <4>;
481				reg-io-width = <4>;
482			};
483
484			spi3: spi@54000000 {
485				#address-cells = <1>;
486				#size-cells = <0>;
487				compatible = "snps,dwc-ssi-1.01a";
488				reg = <0x54000000 0x200>;
489				interrupts = <4>;
490				clocks = <&sysclk K210_CLK_SPI3>,
491					 <&sysclk K210_CLK_APB2>;
492				clock-names = "ssi_clk", "pclk";
493				resets = <&sysrst K210_RST_SPI3>;
494				reset-names = "spi";
495
496				num-cs = <4>;
497				reg-io-width = <4>;
498			};
499		};
500	};
501};
502